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#ifndef CYGONCE_HAL_PROC_INTR_H
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#define CYGONCE_HAL_PROC_INTR_H
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//==========================================================================
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//
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// proc_intr.h
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//
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// mcf5272 Processor variant interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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// Include any platform specific interrupt definitions.
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#include <cyg/hal/plf_intr.h>
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// Include for the SIM address (MCF5272_SIM).
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#include <cyg/hal/proc_arch.h>
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//---------------------------------------------------------------------------
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// Interrupt controller management
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// This chip has a programmable interrupt vector base which is different
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// from the vector base register (VBR). All interrupts from the interrupt
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// controller are offsets from the programmable interrupt vector register
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// (PIVR).
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#define HAL_PROG_INT_VEC_BASE 64
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// Vector numbers defined by the interrupt controller.
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// These are all relative to the interrupt vector base number.
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#define CYGNUM_HAL_VECTOR_USR_SPUR_INT (0 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_TMR1 (5 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_TMR2 (6 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_TMR3 (7 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_TMR4 (8 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_UART1 (9 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_UART2 (10 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_PROG_INT_VEC_BASE)
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//---------------------------------------------------------------------------
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// Interrupt controller macros.
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// Declare a mirror copy of the interrupt control registers used to set
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// interrupt priorities. In order to mask and unmask a specific interrupt, we
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// must be able to set its priority to zero and then restore it to ist
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// original priority. We use these locations to determine the level to
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// restore the interrupt to in the unmask macro.
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externC cyg_uint32 hal_icr_pri_mirror[4];
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// Block the interrupt associated with the given vector. To do this, we
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// set the interrupt priority level to zero for the specified interrupt. To
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// set the interrupt priority level, we simultaneously write a 1 to the
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// pending interrupt field. The other interrupts are unaffected. Disable all
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// interrupts while we access the hardware registers.
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _icr = _vec_offset / 8; \
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cyg_uint32 _icr_msk = 0xf0000000 >> ((_vec_offset % 8) * 4); \
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CYG_INTERRUPT_STATE _intr_state; \
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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MCF5272_SIM->intc.icr[_icr] &= _icr_msk ^ 0x77777777; \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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CYG_MACRO_END
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// Unblock the interrupt associated with the given vector. Set the
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// interrupt priority using the value from the icr mirror variable. Disable
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// all interrupts while we access the hardware registers.
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _icr = _vec_offset / 8; \
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cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
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cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
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cyg_uint32 _icr_val; \
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CYG_INTERRUPT_STATE _intr_state; \
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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_icr_val = MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
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_icr_val |= hal_icr_pri_mirror[_icr] & _icr_msk; \
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_icr_val |= 0x08 << _icr_msk_offset; \
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MCF5272_SIM->intc.icr[_icr] = _icr_val; \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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CYG_MACRO_END
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// Acknowledge the interrupt by writing a 1 to the corresponding
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// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave
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// all priority levels unchanged. Disable all interrupts while we access the
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// hardware registers.
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _icr = _vec_offset / 8; \
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cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \
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CYG_INTERRUPT_STATE _intr_state; \
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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MCF5272_SIM->intc.icr[_icr] &= _icr_msk | 0x77777777; \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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CYG_MACRO_END
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// Set the priority in the interrupt control register and the icr mirror.
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// Do not copy the icr mirror into the icr because some interrupts may be
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// masked. Disable all interrupts while we access the hardware registers.
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \
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CYG_MACRO_START \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _icr = _vec_offset / 8; \
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cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
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cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
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cyg_uint32 _icr_val = (0x08 | (_prilevel_ & 0x07)) << _icr_msk_offset; \
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CYG_INTERRUPT_STATE _intr_state; \
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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cyg_uint32 _mir_val = hal_icr_pri_mirror[_icr] & 0x77777777 & ~_icr_msk; \
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hal_icr_pri_mirror[_icr] = _mir_val | _icr_val; \
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_icr_val |= MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
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MCF5272_SIM->intc.icr[_icr] = _icr_val; \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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CYG_MACRO_END
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// Set/clear the interrupt transition register bit. Disable all
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// interrupts while we access the hardware registers.
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// WARNING: It seems that manual currently has the polarity of this bit
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// wrong.
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \
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CYG_MACRO_START \
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if (!(_leveltriggered_)) \
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{ \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \
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CYG_INTERRUPT_STATE _intr_state; \
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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if (_up_) \
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{ \
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MCF5272_SIM->intc.pitr |= _itr_bit; \
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} \
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else \
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{ \
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MCF5272_SIM->intc.pitr &= ~_itr_bit; \
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} \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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} \
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CYG_MACRO_END
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PROC_INTR_H
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