OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [m68k/] [mcf52xx/] [var/] [v2_0/] [src/] [var_startup.c] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//==========================================================================
2
//####ECOSGPLCOPYRIGHTBEGIN####
3
// -------------------------------------------
4
// This file is part of eCos, the Embedded Configurable Operating System.
5
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
6
//
7
// eCos is free software; you can redistribute it and/or modify it under
8
// the terms of the GNU General Public License as published by the Free
9
// Software Foundation; either version 2 or (at your option) any later version.
10
//
11
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
12
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
// for more details.
15
//
16
// You should have received a copy of the GNU General Public License along
17
// with eCos; if not, write to the Free Software Foundation, Inc.,
18
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19
//
20
// As a special exception, if other files instantiate templates or use macros
21
// or inline functions from this file, or you compile this file and link it
22
// with other works to produce a work based on this file, this file does not
23
// by itself cause the resulting work to be covered by the GNU General Public
24
// License. However the source code for this file must still be made available
25
// in accordance with section (3) of the GNU General Public License.
26
//
27
// This exception does not invalidate any other reasons why a work based on
28
// this file might be covered by the GNU General Public License.
29
//
30
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
31
// at http://sources.redhat.com/ecos/ecos-license/
32
// -------------------------------------------
33
//####ECOSGPLCOPYRIGHTEND####
34
//==========================================================================
35
 
36
#include <cyg/infra/cyg_type.h>
37
#include <pkgconf/hal.h>
38
#include <cyg/hal/hal_startup.h>
39
#include <cyg/hal/hal_memmap.h>
40
#include <cyg/hal/hal_arch.h>
41
 
42
/*****************************************************************************
43
var_init_cache_acr --  Initialize the cache and access control registers
44
 
45
INPUT:
46
 
47
OUTPUT:
48
 
49
RETURN VALUE:
50
 
51
     None
52
 
53
*****************************************************************************/
54
static void var_init_cache_acr(void)
55
{
56
 
57
    //   Invalidate and disable the cache and ACRs.
58
 
59
    mcf52xx_wr_cacr((CYG_WORD32)0x01000000);
60
    mcf52xx_wr_acr0((CYG_WORD32)0);
61
    mcf52xx_wr_acr1((CYG_WORD32)0);
62
 
63
    //   Call a routine to set  up  the  cache  and  ACRs  for  this  specific
64
    // platform.
65
 
66
    plf_init_cache_acr();
67
 
68
}
69
 
70
/*****************************************************************************
71
var_reset --  Variant-specific reset vector initialization routine
72
 
73
     This routine must be called with interrupts disabled.
74
 
75
INPUT:
76
 
77
OUTPUT:
78
 
79
RETURN VALUE:
80
 
81
     None
82
 
83
*****************************************************************************/
84
void var_reset(void)
85
{
86
 
87
    //   Initialize the processor's vector base register.
88
 
89
    mcf52xx_wr_vbr((CYG_WORD32)__ramvec_start);
90
 
91
    //   Initialize the cache and access control registers.
92
 
93
    var_init_cache_acr();
94
 
95
    //   Do any processor-specific reset initialization.
96
 
97
    proc_reset();
98
}
99
 
100
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.