OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [arch/] [v2_0/] [include/] [mips-stub.h] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_MIPS_STUB_H
2
#define CYGONCE_HAL_MIPS_STUB_H
3
//========================================================================
4
//
5
//      mips-stub.h
6
//
7
//      MIPS-specific definitions for generic stub
8
//
9
//========================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later version.
18
//
19
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22
// for more details.
23
//
24
// You should have received a copy of the GNU General Public License along
25
// with eCos; if not, write to the Free Software Foundation, Inc.,
26
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27
//
28
// As a special exception, if other files instantiate templates or use macros
29
// or inline functions from this file, or you compile this file and link it
30
// with other works to produce a work based on this file, this file does not
31
// by itself cause the resulting work to be covered by the GNU General Public
32
// License. However the source code for this file must still be made available
33
// in accordance with section (3) of the GNU General Public License.
34
//
35
// This exception does not invalidate any other reasons why a work based on
36
// this file might be covered by the GNU General Public License.
37
//
38
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39
// at http://sources.redhat.com/ecos/ecos-license/
40
// -------------------------------------------
41
//####ECOSGPLCOPYRIGHTEND####
42
//========================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):     Red Hat, nickg
46
// Contributors:  Red Hat, nickg, dmoseley
47
// Date:          1998-06-08
48
// Purpose:       
49
// Description:   MIPS-specific definitions for generic stub
50
// Usage:         
51
//
52
//####DESCRIPTIONEND####
53
//
54
//========================================================================
55
 
56
 
57
#include <pkgconf/system.h>
58
#include <pkgconf/hal_mips.h>
59
 
60
#include <cyg/hal/hal_io.h>
61
 
62
#ifdef __cplusplus
63
extern "C" {
64
#endif
65
 
66
#if defined(CYGPKG_HAL_MIPS_GDB_REPORT_CP0)
67
#define NUMREGS   107
68
#else
69
#define NUMREGS    90
70
#endif
71
 
72
#if defined(__mips64)
73
  // The simple case of 64-bit regs represented to GDB as 64-bit regs.
74
 
75
  #define REGSIZE(X) 8
76
  typedef unsigned long long target_register_t;
77
 
78
# ifdef CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT
79
#  error __mips64 & CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT
80
# endif
81
 
82
#elif defined(CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT)
83
 
84
    // This is a catch-all for the common case:
85
    // Even though we are only working with 32 bit registers, GDB expects 64 bits
86
#define REGSIZE(X) 8
87
typedef unsigned long target_register_t;
88
    // We need to sign-extend the registers so GDB doesn't get confused.
89
#define CYGARC_SIGN_EXTEND_REGISTERS
90
 
91
    // The following platform-specific cases can be removed as/when/if they
92
    // get modified to implement CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT
93
 
94
#elif defined(CYGPKG_HAL_MIPS_VR4300)
95
  // Even though we are only working with 32 bit registers, GDB expects 64 bits
96
  #define REGSIZE(X) 8
97
  typedef unsigned long long target_register_t;
98
  // We need to sign-extend the registers so GDB doesn't get confused.
99
  #define CYGARC_SIGN_EXTEND_REGISTERS
100
#elif defined(CYGPKG_HAL_MIPS_TX49)
101
  // Even though we are only working with 32 bit registers, GDB expects 64 bits
102
  #define REGSIZE(X) 8
103
  typedef unsigned long target_register_t;
104
 
105
  // We need to sign-extend the registers so GDB doesn't get confused.
106
  #define CYGARC_SIGN_EXTEND_REGISTERS
107
#elif defined(CYGPKG_HAL_MIPS_RM7000)
108
  // Even though we are only working with 32 bit registers, GDB expects 64 bits
109
  #define REGSIZE(X) 8
110
  typedef unsigned long target_register_t;
111
 
112
  // We need to sign-extend the registers so GDB doesn't get confused.
113
  #define CYGARC_SIGN_EXTEND_REGISTERS
114
#elif 0 //defined(CYGPKG_HAL_MIPS_MIPS32)
115
  // Even though we are only working with 32 bit registers, GDB expects 64 bits
116
  #define REGSIZE(X) 8
117
  typedef unsigned long target_register_t;
118
 
119
  // We need to sign-extend the registers so GDB doesn't get confused.
120
  #define CYGARC_SIGN_EXTEND_REGISTERS
121
#else
122
 
123
  // The simplest case of 32-bit regs represented to GDB as 32-bit regs.
124
  #define REGSIZE(X) 4
125
  typedef unsigned long target_register_t;
126
#endif
127
 
128
enum regnames {
129
        REG_ZERO,   REG_AT,     REG_V0,     REG_V1,     REG_A0,     REG_A1,     REG_A2,     REG_A3,
130
        REG_T0,     REG_T1,     REG_T2,     REG_T3,     REG_T4,     REG_T5,     REG_T6,     REG_T7,
131
        REG_S0,     REG_S1,     REG_S2,     REG_S3,     REG_S4,     REG_S5,     REG_S6,     REG_S7,
132
        REG_T8,     REG_T9,     REG_K0,     REG_K1,     REG_GP,     REG_SP,     REG_S8,     REG_RA,
133
        REG_SR,     REG_LO,     REG_HI,     REG_BAD,    REG_CAUSE,  REG_PC,
134
        REG_CONFIG = 84,    REG_CACHE,  REG_DEBUG,  REG_DEPC,   REG_EPC
135
};
136
#define USE_LONG_NAMES_FOR_ENUM_REGNAMES
137
 
138
typedef enum regnames regnames_t;
139
 
140
/* Given a trap value TRAP, return the corresponding signal. */
141
extern int __computeSignal (unsigned int trap_number);
142
 
143
/* Return the SPARC trap number corresponding to the last-taken trap. */
144
extern int __get_trap_number (void);
145
 
146
/* Return the currently-saved value corresponding to register REG. */
147
extern target_register_t get_register (regnames_t reg);
148
 
149
/* Store VALUE in the register corresponding to WHICH. */
150
extern void put_register (regnames_t which, target_register_t value);
151
 
152
/* Set the currently-saved pc register value to PC. This also updates NPC
153
   as needed. */
154
#if !defined(SET_PC_PROTOTYPE_EXISTS) && !defined(set_pc)
155
#define SET_PC_PROTOTYPE_EXISTS
156
extern void set_pc (target_register_t pc);
157
#endif
158
 
159
/* Set things up so that the next user resume will execute one instruction.
160
   This may be done by setting breakpoints or setting a single step flag
161
   in the saved user registers, for example. */
162
#ifndef __single_step
163
void __single_step (void);
164
#endif
165
 
166
/* Clear the single-step state. */
167
void __clear_single_step (void);
168
 
169
extern int __is_bsp_syscall(void);
170
 
171
extern int hal_syscall_handler(void);
172
 
173
/* If the breakpoint we hit is in the breakpoint() instruction, return a
174
   non-zero value. */
175
#ifndef __is_breakpoint_function
176
extern int __is_breakpoint_function (void);
177
#endif
178
 
179
/* Skip the current instruction. */
180
extern void __skipinst (void);
181
 
182
extern void __install_breakpoints (void);
183
 
184
extern void __clear_breakpoints (void);
185
 
186
extern void __install_breakpoint_list (void);
187
 
188
extern void __clear_breakpoint_list (void);
189
 
190
#ifdef __cplusplus
191
}      /* extern "C" */
192
#endif
193
 
194
#endif // ifndef CYGONCE_HAL_MIPS_STUB_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.