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#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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// plf_intr.h
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//
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// Atlas Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour, dmoseley
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// Date: 2000-06-06
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for the Atlas board.
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//
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// Usage:
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// #include <cyg/hal/plf_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_io.h>
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// These are decoded via the IP bits of the cause
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// register when an external interrupt is delivered.
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#define CYGNUM_HAL_INTERRUPT_SER 0
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#define CYGNUM_HAL_INTERRUPT_TIM0 1
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#define CYGNUM_HAL_INTERRUPT_2 2
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#define CYGNUM_HAL_INTERRUPT_3 3
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#define CYGNUM_HAL_INTERRUPT_FPGA_RTC 4
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#define CYGNUM_HAL_INTERRUPT_COREHI 5
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#define CYGNUM_HAL_INTERRUPT_CORELO 6
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#define CYGNUM_HAL_INTERRUPT_7 7
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#define CYGNUM_HAL_INTERRUPT_PCIA 8
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#define CYGNUM_HAL_INTERRUPT_PCIB 9
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#define CYGNUM_HAL_INTERRUPT_PCIC 10
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#define CYGNUM_HAL_INTERRUPT_PCID 11
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#define CYGNUM_HAL_INTERRUPT_ENUM 12
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#define CYGNUM_HAL_INTERRUPT_DEG 13
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#define CYGNUM_HAL_INTERRUPT_ATXFAIL 14
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#define CYGNUM_HAL_INTERRUPT_INTA 15
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#define CYGNUM_HAL_INTERRUPT_INTB 16
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#define CYGNUM_HAL_INTERRUPT_INTC 17
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#define CYGNUM_HAL_INTERRUPT_INTD 18
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#define CYGNUM_HAL_INTERRUPT_SERR 19
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#define CYGNUM_HAL_INTERRUPT_HW1 20
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#define CYGNUM_HAL_INTERRUPT_HW2 21
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#define CYGNUM_HAL_INTERRUPT_HW3 22
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#define CYGNUM_HAL_INTERRUPT_HW4 23
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#define CYGNUM_HAL_INTERRUPT_HW5 24
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 24
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#define CYGNUM_HAL_ISR_COUNT 25
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#define CYGNUM_HAL_INTERRUPT_DEBUG_UART CYGNUM_HAL_INTERRUPT_SER
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_HW5
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Interrupt controller access.
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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// Array which stores the configured priority levels for the configured
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// interrupts.
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externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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{ \
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cyg_uint32 __vector = _vector_; \
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\
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if( (_vector_) < CYGNUM_HAL_INTERRUPT_HW1 ) \
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HAL_WRITE_UINT32( HAL_ATLAS_INTRSTEN, (1<<(_vector_)) ); \
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else \
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{ \
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__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \
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\
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(__vector) \
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: "$2", "$3" \
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); \
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} \
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}
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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{ \
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cyg_uint32 __vector = _vector_; \
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\
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if( (__vector) < CYGNUM_HAL_INTERRUPT_HW1 ) \
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{ \
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HAL_WRITE_UINT32( HAL_ATLAS_INTSETEN, (1<<(__vector)) ); \
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__vector = 0; \
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} \
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else \
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__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \
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\
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(__vector) \
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: "$2", "$3" \
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); \
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}
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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{ \
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cyg_uint32 __vector = _vector_; \
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\
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if( __vector >= CYGNUM_HAL_INTERRUPT_HW1 ) \
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__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \
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else \
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__vector = 0; \
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\
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asm volatile ( \
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"mfc0 $3,$13\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$13\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(__vector) \
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: "$2", "$3" \
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); \
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\
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}
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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{ \
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}
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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{ \
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}
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Control-C support.
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#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
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# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SER
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externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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# define HAL_CTRLC_ISR hal_ctrlc_isr
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#endif
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//----------------------------------------------------------------------------
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// Reset.
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#ifndef CYGHWR_HAL_RESET_DEFINED
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extern void hal_atlas_reset( void );
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#define CYGHWR_HAL_RESET_DEFINED
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#define HAL_PLATFORM_RESET() hal_atlas_reset()
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#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
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#endif // CYGHWR_HAL_RESET_DEFINED
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLF_INTR_H
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// End of plf_intr.h
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