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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [atlas/] [v2_0/] [src/] [plf_misc.c] - Blame information for rev 638

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//==========================================================================
2
//
3
//      plf_misc.c
4
//
5
//      HAL platform miscellaneous functions
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//==========================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):    nickg
44
// Contributors: nickg, jlarmour, dmoseley
45
// Date:         2000-06-06
46
// Purpose:      HAL miscellaneous functions
47
// Description:  This file contains miscellaneous functions provided by the
48
//               HAL.
49
//
50
//####DESCRIPTIONEND####
51
//
52
//========================================================================*/
53
 
54
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
55
#include <pkgconf/hal.h>
56
 
57
#include <cyg/infra/cyg_type.h>         // Base types
58
#include <cyg/infra/cyg_trac.h>         // tracing macros
59
#include <cyg/infra/cyg_ass.h>          // assertion macros
60
 
61
#include <cyg/hal/hal_arch.h>           // architectural definitions
62
 
63
#include <cyg/hal/hal_intr.h>           // Interrupt handling
64
 
65
#include <cyg/hal/hal_cache.h>          // Cache handling
66
 
67
#include <cyg/hal/hal_if.h>
68
 
69
 
70
#if defined(CYGPKG_IO_PCI)
71
#include <cyg/io/pci_hw.h>
72
#include <cyg/io/pci.h>
73
#endif
74
 
75
/*------------------------------------------------------------------------*/
76
 
77
#if defined(CYGPKG_CYGMON)
78
#include CYGHWR_MEMORY_LAYOUT_H
79
extern unsigned long cygmon_memsize;
80
#endif
81
 
82
void hal_platform_init(void)
83
{
84
    HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, 0xff);
85
#if defined(CYGPKG_CYGMON)
86
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
87
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'C');
88
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'Y');
89
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'G');
90
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'M');
91
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'O');
92
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 'N');
93
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
94
#elif defined(CYGPKG_REDBOOT)
95
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, 'R');
96
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'e');
97
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'd');
98
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'B');
99
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
100
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'o');
101
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 't');
102
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
103
#else
104
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
105
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
106
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e');
107
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C');
108
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
109
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 's');
110
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
111
    HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
112
#endif
113
 
114
    // Set up eCos/ROM interfaces
115
    hal_if_init();
116
 
117
    HAL_ICACHE_INVALIDATE_ALL();
118
    HAL_ICACHE_ENABLE();
119
    HAL_DCACHE_INVALIDATE_ALL();
120
    HAL_DCACHE_ENABLE();
121
 
122
#if defined(CYGPKG_CYGMON)
123
    {
124
        // Store the BSP memory info
125
        unsigned long * ram_real_base = (unsigned long *)0x80000000;
126
        unsigned long memsize = *ram_real_base;
127
        // Adjust memsize for the interrupt vectors reserved space
128
        memsize -= (CYGMEM_REGION_ram - (unsigned long)ram_real_base);
129
        cygmon_memsize = memsize;
130
    }
131
 
132
    {
133
        //
134
        // Go ahead and enable IM[2] (ie HWInt[0]) so that we get interrupts 
135
        // from the external devices.  The device interrupts will still be
136
        // disabled in the CBUS FPGA interrupt controller, so this will not
137
        // cause spurious interrupts.
138
        // It is still up to the device drivers to enable the interrupts in
139
        // the interrupt controller
140
        //
141
        register unsigned long status;
142
        asm volatile (" mfc0 %0, $12" : "=r" (status) : );
143
        status |= SR_IBIT3;
144
        asm volatile (" mtc0 %0, $12" : : "r" (status));
145
    }
146
#endif
147
}
148
 
149
 
150
/*------------------------------------------------------------------------*/
151
/* Reset support                                                          */
152
 
153
void hal_atlas_reset(void)
154
{
155
    *HAL_ATLAS_SOFTRES = HAL_ATLAS_GORESET;
156
}
157
 
158
/*------------------------------------------------------------------------*/
159
/* Syscall support                                                        */
160
#ifdef CYGPKG_CYGMON
161
// Cygmon provides syscall handling for this board
162
#include <cyg/hal/hal_stub.h>
163
int __get_syscall_num (void)
164
{
165
    return SIGSYS;
166
}
167
#endif
168
 
169
 
170
/*------------------------------------------------------------------------*/
171
/* PCI support                                                            */
172
#if defined(CYGPKG_IO_PCI)
173
 
174
#define PCIMEM_START    0x08000000 // PCI memory address
175
#define PCIMEM_SIZE     0x10000000 //   256 MByte
176
#define PCIIO_START     0x18000000 // PCI io address
177
#define PCIIO_SIZE      0x03E00000 //    62 MByte
178
 
179
static int __check_bar(cyg_uint32 addr, cyg_uint32 size)
180
{
181
    int n;
182
 
183
    for (n = 0; n <= 31; n++)
184
        if (size == (1 << n)) {
185
            /* Check that address is naturally aligned */
186
            if (addr != (addr & ~(size-1)))
187
                return 0;
188
            return size - 1;
189
        }
190
    return 0;
191
}
192
 
193
 
194
// One-time PCI initialization.
195
 
196
void cyg_hal_plf_pci_init(void)
197
{
198
    cyg_uint32 bar_ena, start10, start32, end, size;
199
    cyg_uint8  next_bus;
200
 
201
    // Setup for bus mastering
202
    cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
203
                                    CYG_PCI_CFG_COMMAND,
204
                                    CYG_PCI_CFG_COMMAND_IO |
205
                                    CYG_PCI_CFG_COMMAND_MEMORY |
206
                                    CYG_PCI_CFG_COMMAND_MASTER |
207
                                    CYG_PCI_CFG_COMMAND_PARITY |
208
                                    CYG_PCI_CFG_COMMAND_SERR);
209
 
210
    // Setup latency timer field
211
    cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
212
                                   CYG_PCI_CFG_LATENCY_TIMER, 6);
213
 
214
    // Disable all BARs
215
    bar_ena = 0x1ff;
216
 
217
    // Check for active SCS10
218
    start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << 21;
219
    end   = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << 21;
220
    if (end > start10) {
221
        if ((size = __check_bar(start10, end - start10)) != 0) {
222
            // Enable BAR
223
            HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
224
            bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
225
        }
226
    }
227
 
228
    // Check for active SCS32
229
    start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << 21;
230
    end   = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << 21;
231
    if (end > start32) {
232
        if ((size = __check_bar(start32, end - start32)) != 0) {
233
            // Enable BAR
234
            HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
235
            bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
236
        }
237
    }
238
 
239
    bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
240
    HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
241
 
242
 
243
    cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
244
                                    CYG_PCI_CFG_BAR_0, 0xffffffff);
245
 
246
    end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
247
                                         CYG_PCI_CFG_BAR_0);
248
 
249
    cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
250
                                    CYG_PCI_CFG_BAR_0, start10);
251
 
252
 
253
    cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
254
                                    CYG_PCI_CFG_BAR_1, 0xffffffff);
255
 
256
    end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
257
                                         CYG_PCI_CFG_BAR_1);
258
 
259
    cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
260
                                    CYG_PCI_CFG_BAR_1, start32);
261
 
262
 
263
#if 0  // FIXME
264
 
265
    // SAA9730 was previously initialized just enough to use I2C bus
266
    // during SDRAM configuration. We reset it here so generic PCI
267
    // library can deal with it.
268
    *((volatile unsigned *)(HAL_GALILEO_PCI0_MEM0_BASE + HAL_SAA9730_SYSRESET_OFFSET))
269
      = HAL_SAA9730_SYSRESET_ALL;
270
#endif
271
 
272
    // Configure PCI bus.
273
    next_bus = 1;
274
    cyg_pci_set_memory_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE));
275
    cyg_pci_set_io_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE));
276
    cyg_pci_configure_bus(0, &next_bus);
277
}
278
 
279
 
280
// Check for configuration error.
281
static int pci_config_errcheck(void)
282
{
283
    cyg_uint32  irq;
284
 
285
    // Check for master or target abort
286
    irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET);
287
 
288
    if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) {
289
        // Error. Clear bits.
290
        HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET,
291
                           ~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT));
292
        return 1;
293
    }
294
    return 0;
295
}
296
 
297
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
298
                                           cyg_uint32 devfn,
299
                                           cyg_uint32 offset)
300
{
301
    cyg_uint32 config_data;
302
 
303
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
304
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
305
                       (bus << 16) | (devfn << 8) | offset);
306
 
307
    config_data = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
308
 
309
    if (pci_config_errcheck())
310
        return 0xffffffff;
311
    return config_data;
312
}
313
 
314
cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
315
                                          cyg_uint32 devfn,
316
                                          cyg_uint32 offset)
317
{
318
    cyg_uint32 config_dword;
319
 
320
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
321
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
322
                       (bus << 16) | (devfn << 8) | (offset & ~3));
323
 
324
    config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
325
 
326
    if (pci_config_errcheck())
327
        return 0xffff;
328
    return (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff);
329
}
330
 
331
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
332
                                         cyg_uint32 devfn,
333
                                         cyg_uint32 offset)
334
{
335
    cyg_uint32 config_dword;
336
 
337
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
338
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
339
                       (bus << 16) | (devfn << 8) | (offset & ~3));
340
 
341
    config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
342
 
343
    if (pci_config_errcheck())
344
        return 0xff;
345
    return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
346
}
347
 
348
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
349
                                      cyg_uint32 devfn,
350
                                      cyg_uint32 offset,
351
                                      cyg_uint32 data)
352
{
353
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
354
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
355
                       (bus << 16) | (devfn << 8) | offset);
356
 
357
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data);
358
 
359
    (void)pci_config_errcheck();
360
}
361
 
362
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
363
                                     cyg_uint32 devfn,
364
                                     cyg_uint32 offset,
365
                                     cyg_uint16 data)
366
{
367
    cyg_uint32 config_dword, shift;
368
 
369
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
370
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
371
                       (bus << 16) | (devfn << 8) | (offset & ~3));
372
 
373
    config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
374
    if (pci_config_errcheck())
375
        return;
376
 
377
    shift = (offset & 3) * 8;
378
    config_dword &= ~(0xffff << shift);
379
    config_dword |= (data << shift);
380
 
381
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
382
 
383
    (void)pci_config_errcheck();
384
}
385
 
386
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
387
                                     cyg_uint32 devfn,
388
                                     cyg_uint32 offset,
389
                                     cyg_uint8  data)
390
{
391
    cyg_uint32 config_dword, shift;
392
 
393
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
394
                       HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
395
                       (bus << 16) | (devfn << 8) | (offset & ~3));
396
 
397
    config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
398
    if (pci_config_errcheck())
399
        return;
400
 
401
    shift = (offset & 3) * 8;
402
    config_dword &= ~(0xff << shift);
403
    config_dword |= (data << shift);
404
 
405
    HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
406
 
407
    (void)pci_config_errcheck();
408
}
409
#endif  // defined(CYGPKG_IO_PCI)
410
 
411
/*------------------------------------------------------------------------*/
412
/* End of plf_misc.c                                                      */

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