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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [idt32334/] [v2_0/] [src/] [var_intr.c] - Blame information for rev 174

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//==========================================================================
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//
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//      var_intr.c
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//
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//      IDT3233x variant interrupt handlers
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    tmichals
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// Contributors: tmichals
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// Date:         2002-09-20
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// Purpose:      IDT 3233x variant interrupt handlers
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// Description:  This file contains code to handle interrupt related issues
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//               on the idt 3233x variant.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/system.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include CYGHWR_MEMORY_LAYOUT_H
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#include <cyg/infra/cyg_type.h>         // Base types
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#include <cyg/hal/hal_io.h>             // IO macros
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#include <cyg/hal/hal_stub.h>           // Stub macros
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#include <cyg/hal/hal_if.h>             // calling interface API
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#include <cyg/hal/hal_arch.h>           // Register state info
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_intr.h>           // Interrupt names
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#include <cyg/hal/hal_cache.h>
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/* This is the Reference board configuration */
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#include <cyg/hal/idt79rc233x.h>
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#include <cyg/infra/diag.h>             // diag_printf
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#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
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typedef cyg_uint32 cyg_ISR(cyg_uint32 vector, CYG_ADDRWORD data);
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extern void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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static inline cyg_uint32
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hal_call_isr (cyg_uint32 vector)
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{
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    cyg_ISR *isr;
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    CYG_ADDRWORD data;
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    cyg_uint32 isr_ret;
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    isr = (cyg_ISR*) hal_interrupt_handlers[vector];
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    data = hal_interrupt_data[vector];
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    isr_ret = (*isr) (vector, data);
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#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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    if (isr_ret & CYG_ISR_CALL_DSR) {
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        cyg_interrupt_post_dsr (hal_interrupt_objects[vector]);
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    }
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#endif
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    return isr_ret & ~CYG_ISR_CALL_DSR;
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}
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/* This is only for expansion interrupts */
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void cyg_hal_interrupt_mask ( cyg_uint32 vector )
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{
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    cyg_uint32 reg, _old;
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    /* done to void race conditions */
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    HAL_DISABLE_INTERRUPTS(_old);
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    switch (vector)
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        {
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        case CYGNUM_HAL_INTERRUPT_SIO_0:
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            HAL_WRITE_UINT32(INTR_COM0_REG, 0);
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            HAL_READ_UINT32(INTR_MASK_REG, reg);
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            HAL_WRITE_UINT32(INTR_MASK_REG, (reg & (~(1 << SERIAL_PORT0_GROUP))));
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            break;
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        case CYGNUM_HAL_INTERRUPT_SIO_1:
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            HAL_WRITE_UINT32(INTR_COM1_REG, 0);
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            HAL_READ_UINT32(INTR_MASK_REG, reg);
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            HAL_WRITE_UINT32(INTR_MASK_REG, (reg & (~(1 << SERIAL_PORT1_GROUP))));
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            break;
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        default:
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            HAL_INTERRUPT_MASK_CPU(vector);
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        }
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    HAL_RESTORE_INTERRUPTS(_old);
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    return;
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}
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void cyg_hal_interrupt_unmask( cyg_uint32 vector)
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{
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    cyg_uint32 reg, _old;
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    /* done to void race conditions */
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    HAL_DISABLE_INTERRUPTS(_old);
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    switch (vector)
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        {
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        case CYGNUM_HAL_INTERRUPT_SIO_0:
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            HAL_WRITE_UINT32(INTR_COM0_REG, 1);
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            HAL_READ_UINT32(INTR_MASK_REG, reg);
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            HAL_WRITE_UINT32(INTR_MASK_REG, (reg | ((1 << SERIAL_PORT0_GROUP))));
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            break;
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        case CYGNUM_HAL_INTERRUPT_SIO_1:
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            HAL_WRITE_UINT32(INTR_COM1_REG, 1);
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            HAL_READ_UINT32(INTR_MASK_REG, reg);
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            HAL_WRITE_UINT32(INTR_MASK_REG, (reg | ((1 << SERIAL_PORT1_GROUP))));
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            break;
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        default:
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            HAL_INTERRUPT_UNMASK_CPU(vector);
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        }
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    HAL_RESTORE_INTERRUPTS(_old);
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    return;
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}
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void cyg_hal_interrupt_acknowledge (cyg_uint32 vector)
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{
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    cyg_uint32 reg, _old;
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    switch (vector)
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        {
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        case CYGNUM_HAL_INTERRUPT_SIO_0:
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            HAL_WRITE_UINT32(INTR_CLEAR_COM0, 1);
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            break;
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        case CYGNUM_HAL_INTERRUPT_SIO_1:
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            HAL_WRITE_UINT32(INTR_CLEAR_COM1, 1);
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            break;
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        default:
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            HAL_INTERRUPT_ACKNOWLEDGE_CPU(vector);
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        }
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}
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externC cyg_uint32
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hal_extended_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
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{
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    cyg_uint32 isrRet;
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    cyg_uint32 pendingIsr;
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    cyg_uint32 isrNum;
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    HAL_READ_UINT32 (INTR_STATUS_PTR, pendingIsr);
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    for (isrNum=0; isrNum <=31; isrNum)
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        if ( (1 << isrNum) & pendingIsr)
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            break;
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    if (pendingIsr) {
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        isrRet = hal_call_isr (CYGNUM_LAST_IDT_INTERRUPT + isrNum);
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        if (isrRet & CYG_ISR_HANDLED)
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            return isrRet;
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    }
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    return 0;
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}
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externC void
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hal_variant_IRQ_init(void)
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{
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    HAL_INTERRUPT_MASK (CYGNUM_EXPANSION);
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    /* clear the mask register */
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    HAL_WRITE_UINT32(INTR_MASK_REG, 0); /* all expansion interrupts are masked */
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    HAL_INTERRUPT_ATTACH (CYGNUM_EXPANSION, &hal_extended_isr, 0, 0);
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    HAL_INTERRUPT_UNMASK (CYGNUM_EXPANSION);
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}
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externC void
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hal_IRQ_init(void)
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{
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    int i;
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    /* yes this is a quick fix; arch.inc should be changed, but this is
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     * good enough for now */
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    for (i=0; i <= CYGNUM_HAL_INTERRUPT_5;++i )
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                HAL_INTERRUPT_MASK (i);
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    hal_variant_IRQ_init();
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}
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// EOF var_intr.c

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