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##=============================================================================
##
##      platform.S
##
##      MIPS IDT platform code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):    tmichals
## Contributors: nickg
## Date:         2002-10-02
## Purpose:
## Description:  MIPS IDT platform code
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#endif
 
#include 
#include 
 
 
FUNC_START(hal_memc_setup)
#define PIO_BASE_ADDR     0xb8000600
#define PIO_DC_SET        0x00500050
#define PIO_DC_MASK       0xff0fff0f
 
                li      t0,PIO_BASE_ADDR
                lw      t1,0x4(t0)
                nop
                li      t2,PIO_DC_MASK          #mask the UART bits
                and     t1,t1,t2
                nop
                li      t2,PIO_DC_SET           #rx0=rx1=input, tx0=tx1=output
                or      t1,t1,t2
                nop
                sw      t1,0x4(t0)
 
 
                li      t0,PORT_WIDTH_CNTL_REG /* Set PortWidth and Bus parameters */
                li      t1,PORT_WIDTH_CNTL_VAL
                sw      t1,0(t0)
 
                li      t0,BUS_TURN_AROUND_CNTRL_REG
                li      t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles.  0x18000000*/
                sw      t1,0(t0)
 
                li      t0,BUS_TURN_AROUND_REG
                li      t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0xffffe204*/
                sw      t1,0(t0)
 
 
                li      t0,ADDRESS_LATCH_TIMING_REG
                li      t1,ADDRESS_LATCH_TIMING_VAL
                sw      t1,0(t0)
 
 
 
/* CHIP SELECT 0 for FLASH */
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG0
        sw      t1,0(t0)                /* 0x18000080 */
        li      t1,MBM_REG0
        sw      t1,0x4(t0)              /* 0x18000084 */
        li      t0,MEM_CTL_BASE
        li      t1,MCR_CS0_BS
        sw      t1,0(t0)                /* 0x18000200 */
 
/* CHIP SELECT 1 for FLASH */
 
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG1
        sw      t1,8(t0)                /* 0x18000088 */
        li      t1,MBM_REG1             /* 0x1800008C */
        sw      t1,0xc(t0)
        li      t0,MEM_CTL_BASE
        li      t1,MCR_CS1_BS           /* chip select 2 for other flash */
        sw      t1,0x4(t0)              /* 0x18000204 */
 
/* CHIP SELECT 2*/
                li      t1,MCR_CS2_BS
                sw      t1,0x8(t0)
 
/* CHIP SELECT 3*/
                li      t1,MCR_CS3_BS
                sw      t1,0xc(t0)
 
 
/* CHIP SELECT 4*/
                li      t1,MCR_CS4_BS
                sw      t1,0x10(t0)
 
 
/* CHIP SELECT 5*/
                li      t1,MCR_CS5_BS
                sw      t1,0x14(t0)
 
 
 
                li      t0,RHEA_IREG_BASE
                li      t1,DISABLE_TIMER
                sw      t1,0x730(t0)
 
                li      t1,0
                sw      t1,0x310(t0)
 
 
/* SDRAM Initialization:- Start Here!  */
        li      t1,DRAM_BNK0_BASE
        sw      t1,0xc0(t0)
        li      t1,DRAM_BNK1_BASE
        sw      t1,0xc8(t0)
        li      t1,DRAM_BNK2_BASE
        sw      t1,0xd0(t0)
        li      t1,DRAM_BNK3_BASE
        sw      t1,0xd8(t0)
 
        li      t1,DRAM_BNK0_MASK
        sw      t1,0xc4(t0)
        li      t1,DRAM_BNK1_MASK
        sw      t1,0xcc(t0)
        li      t1,DRAM_BNK2_MASK
        sw      t1,0xd4(t0)
        li      t1,DRAM_BNK3_MASK
        sw      t1,0xdc(t0)
 
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG1
        sw      t1,0x8(t0)
        li      t1,MBM_REG1
        sw      t1,0xc(t0)
 
        li      t0,TIMER_BASE
        li      t1,DISABLE_TIMER
        sw      t1,0x60(t0)
                nop
        li      t1,0x0
        sw      t1,0x64(t0)
        li      t1,CPU_BERR_BS
        sw      t1,0x48(t0)
        li      t1,IP_BERR_BS
        sw      t1,0x58(t0)
 
 
        li      t0,RHEA_IREG_BASE
        li      t1,SDRAM_CR_BS
        sw      t1,0x300(t0)
 
        li      t2,2
        li      t3,0
1:
        li      t1,SDRAM_PC_VAL
        sw      t1,0x300(t0)
        nop
        li      t4,SDRAM_TEST_PATTERN
        li      t5,K1BASE | DRAM_BNK0_BASE
        sw      t4,0x1000(t5)
        addu    t3,1
        bne     t3,t2,1b
                nop
 
        li      t2,2
        li      t3,0
1:
        li      t1,SDRAM_RFRSH_CMD
        sw      t1,0x300(t0)
        sw      t4,0x0(t5)
        addu    t3,1
        bne     t3,t2,1b
                nop
 
 
        li      t1,SDRAM_MODE_REG
        sw      t1,0x300(t0)
        sw      t4,0x80(t5)
 
        li      t0,TIMER_BASE
        li      t1,DRAM_RF_CMPR_BS
        sw      t1,0x68(t0)
        li      t1,ENABLE_TIMER
        sw      t1,0x60(t0)
 
 
       /* Delay for Sdram to stabilise with fast refresh */
        li      t2, 0x2FF00
1:
        subu    t2, 1
        bne     t2, zero,1b
        nop
 
       /* Change the Sdram refresh to a standard refresh */
        li      t0,TIMER_BASE
        li      t1,DRAM_RF_CMPR_SE_BS
        sw      t1,0x68(t0)
 
/* SDRAM Initialization : End Here !  */
 
 
                jr      ra
                nop
 
FUNC_END(hal_memc_setup)
 
 
FUNC_START(hal_setTlbEntry)
         .set noreorder
                mtc0 a0,C0_INX
                mtc0 a1,C0_TLBHI
                mtc0 a2,C0_TLBLO0
                mtc0 a3,C0_TLBLO1
                nop
                nop
                tlbwi
                nop
.set reorder
 
                j ra
         nop
FUNC_END(hal_setTlbEntry)
 
FUNC_START(hal_setPageSize)
        .set noreorder
        mtc0  a0,C0_PAGEMASK
        nop
        nop
        .set reorder
        j    ra
        nop
FUNC_END(hal_setPageSize)
 
 
 
 
FUNC_START (hal_sysConfigOutByte)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      li   t2,0x3
      and  a2,t2
      sw   a0,0x0(t0)
      xori a2,0x3
      or   t1,a2
      sb   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END(hal_sysConfigOutByte)
 
 
 
FUNC_START(hal_sysConfigOutHalfWord)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      li   t2,0x3
      and  a2,t2
      sw   a0,0x0(t0)
      xori a2,0x2
      or   t1,a2
      sh   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END (hal_sysConfigOutHalfWord)
 
FUNC_START (hal_sysConfigOutWord)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      sw   a0,0x0(t0)
      sw   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END (hal_sysConfigOutWord)
 
 
/*
 * Function:
 *      unsigned char sysConfigInByte (int pciConfigAddress) ;
 * Inputs:
 *      a0 - pciConfigAddress
 * Outputs:
 *      v0 - byte read from PCI Configuration space.
 */
 FUNC_START (hal_sysConfigInByte)
sysConfigInByte:
        li      t0, 0xb8000000  /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        andi    t1, a0, 0x00000003      /* t1 = PCI config space byte offset. */
        xor     t2, t1, a0              /* t2 = PCI config address of   */
                                        /*      longword containing byte. */
        xori    t1, 0x00000003  /* t1 = big endian byte offset. */
                                        /*      offset 0 -> 3 */
                                        /*      offset 1 -> 2 */
                                        /*      offset 2 -> 1 */
                                        /*      offset 3 -> 0 */
        or      t1, t0                  /* t1 = byte corrected PCI config */
                                        /*      data address. */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      t2, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lbu     v0, 0x2cfc (t1)         /* v0 = PCI config space byte read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END (hal_sysConfigInByte)
 
/*
 * Function:
 *      unsigned short sysConfigInHalfWord (int pciConfigAddress) ;
 *
 * Inputs:
 *      a0 - pciConfigAddress
 *
 * Outputs:
 *      v0 - half word read from PCI Configuration space.
 */
 
FUNC_START (hal_sysConfigInHalfWord)
sysConfigInHalfWord:
        li      t0, 0xb8000000  /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        andi    t1, a0, 0x00000003      /* t1 = Config space halfword offset. */
        xor     t2, t1, a0              /* t2 = PCI config address of   */
                                        /*      longword containing halfword. */
 
        xori    t1, 0x00000002  /* t1 = big endian halfword offset. */
                                        /*      offset 0 -> 2 */
                                        /*      offset 2 -> 0 */
 
        or      t1, t0                  /* t1 = halfword corrected PCI config */
                                        /*      data address. */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      t2, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lhu     v0, 0x2cfc (t1)         /* v0 = config space halfword read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END (hal_sysConfigInHalfWord)
 
/*
 * Function:
 *      unsigned short sysConfigInWord (int pciConfigAddress) ;
 *
 * Inputs:
 *      a0 - pciConfigAddress
 *
 * Outputs:
 *      v0 - word read from PCI Configuration space.
 */
 
FUNC_START (hal_sysConfigInWord)
        li      t0, 0xb8000000          /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      a0, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lw      v0, 0x2cfc (t0)         /* v0 = config space word read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END(hal_sysConfigInWord)
 
 
##-----------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
 
        .extern hal_default_isr
        .data
 
        .globl  hal_interrupt_handlers
hal_interrupt_handlers:
        .rept   30
        .long   hal_default_isr
        .endr
 
        .globl  hal_interrupt_data
hal_interrupt_data:
        .rept   30
        .long   0
        .endr
 
        .globl  hal_interrupt_objects
hal_interrupt_objects:
        .rept   30
        .long   0
        .endr
 
##-----------------------------------------------------------------------------
## end of platform.S
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [idt79s334a/] [v2_0/] [src/] [platform.S] - Blame information for rev 565

Line No.	Rev	Author	Line
1	27	unneback	`##=============================================================================`
2			`##`
3			`## platform.S`
4			`##`
5			`## MIPS IDT platform code`
6			`##`
7			`##=============================================================================`
8			`#####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later version.`
16			`##`
17			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
18			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
19			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
20			`## for more details.`
21			`##`
22			`## You should have received a copy of the GNU General Public License along`
23			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
24			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
25			`##`
26			`## As a special exception, if other files instantiate templates or use macros`
27			`## or inline functions from this file, or you compile this file and link it`
28			`## with other works to produce a work based on this file, this file does not`
29			`## by itself cause the resulting work to be covered by the GNU General Public`
30			`## License. However the source code for this file must still be made available`
31			`## in accordance with section (3) of the GNU General Public License.`
32			`##`
33			`## This exception does not invalidate any other reasons why a work based on`
34			`## this file might be covered by the GNU General Public License.`
35			`##`
36			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
37			`## at http://sources.redhat.com/ecos/ecos-license/`
38			`## -------------------------------------------`
39			`#####ECOSGPLCOPYRIGHTEND####`
40			`##=============================================================================`
41			`#######DESCRIPTIONBEGIN####`
42			`##`
43			`## Author(s): tmichals`
44			`## Contributors: nickg`
45			`## Date: 2002-10-02`
46			`## Purpose:`
47			`## Description: MIPS IDT platform code`
48			`##`
49			`######DESCRIPTIONEND####`
50			`##`
51			`##=============================================================================`
52
53			`#include`
54			`#include`
55
56			`#ifdef CYGPKG_KERNEL`
57			`# include`
58			`#endif`
59
60			`#include`
61			`#include`
62
63
64			`FUNC_START(hal_memc_setup)`
65			`#define PIO_BASE_ADDR 0xb8000600`
66			`#define PIO_DC_SET 0x00500050`
67			`#define PIO_DC_MASK 0xff0fff0f`
68
69			`li t0,PIO_BASE_ADDR`
70			`lw t1,0x4(t0)`
71			`nop`
72			`li t2,PIO_DC_MASK #mask the UART bits`
73			`and t1,t1,t2`
74			`nop`
75			`li t2,PIO_DC_SET #rx0=rx1=input, tx0=tx1=output`
76			`or t1,t1,t2`
77			`nop`
78			`sw t1,0x4(t0)`
79
80
81			`li t0,PORT_WIDTH_CNTL_REG /* Set PortWidth and Bus parameters */`
82			`li t1,PORT_WIDTH_CNTL_VAL`
83			`sw t1,0(t0)`
84
85			`li t0,BUS_TURN_AROUND_CNTRL_REG`
86			`li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0x18000000*/`
87			`sw t1,0(t0)`
88
89			`li t0,BUS_TURN_AROUND_REG`
90			`li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0xffffe204*/`
91			`sw t1,0(t0)`
92
93
94			`li t0,ADDRESS_LATCH_TIMING_REG`
95			`li t1,ADDRESS_LATCH_TIMING_VAL`
96			`sw t1,0(t0)`
97
98
99
100			`/* CHIP SELECT 0 for FLASH */`
101			`li t0,MEM_BASE_BASE`
102			`li t1,MBA_REG0`
103			`sw t1,0(t0) /* 0x18000080 */`
104			`li t1,MBM_REG0`
105			`sw t1,0x4(t0) /* 0x18000084 */`
106			`li t0,MEM_CTL_BASE`
107			`li t1,MCR_CS0_BS`
108			`sw t1,0(t0) /* 0x18000200 */`
109
110			`/* CHIP SELECT 1 for FLASH */`
111
112			`li t0,MEM_BASE_BASE`
113			`li t1,MBA_REG1`
114			`sw t1,8(t0) /* 0x18000088 */`
115			`li t1,MBM_REG1 /* 0x1800008C */`
116			`sw t1,0xc(t0)`
117			`li t0,MEM_CTL_BASE`
118			`li t1,MCR_CS1_BS /* chip select 2 for other flash */`
119			`sw t1,0x4(t0) /* 0x18000204 */`
120
121			`/* CHIP SELECT 2*/`
122			`li t1,MCR_CS2_BS`
123			`sw t1,0x8(t0)`
124
125			`/* CHIP SELECT 3*/`
126			`li t1,MCR_CS3_BS`
127			`sw t1,0xc(t0)`
128
129
130			`/* CHIP SELECT 4*/`
131			`li t1,MCR_CS4_BS`
132			`sw t1,0x10(t0)`
133
134
135			`/* CHIP SELECT 5*/`
136			`li t1,MCR_CS5_BS`
137			`sw t1,0x14(t0)`
138
139
140
141			`li t0,RHEA_IREG_BASE`
142			`li t1,DISABLE_TIMER`
143			`sw t1,0x730(t0)`
144
145			`li t1,0`
146			`sw t1,0x310(t0)`
147
148
149			`/* SDRAM Initialization:- Start Here! */`
150			`li t1,DRAM_BNK0_BASE`
151			`sw t1,0xc0(t0)`
152			`li t1,DRAM_BNK1_BASE`
153			`sw t1,0xc8(t0)`
154			`li t1,DRAM_BNK2_BASE`
155			`sw t1,0xd0(t0)`
156			`li t1,DRAM_BNK3_BASE`
157			`sw t1,0xd8(t0)`
158
159			`li t1,DRAM_BNK0_MASK`
160			`sw t1,0xc4(t0)`
161			`li t1,DRAM_BNK1_MASK`
162			`sw t1,0xcc(t0)`
163			`li t1,DRAM_BNK2_MASK`
164			`sw t1,0xd4(t0)`
165			`li t1,DRAM_BNK3_MASK`
166			`sw t1,0xdc(t0)`
167
168			`li t0,MEM_BASE_BASE`
169			`li t1,MBA_REG1`
170			`sw t1,0x8(t0)`
171			`li t1,MBM_REG1`
172			`sw t1,0xc(t0)`
173
174			`li t0,TIMER_BASE`
175			`li t1,DISABLE_TIMER`
176			`sw t1,0x60(t0)`
177			`nop`
178			`li t1,0x0`
179			`sw t1,0x64(t0)`
180			`li t1,CPU_BERR_BS`
181			`sw t1,0x48(t0)`
182			`li t1,IP_BERR_BS`
183			`sw t1,0x58(t0)`
184
185
186			`li t0,RHEA_IREG_BASE`
187			`li t1,SDRAM_CR_BS`
188			`sw t1,0x300(t0)`
189
190			`li t2,2`
191			`li t3,0`
192			`1:`
193			`li t1,SDRAM_PC_VAL`
194			`sw t1,0x300(t0)`
195			`nop`
196			`li t4,SDRAM_TEST_PATTERN`
197			`li t5,K1BASE \| DRAM_BNK0_BASE`
198			`sw t4,0x1000(t5)`
199			`addu t3,1`
200			`bne t3,t2,1b`
201			`nop`
202
203			`li t2,2`
204			`li t3,0`
205			`1:`
206			`li t1,SDRAM_RFRSH_CMD`
207			`sw t1,0x300(t0)`
208			`sw t4,0x0(t5)`
209			`addu t3,1`
210			`bne t3,t2,1b`
211			`nop`
212
213
214			`li t1,SDRAM_MODE_REG`
215			`sw t1,0x300(t0)`
216			`sw t4,0x80(t5)`
217
218			`li t0,TIMER_BASE`
219			`li t1,DRAM_RF_CMPR_BS`
220			`sw t1,0x68(t0)`
221			`li t1,ENABLE_TIMER`
222			`sw t1,0x60(t0)`
223
224
225			`/* Delay for Sdram to stabilise with fast refresh */`
226			`li t2, 0x2FF00`
227			`1:`
228			`subu t2, 1`
229			`bne t2, zero,1b`
230			`nop`
231
232			`/* Change the Sdram refresh to a standard refresh */`
233			`li t0,TIMER_BASE`
234			`li t1,DRAM_RF_CMPR_SE_BS`
235			`sw t1,0x68(t0)`
236
237			`/* SDRAM Initialization : End Here ! */`
238
239
240			`jr ra`
241			`nop`
242
243			`FUNC_END(hal_memc_setup)`
244
245
246			`FUNC_START(hal_setTlbEntry)`
247			`.set noreorder`
248			`mtc0 a0,C0_INX`
249			`mtc0 a1,C0_TLBHI`
250			`mtc0 a2,C0_TLBLO0`
251			`mtc0 a3,C0_TLBLO1`
252			`nop`
253			`nop`
254			`tlbwi`
255			`nop`
256			`.set reorder`
257
258			`j ra`
259			`nop`
260			`FUNC_END(hal_setTlbEntry)`
261
262			`FUNC_START(hal_setPageSize)`
263			`.set noreorder`
264			`mtc0 a0,C0_PAGEMASK`
265			`nop`
266			`nop`
267			`.set reorder`
268			`j ra`
269			`nop`
270			`FUNC_END(hal_setPageSize)`
271
272
273
274
275			`FUNC_START (hal_sysConfigOutByte)`
276			`.set noreorder`
277			`li t0,0xb8002cf8`
278			`li t1,0xb8002cfc`
279			`li t2,0x3`
280			`and a2,t2`
281			`sw a0,0x0(t0)`
282			`xori a2,0x3`
283			`or t1,a2`
284			`sb a1,0x0(t1)`
285			`j ra`
286			`nop`
287			`.set reorder`
288			`FUNC_END(hal_sysConfigOutByte)`
289
290
291
292			`FUNC_START(hal_sysConfigOutHalfWord)`
293			`.set noreorder`
294			`li t0,0xb8002cf8`
295			`li t1,0xb8002cfc`
296			`li t2,0x3`
297			`and a2,t2`
298			`sw a0,0x0(t0)`
299			`xori a2,0x2`
300			`or t1,a2`
301			`sh a1,0x0(t1)`
302			`j ra`
303			`nop`
304			`.set reorder`
305			`FUNC_END (hal_sysConfigOutHalfWord)`
306
307			`FUNC_START (hal_sysConfigOutWord)`
308			`.set noreorder`
309			`li t0,0xb8002cf8`
310			`li t1,0xb8002cfc`
311			`sw a0,0x0(t0)`
312			`sw a1,0x0(t1)`
313			`j ra`
314			`nop`
315			`.set reorder`
316			`FUNC_END (hal_sysConfigOutWord)`
317
318
319			`/*`
320			`* Function:`
321			`* unsigned char sysConfigInByte (int pciConfigAddress) ;`
322			`* Inputs:`
323			`* a0 - pciConfigAddress`
324			`* Outputs:`
325			`* v0 - byte read from PCI Configuration space.`
326			`*/`
327			`FUNC_START (hal_sysConfigInByte)`
328			`sysConfigInByte:`
329			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
330			`/* space address register */`
331			`andi t1, a0, 0x00000003 /* t1 = PCI config space byte offset. */`
332			`xor t2, t1, a0 /* t2 = PCI config address of */`
333			`/* longword containing byte. */`
334			`xori t1, 0x00000003 /* t1 = big endian byte offset. */`
335			`/* offset 0 -> 3 */`
336			`/* offset 1 -> 2 */`
337			`/* offset 2 -> 1 */`
338			`/* offset 3 -> 0 */`
339			`or t1, t0 /* t1 = byte corrected PCI config */`
340			`/* data address. */`
341			`.set noreorder /* Instructions must not be moved ! */`
342			`sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */`
343			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
344
345			`lbu v0, 0x2cfc (t1) /* v0 = PCI config space byte read */`
346
347			`j ra /* Return to caller. */`
348			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
349
350			`.set reorder`
351			`FUNC_END (hal_sysConfigInByte)`
352
353			`/*`
354			`* Function:`
355			`* unsigned short sysConfigInHalfWord (int pciConfigAddress) ;`
356			`*`
357			`* Inputs:`
358			`* a0 - pciConfigAddress`
359			`*`
360			`* Outputs:`
361			`* v0 - half word read from PCI Configuration space.`
362			`*/`
363
364			`FUNC_START (hal_sysConfigInHalfWord)`
365			`sysConfigInHalfWord:`
366			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
367			`/* space address register */`
368			`andi t1, a0, 0x00000003 /* t1 = Config space halfword offset. */`
369			`xor t2, t1, a0 /* t2 = PCI config address of */`
370			`/* longword containing halfword. */`
371
372			`xori t1, 0x00000002 /* t1 = big endian halfword offset. */`
373			`/* offset 0 -> 2 */`
374			`/* offset 2 -> 0 */`
375
376			`or t1, t0 /* t1 = halfword corrected PCI config */`
377			`/* data address. */`
378			`.set noreorder /* Instructions must not be moved ! */`
379			`sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */`
380			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
381
382			`lhu v0, 0x2cfc (t1) /* v0 = config space halfword read */`
383
384			`j ra /* Return to caller. */`
385			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
386
387			`.set reorder`
388			`FUNC_END (hal_sysConfigInHalfWord)`
389
390			`/*`
391			`* Function:`
392			`* unsigned short sysConfigInWord (int pciConfigAddress) ;`
393			`*`
394			`* Inputs:`
395			`* a0 - pciConfigAddress`
396			`*`
397			`* Outputs:`
398			`* v0 - word read from PCI Configuration space.`
399			`*/`
400
401			`FUNC_START (hal_sysConfigInWord)`
402			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
403			`/* space address register */`
404			`.set noreorder /* Instructions must not be moved ! */`
405			`sw a0, 0x2cf8 (t0) /* Write PCI config space address reg */`
406			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
407
408			`lw v0, 0x2cfc (t0) /* v0 = config space word read */`
409
410			`j ra /* Return to caller. */`
411			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
412
413			`.set reorder`
414			`FUNC_END(hal_sysConfigInWord)`
415
416
417			`##-----------------------------------------------------------------------------`
418			`# Interrupt vector tables.`
419			`# These tables contain the isr, data and object pointers used to deliver`
420			`# interrupts to user code.`
421
422			`.extern hal_default_isr`
423			`.data`
424
425			`.globl hal_interrupt_handlers`
426			`hal_interrupt_handlers:`
427			`.rept 30`
428			`.long hal_default_isr`
429			`.endr`
430
431			`.globl hal_interrupt_data`
432			`hal_interrupt_data:`
433			`.rept 30`
434			`.long 0`
435			`.endr`
436
437			`.globl hal_interrupt_objects`
438			`hal_interrupt_objects:`
439			`.rept 30`
440			`.long 0`
441			`.endr`
442
443			`##-----------------------------------------------------------------------------`
444			`## end of platform.S`
445