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#ifndef CYGONCE_IMP_CACHE_H
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#define CYGONCE_IMP_CACHE_H
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//=============================================================================
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//
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// imp_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, dmoseley
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// Date: 1998-02-17
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/imp_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/mips-regs.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/plf_cache.h>
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#include <cyg/hal/var_arch.h>
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#ifdef CYGHWR_HAL_MIPS_MIPS64_CORE_5K
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//-----------------------------------------------------------------------------
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// Cache dimensions
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// Data cache
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#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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#define HAL_ICACHE_WAYS 2 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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#define HAL_DCACHE_WRITETHRU_MODE 1
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#define HAL_DCACHE_WRITEBACK_MODE 0
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#else
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#error Unknown MIPS32 Variant
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#endif
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//-----------------------------------------------------------------------------
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// General cache defines.
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#define HAL_CLEAR_TAGLO() asm volatile (" mtc0 $0, $28;" \
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" nop;" \
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" nop;" \
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" nop;")
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#define HAL_CLEAR_TAGHI() asm volatile (" mtc0 $0, $29;" \
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" nop;" \
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" nop;" \
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" nop;")
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/* Cache instruction opcodes */
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#define HAL_CACHE_OP(which, op) (which | (op << 2))
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#define HAL_WHICH_ICACHE 0x0
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#define HAL_WHICH_DCACHE 0x1
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#define HAL_INDEX_INVALIDATE 0x0
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#define HAL_INDEX_LOAD_TAG 0x1
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#define HAL_INDEX_STORE_TAG 0x2
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#define HAL_HIT_INVALIDATE 0x4
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#define HAL_ICACHE_FILL 0x5
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#define HAL_DCACHE_HIT_INVALIDATE 0x5
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#define HAL_DCACHE_HIT_WRITEBACK 0x6
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#define HAL_FETCH_AND_LOCK 0x7
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Invalidate the entire cache
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#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
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#define HAL_DCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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register volatile CYG_BYTE *addr; \
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HAL_CLEAR_TAGLO(); \
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HAL_CLEAR_TAGHI(); \
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for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
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addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE); \
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addr += HAL_DCACHE_LINE_SIZE ) \
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{ \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)), \
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"r"(addr)); \
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} \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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extern void hal_dcache_sync(void);
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#define HAL_DCACHE_SYNC_DEFINED
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#define HAL_DCACHE_SYNC() hal_dcache_sync()
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_asize_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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#define HAL_DCACHE_LOCK_DEFINED
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#define HAL_DCACHE_LOCK(_base_, _asize_) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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// Undo a previous lock operation
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#define HAL_DCACHE_UNLOCK_DEFINED
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#define HAL_DCACHE_UNLOCK(_base_, _asize_) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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// Unlock entire cache
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#define HAL_DCACHE_UNLOCK_ALL_DEFINED
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#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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#define HAL_DCACHE_FLUSH_DEFINED
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#if HAL_DCACHE_WRITETHRU_MODE == 1
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// No need to flush a writethrough cache
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#define HAL_DCACHE_FLUSH( _base_ , _asize_ )
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#else
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#error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
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#endif
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// Write dirty cache lines to memory for the given address range.
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#define HAL_DCACHE_STORE_DEFINED
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#if HAL_DCACHE_WRITETHRU_MODE == 1
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// No need to store a writethrough cache
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#define HAL_DCACHE_STORE( _base_ , _asize_ )
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#else
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#error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
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#endif
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// Invalidate cache lines in the given range without writing to memory.
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#define HAL_DCACHE_INVALIDATE_DEFINED
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#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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#define HAL_ICACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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register volatile CYG_BYTE *addr; \
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HAL_CLEAR_TAGLO(); \
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HAL_CLEAR_TAGHI(); \
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for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
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addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE); \
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addr += HAL_ICACHE_LINE_SIZE ) \
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{ \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)), \
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"r"(addr)); \
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} \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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extern void hal_icache_sync(void);
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#define HAL_ICACHE_SYNC_DEFINED
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#define HAL_ICACHE_SYNC() hal_icache_sync()
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_asize_)
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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#define HAL_ICACHE_LOCK_DEFINED
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#define HAL_ICACHE_LOCK(_base_, _asize_) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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// Undo a previous lock operation
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#define HAL_ICACHE_UNLOCK_DEFINED
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#define HAL_ICACHE_UNLOCK(_base_, _asize_) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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// Unlock entire cache
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#define HAL_ICACHE_UNLOCK_ALL_DEFINED
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#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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#define HAL_ICACHE_INVALIDATE_DEFINED
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#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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asm volatile (" cache %0, 0(%1)" \
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: \
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: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
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"r"(_addr_)); \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_IMP_CACHE_H
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// End of imp_cache.h
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