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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [ref4955/] [v2_0/] [include/] [platform.inc] - Blame information for rev 174

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#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##
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##      platform.inc
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##
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##      REF4955/TX4955 board assembler header file
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s):   nickg
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## Contributors:nickg,jskov
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## Date:        2000-05-15
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## Purpose:     REF4955/TX4955 board definitions.
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## Description: This file contains various definitions and macros that are
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##              useful for writing assembly code for the REF4955/TX4955 board.
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## Usage:
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##              #include 
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##              ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include 
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#include 
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#------------------------------------------------------------------------------
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# Macro for copying vectors to RAM if necessary.
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#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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        .macro  hal_vectors_init
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        # If we don~t play nice with a ROM monitor, copy the required
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        # vectors into the proper location.
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        la      t0,0x80000000           # dest addr
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        la      t1,utlb_vector          # source addr
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        la      t3,utlb_vector_end      # end dest addr
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1:
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        lw      v0,0(t1)                # get word
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        addi    t1,t1,4
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        sw      v0,0(t0)                # write word
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        addi    t0,t0,4
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        bne     t1,t3,1b
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         nop
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        la      t0,0x80000180           # dest addr
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        la      t1,other_vector         # source addr
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        la      t3,other_vector_end     # end dest addr
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1:
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        lw      v0,0(t1)                # get word
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        addi    t1,t1,4
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        sw      v0,0(t0)                # write word
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        addi    t0,t0,4
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        bne     t1,t3,1b
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         nop
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        .set mips3                      # Set ISA to MIPS 3 to allow cache insns
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        # Now clear the region in the caches
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        la      t0,0x80000000           # dest addr
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        ori     t1,t0,0x200             # source addr
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1:      cache   0x01,0(t0)              # Flush word from data cache
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        cache   0x01,1(t0)
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        cache   0x01,2(t0)
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        cache   0x01,3(t0)
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        nop
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        cache   0x00,0(t0)              # Invalidate icache for word
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        cache   0x00,1(t0)
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        cache   0x00,2(t0)
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        cache   0x00,3(t0)
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        nop
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        addi    t0,t0,0x20
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        bne     t0,t1,1b
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         nop
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        .set mips0                      # reset ISA to default
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        .endm
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#else
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        .macro  hal_vectors_init
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        .endm
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#endif
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#------------------------------------------------------------------------------
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# Monitor initialization.
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#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
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#if     defined(CYG_HAL_STARTUP_ROM) ||                 \
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        (       defined(CYG_HAL_STARTUP_RAM) &&         \
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                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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        # If we are starting up from ROM, or we are starting in
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        # RAM and NOT using a ROM monitor, initialize the VSR table.
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        .macro  hal_mon_init
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        hal_vectors_init
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        # Set default exception VSR for all vectors
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        ori     a0,zero,CYGNUM_HAL_VSR_COUNT
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        la      a1,__default_exception_vsr
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        la      a2,hal_vsr_table
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1:      sw      a1,0(a2)
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        addi    a2,a2,4
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        addi    a0,a0,-1
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        bne     a0,zero,1b
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         nop
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        # Now set special VSRs
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        la      a0,hal_vsr_table
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        # Set interrupt VSR
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        la      a1,__default_interrupt_vsr
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        sw      a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
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        # Add special handler on breakpoint vector to allow GDB and
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        # GCC to both use 'break' without conflicts.
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        la      a1,__break_vsr_springboard
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        sw      a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0)
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        # Set exception handler on special vectors
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        # FIXME: Should use proper definitions
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        la      a1,__default_exception_vsr
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        sw      a1,32*4(a0)             # debug
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        sw      a1,33*4(a0)             # utlb
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        sw      a1,34*4(a0)             # nmi
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        .endm
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#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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        # Initialize the VSR table entries
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        # We only take control of the interrupt vector,
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        # the rest are left to the ROM for now...
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        .macro  hal_mon_init
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        hal_vectors_init
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        # Set interrupt VSR
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        la      a0,hal_vsr_table
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        la      a1,__default_interrupt_vsr
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        sw      a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
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        .endm
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#else
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        .macro  hal_mon_init
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        hal_vectors_init
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        .endm
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#endif
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#define CYGPKG_HAL_MIPS_MON_DEFINED
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#endif
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#------------------------------------------------------------------------------
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#if !defined(CYG_HAL_STARTUP_RAM)
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        .macro  hal_memc_init
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        // Only initialize the SDRAM controller when running in ROM
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        .extern hal_memc_setup
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        lar     t0,hal_memc_setup
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        jalr    t0
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        nop
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        .endm
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#define CYGPKG_HAL_MIPS_MEMC_DEFINED
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#endif
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#------------------------------------------------------------------------------
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# Decide whether the VSR table is defined externally, or is to be defined
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# here.
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## ISR tables are defined in platform.S
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#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
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## VSR table is at a fixed RAM address defined by the linker script
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#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
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##-----------------------------------------------------------------------------
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## For chaining, use the calculated cause vector number.
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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        .macro  hal_intc_translate inum,vnum
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        move    \vnum,\inum                     # Vector == interrupt number
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        .endm
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#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
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#endif
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##-----------------------------------------------------------------------------
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#ifdef CYG_STARTUP_ROM
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## Initial SR value for use in ROM:
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## CP0 usable
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## Vectors in RAM
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## FP registers are 32 bit
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## All hw ints disabled
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#define INITIAL_SR      0x30000000
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#else
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## Initial SR value for use standalone:
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## CP0 usable
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## Vectors to RAM
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## FP registers are 32 bit
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## All hw ints disabled
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#define INITIAL_SR      0x30000000
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#endif
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#------------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLATFORM_INC
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# end of platform.inc

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