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#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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// plf_intr.h
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//
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// REF4955 Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov, nickg
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// Date: 2000-05-09
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for the REF4955 board.
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//
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// Usage:
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// #include <cyg/hal/plf_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// The first 6 correspond to the interrupt lines in the status/cause regs
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#define CYGNUM_HAL_INTERRUPT_V320USC_INT0 0
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#define CYGNUM_HAL_INTERRUPT_V320USC_INT1 1
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#define CYGNUM_HAL_INTERRUPT_EXT 2
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#define CYGNUM_HAL_INTERRUPT_LAN 3
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#define CYGNUM_HAL_INTERRUPT_IO 4
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#define CYGNUM_HAL_INTERRUPT_COMPARE 5
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#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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// This overlaps with LB_MBI below but it doesn't matter. It's only used
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// by the HAL to access the special chaining entry in the ISR tables.
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// All other attempted access to the ISR table will be redirected to this
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// entry (curtsey of HAL_TRANSLATE_VECTOR). The other vector definitions
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// are still valid, but only for enable/disable/config etc. (i.e., in
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// chaining mode they have associated entries in the ISR tables).
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#define CYGNUM_HAL_INTERRUPT_CHAINING 6
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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(_index_) = CYGNUM_HAL_INTERRUPT_CHAINING
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#endif
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// The next 32 correspond to the interrupt lines in the V320USC's interrupt
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// controller. These are decoded from the controller when an interrupt
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// enters via CYGNUM_HAL_INTERRUPT_V320USC_INT0.
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#define CYGNUM_HAL_INTERRUPT_INTC_V320USC_base 6
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#define CYGNUM_HAL_INTERRUPT_LB_MBI 6
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#define CYGNUM_HAL_INTERRUPT_PCI_MBI 7
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#define CYGNUM_HAL_INTERRUPT_RESERVED_2 8
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#define CYGNUM_HAL_INTERRUPT_I2O_OP_NE 9
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#define CYGNUM_HAL_INTERRUPT_I2O_IF_NF 10
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#define CYGNUM_HAL_INTERRUPT_I2O_IP_NE 11
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#define CYGNUM_HAL_INTERRUPT_I2O_OP_NF 12
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#define CYGNUM_HAL_INTERRUPT_I2O_OF_NE 13
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#define CYGNUM_HAL_INTERRUPT_RESERVED_8 14
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#define CYGNUM_HAL_INTERRUPT_RESERVED_9 15
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#define CYGNUM_HAL_INTERRUPT_RESERVED_10 16
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#define CYGNUM_HAL_INTERRUPT_RESERVED_11 17
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#define CYGNUM_HAL_INTERRUPT_TIMER0 18
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#define CYGNUM_HAL_INTERRUPT_TIMER1 19
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#define CYGNUM_HAL_INTERRUPT_RESERVED_14 20
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#define CYGNUM_HAL_INTERRUPT_ENUM 21
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#define CYGNUM_HAL_INTERRUPT_DMA0 22
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#define CYGNUM_HAL_INTERRUPT_DMA1 23
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#define CYGNUM_HAL_INTERRUPT_RESERVED_18 24
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#define CYGNUM_HAL_INTERRUPT_RESERVED_19 25
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#define CYGNUM_HAL_INTERRUPT_PWR_STATE 26
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#define CYGNUM_HAL_INTERRUPT_HBI 27
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#define CYGNUM_HAL_INTERRUPT_WDI 28
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#define CYGNUM_HAL_INTERRUPT_BWI 29
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#define CYGNUM_HAL_INTERRUPT_PSLAVE_PI 30
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#define CYGNUM_HAL_INTERRUPT_PMASTER_PI 31
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#define CYGNUM_HAL_INTERRUPT_PCI_T_ABORT 32
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#define CYGNUM_HAL_INTERRUPT_PCI_M_ABORT 33
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#define CYGNUM_HAL_INTERRUPT_DRAM_PI 34
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#define CYGNUM_HAL_INTERRUPT_RESERVED_29 35
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#define CYGNUM_HAL_INTERRUPT_DI0 36
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#define CYGNUM_HAL_INTERRUPT_DI1 37
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// The next 6 correspond to the interrupt lines specific to the PCI
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// connector (decoded from CYGNUM_HAL_INTERRUPT_V320USC_INT1)
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#define CYGNUM_HAL_INTERRUPT_INTC_PCI_base 38
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#define CYGNUM_HAL_INTERRUPT_SERR 38
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#define CYGNUM_HAL_INTERRUPT_PERR 39
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#define CYGNUM_HAL_INTERRUPT_INTD 40
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#define CYGNUM_HAL_INTERRUPT_INTC 41
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#define CYGNUM_HAL_INTERRUPT_INTB 42
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#define CYGNUM_HAL_INTERRUPT_INTA 43
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// The next 5 correspond to the interrupt lines specific to the REF4955
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// board (decoded from CYGNUM_HAL_INTERRUPT_IO)
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#define CYGNUM_HAL_INTERRUPT_INTC_IO_base 44
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#define CYGNUM_HAL_INTERRUPT_SOFTWARE 44
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#define CYGNUM_HAL_INTERRUPT_INT_SWITCH 45
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#define CYGNUM_HAL_INTERRUPT_PARALLEL 46
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#define CYGNUM_HAL_INTERRUPT_DEBUG_UART 47
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#define CYGNUM_HAL_INTERRUPT_USER_UART 48
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_V320USC_INT0
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_USER_UART
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
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// The vector used by the Real time clock
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Interrupt controler information
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// V320USC
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#define CYGARC_REG_INT_STAT 0xb80000ec
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#define CYGARC_REG_INT_CFG0 0xb80000e0
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#define CYGARC_REG_INT_CFG1 0xb80000e4
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#define CYGARC_REG_INT_CFG2 0xb80000e8
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#define CYGARC_REG_INT_CFG3 0xb8000158
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#define CYGARC_REG_INT_CFG_INT0 0x00000100
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#define CYGARC_REG_INT_CFG_INT1 0x00000200
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#define CYGARC_REG_INT_CFG_INT2 0x00000400
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#define CYGARC_REG_INT_CFG_INT3 0x00000800
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// FPGA
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#define CYGARC_REG_PCI_STAT 0xb5300000
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#define CYGARC_REG_PCI_MASK 0xb5300030
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#define CYGARC_REG_IO_STAT 0xb5300010
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#define CYGARC_REG_IO_MASK 0xb5300040
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
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HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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} \
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else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
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HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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} else { /* V320USC */ \
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cyg_uint32 _mask_; \
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cyg_uint32 _shift_ = \
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(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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_mask_ &= !(1<<_shift_); \
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HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
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HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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_mask_ |= (1<<_shift_); \
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HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
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} \
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else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
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{ \
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| 259 |
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
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HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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_mask_ |= (1<<_shift_); \
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HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
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} else { /* V320USC */ \
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cyg_uint32 _mask_; \
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cyg_uint32 _shift_ = \
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(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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_mask_ |= (1<<_shift_); \
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HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _srvector_ = _vector_; \
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if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) { \
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_srvector_ = CYGNUM_HAL_INTERRUPT_IO; \
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} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) { \
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_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT1; \
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} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_V320USC_base) { \
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cyg_uint32 _mask_; \
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cyg_uint32 _shift_ = \
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(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
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_mask_ = (1<<_shift_); \
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HAL_WRITE_UINT32(CYGARC_REG_INT_STAT, _mask_ ); \
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| 287 |
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_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT0; \
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} \
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asm volatile ( \
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| 290 |
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"mfc0 $3,$13\n" \
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| 291 |
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"la $2,0x00000400\n" \
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| 292 |
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"sllv $2,$2,%0\n" \
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| 293 |
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"nor $2,$2,$0\n" \
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| 294 |
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"and $3,$3,$2\n" \
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| 295 |
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"mtc0 $3,$13\n" \
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| 296 |
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"nop; nop; nop\n" \
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| 297 |
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: \
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: "r"(_srvector_) \
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| 299 |
|
|
: "$2", "$3" \
|
| 300 |
|
|
); \
|
| 301 |
|
|
CYG_MACRO_END
|
| 302 |
|
|
|
| 303 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
|
| 304 |
|
|
|
| 305 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
|
| 306 |
|
|
|
| 307 |
|
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
//----------------------------------------------------------------------------
|
| 311 |
|
|
// Reset.
|
| 312 |
|
|
#define CYGARC_REG_BOARD_RESET 0xb5400000
|
| 313 |
|
|
|
| 314 |
|
|
#define HAL_PLATFORM_RESET() HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,0)
|
| 315 |
|
|
|
| 316 |
|
|
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
|
| 317 |
|
|
|
| 318 |
|
|
//--------------------------------------------------------------------------
|
| 319 |
|
|
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
|
| 320 |
|
|
// End of plf_intr.h
|
