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#ifndef CYGONCE_PLF_IO_H

#define CYGONCE_PLF_IO_H

//=============================================================================

//

//      plf_io.h

//

//      HAL platform device IO register support.

//

//=============================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

//

// eCos is free software; you can redistribute it and/or modify it under

// the terms of the GNU General Public License as published by the Free

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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

//

// As a special exception, if other files instantiate templates or use macros

// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

// by itself cause the resulting work to be covered by the GNU General Public

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//

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//####ECOSGPLCOPYRIGHTEND####

//=============================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):   nickg

// Contributors:nickg, jskov

// Date:        2000-05-18

// Purpose:     Define IO register support

// Description: The macros defined here provide the HAL APIs for handling

//              device IO control registers.

//              

// Usage:

//              #include <cyg/hal/plf_io.h>

//              ...

//              

//

//####DESCRIPTIONEND####

//

//=============================================================================

#include <pkgconf/hal.h>

//-----------------------------------------------------------------------------

// BYTE Register access.

// Individual and vectorized access to 8 bit registers.

// Little-endian version

#if (CYG_BYTEORDER == CYG_LSBFIRST)

#define HAL_READ_UINT8( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_BYTE *)(_register_)))

#define HAL_WRITE_UINT8( _register_, _value_ ) \

        (*((volatile CYG_BYTE *)(_register_)) = (_value_))

#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \

    CYG_MACRO_END

#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \

    CYG_MACRO_END

#else // Big-endian version

#define HAL_READ_UINT8( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))

#define HAL_WRITE_UINT8( _register_, _value_ ) \

        (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))

#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = _r_[_j_];                                        \

    CYG_MACRO_END

#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        _r_[_j_] = (_buf_)[_i_];                                        \

    CYG_MACRO_END

#endif // Big-endian

//-----------------------------------------------------------------------------

// 16 bit access.

// Individual and vectorized access to 16 bit registers.

// Little-endian version

#if (CYG_BYTEORDER == CYG_LSBFIRST)

#define HAL_READ_UINT16( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))

#define HAL_WRITE_UINT16( _register_, _value_ ) \

        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))

#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \

    CYG_MACRO_END

#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \

    CYG_MACRO_END

#else // Big-endian version

#define HAL_READ_UINT16( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))

#define HAL_WRITE_UINT16( _register_, _value_ ) \

        (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))

#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = _r_[_j_];                                        \

    CYG_MACRO_END

#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \

    CYG_MACRO_START                                                     \

    cyg_count32 _i_,_j_;                                                \

    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        _r_[_j_] = (_buf_)[_i_];                                        \

    CYG_MACRO_END

#endif // Big-endian

//-----------------------------------------------------------------------------

// 32 bit access.

// Individual and vectorized access to 32 bit registers.

// Note: same macros for little- and big-endian systems.

#define HAL_READ_UINT32( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))

#define HAL_WRITE_UINT32( _register_, _value_ ) \

        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))

#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \

}

#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \

}

#define HAL_IO_MACROS_DEFINED

//-----------------------------------------------------------------------------

#endif // ifndef CYGONCE_HAL_PLF_IO_H

// End of plf_io.h