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##=============================================================================
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##
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## platform.S
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##
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## MIPS REF4955-TX4955 platform code
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors:nickg, jskov
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## Date: 2000-05-09
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## Purpose: MIPS REF4955-TX4955 platform code
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## Description: Platform specific code for REF4955-TX4955 board.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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.set noreorder
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#include
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#include
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#ifdef CYGPKG_KERNEL
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# include
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#endif
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#include
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#include
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##-----------------------------------------------------------------------------
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## ISR springboard.
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## This routine decodes the interrupt from the various interrupt controllers
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## and vectors to it.
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# On entry:
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# a0 = MIPS status register interrupt number (1,2 or 3)
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# a1 = ISR data value (= interrupt controller reg address)
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# a2 = saved reg dump ptr
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# s0 = saved reg dump ptr
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# s1 = vector table offset
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# s2 = interrupt number
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# a3,v0,v1 etc available for use
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.text
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FUNC_START(hal_isr_springboard_pci)
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lbu v0,0(a1)
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nor v0,v0,v0
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la a1,CYGARC_REG_PCI_MASK
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lbu a2,0(a1)
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and v0,v0,a2
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addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_PCI_base
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b hal_isr_springboard
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nop
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FUNC_END(hal_isr_springboard_pci)
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FUNC_START(hal_isr_springboard_io)
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lbu v0,0(a1)
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nor v0,v0,v0
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la a1,CYGARC_REG_IO_MASK
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lbu a2,0(a1)
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and v0,v0,a2
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addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_IO_base
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b hal_isr_springboard
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nop
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FUNC_END(hal_isr_springboard_io)
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hal_isr_springboard_v320usc:
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lw v0,0(a1)
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la a1,CYGARC_REG_INT_CFG0
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lw v1,0(a1)
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lw a2,4(a1) # CFG1
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or v1,v1,a2
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lw a2,8(a1) # CFG2
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or v1,v1,a2
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la a1,CYGARC_REG_INT_CFG3
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lw a2,0(a1)
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or v1,v1,a2
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and v0,v0,v1
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addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_V320USC_base
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FUNC_START(hal_isr_springboard)
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# The following code implements an ls bit index algorithm similar
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# to that in hal_lsbit_index() in hal_misc.c.
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negu v1,v0 # v1 = -v0
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and v1,v1,v0 # v1 &= v0 [isolate ls bit]
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sll v0,v1,16 # v0 = v1<<16
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subu v1,v0,v1 # v1 = v0 - v1
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sll a0,v1,6 # a0 = v1<<6
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addu v1,v1,a0 # v1 += a0
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sll a1,v1,4 # a1 = v1<<4
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addu v1,v1,a1 # v1 += a1
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la v0,hal_isr_springboard_table # v0 = table address
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srl v1,v1,26 # v1 = v1>>26
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addu v1,v1,v0 # v1 = table entry address
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lb a0,0(v1) # a0 = intc isr number
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add s2,a0,a2 # s2 = eCos isr number
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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hal_isr_springboard_chaining:
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# This serves as the __default_interrupt_isr entry-point in
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# chaning mode, thus ensuring that all interrupts from
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# vectors 0-5 eventually end up on the special CHAINING vector.
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# (See the hal_interrupt_handlers table)
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ori s1,zero,CYGNUM_HAL_INTERRUPT_CHAINING*4 # s1 = chaining isr ix
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#else
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sll s1,s2,2 # s1 = isr table index
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#endif
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la v1,hal_interrupt_handlers
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add v1,v1,s1 # v1 = isr handler address
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lw v1,0(v1) # v1 = isr handler
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la a1,hal_interrupt_data
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add a1,a1,s1 # a1 = address of data ptr
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lw a1,0(a1) # a1 = data pointer
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move a0,s2 # pass interrupt number
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jr v1 # jump to handler, return is to
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# default vsr already in ra
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nop
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| 160 |
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FUNC_END(hal_isr_springboard)
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hal_isr_springboard_table:
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.byte -1, 0, 1, 12, 2, 6, 0, 13
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.byte 3, 0, 7, 0, 0, 0, 0, 14
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.byte 10, 4, 0, 0, 8, 0, 0, 25
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.byte 0, 0, 0, 0, 0, 21, 27, 15
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.byte 31, 11, 5, 0, 0, 0, 0, 0
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.byte 9, 0, 0, 24, 0, 0, 20, 26
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.byte 30, 0, 0, 0, 0, 23, 0, 19
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.byte 29, 0, 22, 18, 28, 17, 16, 0
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| 173 |
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| 174 |
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##-----------------------------------------------------------------------------
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## MEMC initialization.
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## This also initializes the PCI bus and ISA bus bridge, so at the end of this
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## we should have full access to all the memory and devices we need.
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## This code is table driven, which is somewhat more compact that coding it all.
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## Table entries consist of an address and a value to store in that address.
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## A zero address terminates the table. Two special address values modify the
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## behaviour:
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## DELAY_LOOP loops for the number of iterations in the value field.
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## WRITE16 treats the next 2 words as an address and value to be written
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## with a 16 bit write cycle.
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| 186 |
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#if !defined(CYG_HAL_STARTUP_RAM)
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| 188 |
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#define DELAY_LOOP 1
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#define WRITE16 2
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FUNC_START(hal_memc_setup)
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lar t0,hal_memc_setup_table
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la t1,0xbfc00000
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la t2,DELAY_LOOP
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la t3,WRITE16
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1:
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lw a0,0(t0) # next table entry
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lw a1,4(t0) # value to write
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addiu t0,8 # go to next entry
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beq a0,t2,2f # Check for delay
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nop
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| 203 |
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beq a0,t3,3f # Check for 16 bit write
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nop
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beqz a0,9f # zero terminates loop
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nop
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sw a1,0(a0) # write it
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lw zero,0(t1) # uncached read to flush write buffer
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b 1b
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nop
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2:
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lw zero,0(t1) # uncached read to flush write buffer
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bnez a1,2b # count down by value in a1
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addiu a1,-1 # decrement in delay slot
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b 1b # go back to loop
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nop
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3:
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lw a3,0(t0) # get next word
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addiu t0,4 # skip it
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sh a3,0(a1) # store halfword
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lw zero,0(t1) # uncached read to flush write buffer
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b 1b
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nop
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9:
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jr ra
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nop
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FUNC_END(hal_memc_setup)
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##-----------------------------------------------------------------------------
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| 232 |
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## The initialization table
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| 233 |
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| 234 |
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#define USC_LB_BUS_CFG 0xb800007c
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#define USC_SDRAM_MA_CMD 0xb8000088
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| 236 |
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| 237 |
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hal_memc_setup_table:
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| 238 |
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| 239 |
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.long DELAY_LOOP, 10000 # Wait for HW to settle
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| 240 |
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| 241 |
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#ifdef CYGPKG_HAL_MIPS_MSBFIRST
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| 242 |
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# V320SC : big-endian, max bus watch timer
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| 243 |
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.long USC_LB_BUS_CFG, 0x04010ff0
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| 244 |
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#else
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| 245 |
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.long USC_LB_BUS_CFG, 0x04000ff0
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| 246 |
|
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#endif
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| 247 |
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.long USC_SDRAM_MA_CMD, 0x00a70000
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| 248 |
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.long USC_SDRAM_MA_CMD, 0x00e70220
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| 249 |
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| 250 |
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.long 0, 0
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| 251 |
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| 252 |
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#endif // !CYG_HAL_STARTUP_RAM
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| 253 |
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| 254 |
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##-----------------------------------------------------------------------------
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| 255 |
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## ISR tables.
|
| 256 |
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|
| 257 |
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.extern hal_default_isr
|
| 258 |
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|
| 259 |
|
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.data
|
| 260 |
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| 261 |
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 262 |
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.globl hal_interrupt_handlers
|
| 263 |
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hal_interrupt_handlers:
|
| 264 |
|
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# These first 6 vectors all go through a springboard for further
|
| 265 |
|
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# interrupt controller vector decoding before ending up on the
|
| 266 |
|
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# special chaining vector below.
|
| 267 |
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.long hal_isr_springboard_v320usc
|
| 268 |
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.long hal_isr_springboard_pci
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| 269 |
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.long hal_isr_springboard_chaining
|
| 270 |
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.long hal_isr_springboard_chaining
|
| 271 |
|
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.long hal_isr_springboard_io
|
| 272 |
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.long hal_isr_springboard_chaining
|
| 273 |
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|
| 274 |
|
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.long hal_default_isr # chaining vector
|
| 275 |
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|
| 276 |
|
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.globl hal_interrupt_data
|
| 277 |
|
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hal_interrupt_data:
|
| 278 |
|
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.long CYGARC_REG_INT_STAT
|
| 279 |
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.long CYGARC_REG_PCI_STAT
|
| 280 |
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.long 0
|
| 281 |
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.long 0
|
| 282 |
|
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.long CYGARC_REG_IO_STAT
|
| 283 |
|
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.long 0
|
| 284 |
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|
| 285 |
|
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.long 0 # chaining vector data
|
| 286 |
|
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|
| 287 |
|
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.globl hal_interrupt_objects
|
| 288 |
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hal_interrupt_objects:
|
| 289 |
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.long 0
|
| 290 |
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.long 0
|
| 291 |
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.long 0
|
| 292 |
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.long 0
|
| 293 |
|
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.long 0
|
| 294 |
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.long 0
|
| 295 |
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|
| 296 |
|
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.long 0 # chaining vector object
|
| 297 |
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|
| 298 |
|
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.globl cyg_hal_interrupt_level
|
| 299 |
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cyg_hal_interrupt_level:
|
| 300 |
|
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.rept CYGNUM_HAL_ISR_COUNT
|
| 301 |
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.byte 0
|
| 302 |
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.endr
|
| 303 |
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|
| 304 |
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#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 305 |
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|
| 306 |
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.globl hal_interrupt_handlers
|
| 307 |
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hal_interrupt_handlers:
|
| 308 |
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.long hal_isr_springboard_v320usc
|
| 309 |
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.long hal_isr_springboard_pci
|
| 310 |
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.long hal_default_isr
|
| 311 |
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.long hal_default_isr
|
| 312 |
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.long hal_isr_springboard_io
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| 313 |
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.long hal_default_isr
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| 314 |
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|
| 315 |
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.rept CYGNUM_HAL_ISR_COUNT-6
|
| 316 |
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.long hal_default_isr
|
| 317 |
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.endr
|
| 318 |
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|
| 319 |
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.globl hal_interrupt_data
|
| 320 |
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hal_interrupt_data:
|
| 321 |
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.long CYGARC_REG_INT_STAT
|
| 322 |
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.long CYGARC_REG_PCI_STAT
|
| 323 |
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.long 0
|
| 324 |
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.long 0
|
| 325 |
|
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.long CYGARC_REG_IO_STAT
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| 326 |
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.long 0
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| 327 |
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|
| 328 |
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.rept CYGNUM_HAL_ISR_COUNT-6
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| 329 |
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.long 0
|
| 330 |
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.endr
|
| 331 |
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|
| 332 |
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.globl hal_interrupt_objects
|
| 333 |
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hal_interrupt_objects:
|
| 334 |
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.rept CYGNUM_HAL_ISR_COUNT
|
| 335 |
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.long 0
|
| 336 |
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.endr
|
| 337 |
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|
|
| 338 |
|
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.globl cyg_hal_interrupt_level
|
| 339 |
|
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cyg_hal_interrupt_level:
|
| 340 |
|
|
.rept CYGNUM_HAL_ISR_COUNT
|
| 341 |
|
|
.byte 0
|
| 342 |
|
|
.endr
|
| 343 |
|
|
|
| 344 |
|
|
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 345 |
|
|
|
| 346 |
|
|
##-----------------------------------------------------------------------------
|
| 347 |
|
|
## end of platform.S
|
