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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [ref4955/] [v2_0/] [src/] [plf_misc.c] - Blame information for rev 475

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//==========================================================================
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//
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//      plf_misc.c
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//
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//      HAL platform miscellaneous functions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    nickg
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// Contributors: nickg, jlarmour, jskov
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// Date:         2000-05-15
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// Purpose:      HAL miscellaneous functions
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// Description:  This file contains miscellaneous functions provided by the
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//               HAL.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>         // Base types
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#include <cyg/infra/cyg_trac.h>         // tracing macros
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#include <cyg/infra/cyg_ass.h>          // assertion macros
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#include <cyg/hal/hal_arch.h>           // architectural definitions
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#include <cyg/hal/hal_intr.h>           // Interrupt handling
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#include <cyg/hal/hal_cache.h>          // Cache handling
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#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
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#include <cyg/hal/hal_if.h>             // Calling interface definitions
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#include <cyg/hal/hal_misc.h>           // Helper functions
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//--------------------------------------------------------------------------
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#define CYGARC_REG_SUPERIO_IREG     0xb4000398
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#define CYGARC_REG_SUPERIO_DREG     0xb4000399
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#define CYGARC_REG_SUPERIO_FER      0x00 // function enable
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#define CYGARC_REG_SUPERIO_FAR      0x01 // function address
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#define CYGARC_REG_SUPERIO_PTR      0x02 // power and test
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#define CYGARC_REG_SUPERIO_CLK      0x51 // clock controller
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#define CYGARC_REG_SUPERIO_FER_PAR  0x01
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#define CYGARC_REG_SUPERIO_FER_SCC1 0x02
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#define CYGARC_REG_SUPERIO_FER_SCC2 0x04
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#define CYGARC_REG_SUPERIO_CLK_14M  0x00 // 14MHz source
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#define CYGARC_REG_SUPERIO_CLK_CME  0x04 // clock multiplier enabled
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#define CYGARC_REG_SUPERIO_PTR_PPEXT 0x80 // extended
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static void write_super_io(cyg_uint8 offset, cyg_uint8 data)
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{
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    HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_IREG, offset);
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    HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
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    HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
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}
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void hal_platform_init(void)
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{
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    hal_if_init();
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    // Configure the SuperIO chip
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    write_super_io(CYGARC_REG_SUPERIO_FER,
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                   CYGARC_REG_SUPERIO_FER_SCC1|CYGARC_REG_SUPERIO_FER_SCC2);
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    write_super_io(CYGARC_REG_SUPERIO_FAR, 0x10);
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    write_super_io(CYGARC_REG_SUPERIO_CLK,
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                   CYGARC_REG_SUPERIO_CLK_14M|CYGARC_REG_SUPERIO_CLK_CME);
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    // Set up VSC320 interrupt controller. INT1 must merge INT2 and
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    // INT3 according to the platform specification.
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    HAL_WRITE_UINT32(CYGARC_REG_INT_CFG1,
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                     CYGARC_REG_INT_CFG_INT2|CYGARC_REG_INT_CFG_INT3);
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    // Unmask vectors which are entry points for interrupt controllers
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    HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT0);
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    HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT1);
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    HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_IO);
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}
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//--------------------------------------------------------------------------
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// End of plf_misc.c

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