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##=============================================================================
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##
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## platform.S
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##
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## MIPS Ocelot platform code
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors:nickg, jskov
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## Date: 2000-05-09
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## Purpose: MIPS Ocelot platform code
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## Description: Platform specific code for Ocelot board.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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.set noreorder
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#include
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#include
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#ifdef CYGPKG_KERNEL
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# include
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#endif
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#include
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#include
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#include
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##-----------------------------------------------------------------------------
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## MEMC initialization.
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## This code is table driven, which is somewhat more compact that coding it
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## all.
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## Table entries consist of an address and a value to store in that address.
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## A zero address terminates the table. Two special address values modify the
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## behaviour:
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## DELAY_LOOP loops for the number of iterations in the value field.
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## WRITE16 treats the next 2 words as an address and value to be written
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## with a 16 bit write cycle.
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#define HAL_GALILEO_CONTROLLER_BASE 0xb4000000
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#define GL_CPU_CFG 0xb4000000
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#define GL_CPU_CFG_WRITERATE 0x00010000
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#define GL_DEV_PAR_BANK0 0xb400045c
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#define GL_DEV_PAR_BANK1 0xb4000460
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#define GL_DEV_PAR_BANK2 0xb4000464
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#define GL_DEV_PAR_BANK3 0xb4000468
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#define GL_DEV_PAR_BOOT 0xb400046c
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#define GL_SDRAM_CFG 0xb4000448
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#define GL_SDRAM_CFG_REF_INT_CNT_default 0x00000200
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#define GL_SDRAM_CFG_CPU_TO_DRAM_ERR 0x00020000
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#define GL_SDRAM_CFG_ECC_INT 0x00040000
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#define GL_SDRAM_CFG_DUP_BA 0x00100000
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#define GL_SDRAM_CFG_REG_SDRAM 0x00800000
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#define GL_SDRAM_CFG_DADR_12_SEL 0x01000000
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#define GL_SDRAM_CFG_init (GL_SDRAM_CFG_REF_INT_CNT_default| \
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GL_SDRAM_CFG_CPU_TO_DRAM_ERR| \
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GL_SDRAM_CFG_ECC_INT| \
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GL_SDRAM_CFG_DUP_BA| \
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GL_SDRAM_CFG_REG_SDRAM| \
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GL_SDRAM_CFG_DADR_12_SEL)
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#define GL_SDRAM_PAR_BANK0 0xb400044c
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#define GL_SDRAM_PAR_BANK2 0xb4000454
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#define GL_CPU_SCS10_LO 0xb4000008
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#define GL_CPU_SCS10_HI 0xb4000010
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#define GL_CPU_SCS32_LO 0xb4000018
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#define GL_CPU_SCS32_HI 0xb4000020
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#define GL_SDRAM_SCS0_LO 0xb4000400
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#define GL_SDRAM_SCS0_HI 0xb4000404
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#define GL_SDRAM_SCS1_LO 0xb4000408
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#define GL_SDRAM_SCS1_HI 0xb400040c
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#define GL_SDRAM_SCS2_LO 0xb4000410
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#define GL_SDRAM_SCS2_HI 0xb4000414
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#define GL_SDRAM_SCS3_LO 0xb4000418
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#define GL_SDRAM_SCS3_HI 0xb400041c
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#define GL_SDRAM_MODE 0xb4000474
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#define GL_SDRAM_MODE_NORMAL 0x00000000
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#define GL_SDRAM_MODE_ENABLE 0x00000003
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#define PLD_BOARD_STAT 0xbc000004
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#define PLD_INT_SET 0xbc00000c
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#define PLD_INT_CLEAR 0xbc00000d
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#define PLD_INT_SET_USER_LED 0x40
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#define CPU_TO_LE(x) (((x & 0xff) << 24) | ((x & 0xff00) << 8) | ((x & 0xff0000) >> 8) | ((x >> 24) & 0xff))
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#define HAL_OCELOT_RAM_BASE 0x00000000
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#define HAL_GALILEO_CPU_DECODE_SHIFT 21
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#define HAL_GALILEO_DEV_DECODE_SHIFT 20
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#define HAL_GALILEO_SCS10_LD_OFFSET 0x008
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#define HAL_GALILEO_SCS10_HD_OFFSET 0x010
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#define HAL_GALILEO_SCS32_LD_OFFSET 0x018
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#define HAL_GALILEO_SCS32_HD_OFFSET 0x020
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#define HAL_GALILEO_SCS0_LD_OFFSET 0x400
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#define HAL_GALILEO_SCS0_HD_OFFSET 0x404
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#define HAL_GALILEO_SCS1_LD_OFFSET 0x408
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#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
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#define HAL_GALILEO_SCS2_LD_OFFSET 0x410
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#define HAL_GALILEO_SCS2_HD_OFFSET 0x414
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#define HAL_GALILEO_SCS3_LD_OFFSET 0x418
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#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
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#if !defined(CYG_HAL_STARTUP_RAM)
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#define DELAY_LOOP 1
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#define WRITE16 2
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#define swap(v, t1, t2, t3) \
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lui t1,0xff; \
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andi t2,v,0xff00; \
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and t3,v,t1; \
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sll t1,v,0x18; \
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srl v,v,0x18; \
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or v,v,t1; \
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srl t3,t3,0x08; \
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sll t2,t2,0x08; \
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or v,v,t3; \
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or v,v,t2;
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FUNC_START(hal_memc_setup)
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lar t0,hal_memc_setup_table
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la t1,0xbfc00000
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la t2,DELAY_LOOP
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la t3,WRITE16
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1:
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lw a0,0(t0) # next table entry
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lw a1,4(t0) # value to write
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addiu t0,8 # go to next entry
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beq a0,t2,2f # Check for delay
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nop
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beq a0,t3,3f # Check for 16 bit write
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nop
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beqz a0,9f # zero terminates loop
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nop
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sw a1,0(a0) # write it
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lw zero,0(t1) # uncached read to flush write buffer
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b 1b
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nop
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2:
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lw zero,0(t1) # uncached read to flush write buffer
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bnez a1,2b # count down by value in a1
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addiu a1,-1 # decrement in delay slot
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b 1b # go back to loop
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nop
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3:
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lw a3,0(t0) # get next word
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addiu t0,4 # skip it
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sh a3,0(a1) # store halfword
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lw zero,0(t1) # uncached read to flush write buffer
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b 1b
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nop
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9:
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// Complete the SDRAM setup.
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la t0,GL_SDRAM_MODE
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la t1,CPU_TO_LE(GL_SDRAM_MODE_ENABLE)
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sw t1,0(t0)
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// Wait 100us after writing mode
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la a1,(CYGHWR_HAL_MIPS_RM7000_CPU_CLOCK * 100 / 1000000)
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lui a0,0xa000 // uncached bank0 device
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sw zero,0(a0)
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mtc0 zero,$9
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1: mfc0 a0,$9
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nop
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blt a0, a1, 1b
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nop
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lui a0,0xa080 // uncached bank2 device
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sw zero,0(a0)
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mtc0 zero,$9
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1: mfc0 a0,$9
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nop
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blt a0, a1, 1b
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nop
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la t0,GL_SDRAM_MODE
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la t1,CPU_TO_LE(GL_SDRAM_MODE_NORMAL)
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sw t1,0(t0)
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// Set CPU cfg word
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la a0,GL_CPU_CFG
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lw a1,0(a0)
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la t0,CPU_TO_LE(0x20000)
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or a1,a1,t0 // disable retries
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// CPU WriteRate - set GT to match CPU
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mfc0 t0,$16
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la t1, 0x0f000000
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and t0, t0, t1
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beqz t0,1f // defaults to zero
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nop
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la t0, CPU_TO_LE(GL_CPU_CFG_WRITERATE)
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or a1, a1, t0
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1:
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sw a1,0(a0)
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# FIXME: Hardwired for 256MB - need kuseg magic to map full 512MB.
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#
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# Setup SDRAM Bank 0 Address Decoding
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#
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la s7, HAL_GALILEO_CONTROLLER_BASE
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la a0, HAL_OCELOT_RAM_BASE # Phys bottom of Bank 0
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la a1, (HAL_OCELOT_RAM_BASE+128*1024*1024)
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subu a1, 1 # Phys top of Bank0
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srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[1:0]
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swap(t0,t1,t2,t3) # 1st level decoding
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sw t0, HAL_GALILEO_SCS10_LD_OFFSET(s7) # (CPU Decode Region)
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srl t0, a1, HAL_GALILEO_CPU_DECODE_SHIFT #
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swap(t0,t1,t2,t3)
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sw t0, HAL_GALILEO_SCS10_HD_OFFSET(s7) #
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srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS0
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swap(t0,t1,t2,t3) # 2nd level decoding
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sw t0, HAL_GALILEO_SCS0_LD_OFFSET(s7) # (Device Sub-decode Region)
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srl t0, a1, HAL_GALILEO_DEV_DECODE_SHIFT #
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swap(t0,t1,t2,t3)
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| 268 |
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sw t0, HAL_GALILEO_SCS0_HD_OFFSET(s7) #
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| 269 |
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| 270 |
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#
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| 271 |
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# Setup SDRAM Bank 1 Address Decoding
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#
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la a0, (HAL_OCELOT_RAM_BASE+128*1024*1024) # Phys bottom of Bank 1
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la a1, (HAL_OCELOT_RAM_BASE+256*1024*1024)
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subu a1, 1 # Phys top of Bank1
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| 277 |
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srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[3:2]
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swap(t0,t1,t2,t3) # 1st level decoding
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| 279 |
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sw t0, HAL_GALILEO_SCS32_LD_OFFSET(s7) # (CPU Decode Region)
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srl t0, a1, HAL_GALILEO_CPU_DECODE_SHIFT #
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| 281 |
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swap(t0,t1,t2,t3)
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| 282 |
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sw t0, HAL_GALILEO_SCS32_HD_OFFSET(s7) #
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| 283 |
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| 284 |
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srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS2
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| 285 |
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swap(t0,t1,t2,t3) # 2nd level decoding
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| 286 |
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sw t0, HAL_GALILEO_SCS2_LD_OFFSET(s7) # (Device Sub-decode Region)
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| 287 |
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srl t0, a1, HAL_GALILEO_DEV_DECODE_SHIFT #
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swap(t0,t1,t2,t3)
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sw t0, HAL_GALILEO_SCS2_HD_OFFSET(s7) #
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jr ra
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nop
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| 294 |
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FUNC_END(hal_memc_setup)
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| 295 |
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| 296 |
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##-----------------------------------------------------------------------------
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| 297 |
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## The initialization table
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| 298 |
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| 299 |
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hal_memc_setup_table:
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| 300 |
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| 301 |
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.long DELAY_LOOP, 10000 # Wait for HW to settle
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| 302 |
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| 303 |
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.long GL_DEV_PAR_BANK0, CPU_TO_LE(0x000b6b33) // PLD
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| 304 |
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.long GL_DEV_PAR_BANK1, CPU_TO_LE(0x000bad53) // NVRAM
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| 305 |
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.long GL_DEV_PAR_BANK2, CPU_TO_LE(0x000bad54) // UART
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| 306 |
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.long GL_DEV_PAR_BANK3, CPU_TO_LE(0x000fef73) // flash disk
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| 307 |
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.long GL_DEV_PAR_BOOT, CPU_TO_LE(0x144bee63) // boot flash
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| 308 |
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| 309 |
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.long GL_SDRAM_CFG, CPU_TO_LE(GL_SDRAM_CFG_init)
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| 310 |
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.long GL_SDRAM_PAR_BANK0, CPU_TO_LE(0x00000c69 | 0x4000)
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| 311 |
|
|
.long GL_SDRAM_PAR_BANK2, CPU_TO_LE(0x00000c69 | 0x4000)
|
| 312 |
|
|
|
| 313 |
|
|
.long GL_CPU_SCS10_LO, CPU_TO_LE(0x00000000)
|
| 314 |
|
|
.long GL_CPU_SCS10_HI, CPU_TO_LE(0x00000003)
|
| 315 |
|
|
.long GL_CPU_SCS32_LO, CPU_TO_LE(0x00000004)
|
| 316 |
|
|
.long GL_CPU_SCS32_HI, CPU_TO_LE(0x00000007)
|
| 317 |
|
|
|
| 318 |
|
|
.long GL_SDRAM_SCS0_LO, CPU_TO_LE(0x00000000)
|
| 319 |
|
|
.long GL_SDRAM_SCS0_HI, CPU_TO_LE(0x00000007)
|
| 320 |
|
|
.long GL_SDRAM_SCS1_LO, CPU_TO_LE(0x000000ff)
|
| 321 |
|
|
.long GL_SDRAM_SCS1_HI, CPU_TO_LE(0x00000000)
|
| 322 |
|
|
.long GL_SDRAM_SCS2_LO, CPU_TO_LE(0x00000008)
|
| 323 |
|
|
.long GL_SDRAM_SCS2_HI, CPU_TO_LE(0x0000000f)
|
| 324 |
|
|
.long GL_SDRAM_SCS3_LO, CPU_TO_LE(0x000000ff)
|
| 325 |
|
|
.long GL_SDRAM_SCS3_HI, CPU_TO_LE(0x00000000)
|
| 326 |
|
|
|
| 327 |
|
|
.long 0, 0
|
| 328 |
|
|
|
| 329 |
|
|
#endif // !CYG_HAL_STARTUP_RAM
|
| 330 |
|
|
|
| 331 |
|
|
##-----------------------------------------------------------------------------
|
| 332 |
|
|
## ISR tables.
|
| 333 |
|
|
|
| 334 |
|
|
.extern hal_default_isr
|
| 335 |
|
|
|
| 336 |
|
|
.data
|
| 337 |
|
|
|
| 338 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 339 |
|
|
.globl hal_interrupt_handlers
|
| 340 |
|
|
hal_interrupt_handlers:
|
| 341 |
|
|
.long hal_default_isr # chaining vector
|
| 342 |
|
|
|
| 343 |
|
|
.globl hal_interrupt_data
|
| 344 |
|
|
hal_interrupt_data:
|
| 345 |
|
|
.long 0 # chaining vector data
|
| 346 |
|
|
|
| 347 |
|
|
.globl hal_interrupt_objects
|
| 348 |
|
|
hal_interrupt_objects:
|
| 349 |
|
|
.long 0 # chaining vector object
|
| 350 |
|
|
|
| 351 |
|
|
.globl cyg_hal_interrupt_level
|
| 352 |
|
|
cyg_hal_interrupt_level:
|
| 353 |
|
|
.rept CYGNUM_HAL_ISR_COUNT
|
| 354 |
|
|
.byte 0
|
| 355 |
|
|
.endr
|
| 356 |
|
|
|
| 357 |
|
|
#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 358 |
|
|
|
| 359 |
|
|
.globl hal_interrupt_handlers
|
| 360 |
|
|
hal_interrupt_handlers:
|
| 361 |
|
|
.long hal_default_isr
|
| 362 |
|
|
.long hal_default_isr
|
| 363 |
|
|
.long hal_default_isr
|
| 364 |
|
|
.long hal_default_isr
|
| 365 |
|
|
.long hal_default_isr
|
| 366 |
|
|
.long hal_default_isr
|
| 367 |
|
|
.long hal_default_isr
|
| 368 |
|
|
.long hal_default_isr
|
| 369 |
|
|
.long hal_default_isr
|
| 370 |
|
|
.long hal_default_isr
|
| 371 |
|
|
|
| 372 |
|
|
.rept CYGNUM_HAL_ISR_COUNT-10
|
| 373 |
|
|
.long hal_default_isr
|
| 374 |
|
|
.endr
|
| 375 |
|
|
|
| 376 |
|
|
.globl hal_interrupt_data
|
| 377 |
|
|
hal_interrupt_data:
|
| 378 |
|
|
.long 0
|
| 379 |
|
|
.long 0
|
| 380 |
|
|
.long 0
|
| 381 |
|
|
.long 0
|
| 382 |
|
|
.long 0
|
| 383 |
|
|
.long 0
|
| 384 |
|
|
.long 0
|
| 385 |
|
|
.long 0
|
| 386 |
|
|
.long 0
|
| 387 |
|
|
.long 0
|
| 388 |
|
|
|
| 389 |
|
|
.rept CYGNUM_HAL_ISR_COUNT-10
|
| 390 |
|
|
.long 0
|
| 391 |
|
|
.endr
|
| 392 |
|
|
|
| 393 |
|
|
.globl hal_interrupt_objects
|
| 394 |
|
|
hal_interrupt_objects:
|
| 395 |
|
|
.rept CYGNUM_HAL_ISR_COUNT
|
| 396 |
|
|
.long 0
|
| 397 |
|
|
.endr
|
| 398 |
|
|
|
| 399 |
|
|
.globl cyg_hal_interrupt_level
|
| 400 |
|
|
cyg_hal_interrupt_level:
|
| 401 |
|
|
.rept CYGNUM_HAL_ISR_COUNT
|
| 402 |
|
|
.byte 0
|
| 403 |
|
|
.endr
|
| 404 |
|
|
|
| 405 |
|
|
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 406 |
|
|
|
| 407 |
|
|
##-----------------------------------------------------------------------------
|
| 408 |
|
|
## end of platform.S
|
