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#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// imp_intr.h
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//
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// RM7000 Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov
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// Date: 2000-05-09
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// Purpose: RM7000 Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for variants of the RM7000 MIPS
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// architecture.
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//
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// Usage:
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// #include <cyg/hal/var_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// Interrupt controller information
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else \
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{ \
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/* int 6:9 are masked in the Interrupt Control register */ \
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asm volatile ( \
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"cfc0 $3,$20\n" \
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"la $2,0x00000004\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"ctc0 $3,$20\n" \
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"nop; nop; nop\n" \
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: \
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: "r"((_vector_) ) \
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: "$2", "$3" \
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); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else \
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{ \
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/* int 6:9 are masked in the Interrupt Control register */ \
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asm volatile ( \
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"cfc0 $3,$20\n" \
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"la $2,0x00000004\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"ctc0 $3,$20\n" \
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"nop; nop; nop\n" \
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: \
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: "r"((_vector_) ) \
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: "$2", "$3" \
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); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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/* All 10 interrupts have pending bits in the cause register */ \
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cyg_uint32 _srvector_ = _vector_; \
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asm volatile ( \
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"mfc0 $3,$13\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$13\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_srvector_) \
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: "$2", "$3" \
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); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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// Vectors and handling of these are defined in platform HALs since the
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// CPU itself does not have a builtin interrupt controller.
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//--------------------------------------------------------------------------
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// Clock control
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// This is handled by the default code
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_VAR_INTR_H
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// End of var_intr.h
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