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#ifndef CYGONCE_IMP_CACHE_H
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#define CYGONCE_IMP_CACHE_H
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//=============================================================================
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//
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// imp_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg
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// Date: 1998-02-17
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/imp_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_cache.h>
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//=============================================================================
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// Toshiba TX3904
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#ifdef CYGPKG_HAL_MIPS_TX3904
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//-----------------------------------------------------------------------------
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// Cache dimensions
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// Data cache
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#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 1 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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// This uses a bit in the config register, which is TX39 specific.
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#define HAL_DCACHE_ENABLE_DEFINED
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#define HAL_DCACHE_ENABLE() \
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{ \
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asm volatile ("mfc0 $2,$3;" \
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"ori $2,$2,0x0010;" \
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"mtc0 $2,$3;" \
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: \
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: \
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: "$2" \
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); \
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\
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}
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// Disable the data cache
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#define HAL_DCACHE_DISABLE_DEFINED
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#define HAL_DCACHE_DISABLE() \
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{ \
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asm volatile ("mfc0 $2,$3;" \
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"la $3,0xFFFFFFEF;" \
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"and $2,$2,$3;" \
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"mtc0 $2,$3;" \
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: \
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: \
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: "$2", "$3" \
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); \
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\
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}
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// Invalidate the entire cache
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// The TX39 only has hit-invalidate on the DCACHE, not
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// index-invalidate, so we cannot just empty the cache out without
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// knowing what is in it. This is annoying. So, the best we can do is
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// fill the cache with data that is unlikely to be there
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// otherwise. Hence we read bytes from the ROM space since this is
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// most likely to be code, and will not get out of sync even if it is not.
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#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
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#define HAL_DCACHE_INVALIDATE_ALL() \
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{ \
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volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000); \
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volatile CYG_BYTE tmp = 0; \
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int i; \
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for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
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{ \
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tmp = addr[i]; \
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} \
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}
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC_DEFINED
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#define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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//#define HAL_DCACHE_WRITETHRU_MODE 0
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//#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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#define HAL_DCACHE_LOCK_DEFINED
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#define HAL_DCACHE_LOCK(_base_, _size_) \
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{ \
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asm volatile ("mfc0 $2,$7;" \
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"ori $2,$2,0x0100;" \
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"mtc0 $2,$7;" \
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: \
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: \
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: "$2" \
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); \
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}
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// Undo a previous lock operation
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#define HAL_DCACHE_UNLOCK_DEFINED
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#define HAL_DCACHE_UNLOCK(_base_, _size_) \
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{ \
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asm volatile ("mfc0 $2,$7;" \
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"la $3,0xFFFFFEFF;" \
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"and $2,$2,$3;" \
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"mtc0 $2,$7;" \
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: \
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: \
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: "$2", "$3" \
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); \
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}
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// Unlock entire cache
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#define HAL_DCACHE_UNLOCK_ALL_DEFINED
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#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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#define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
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// Write dirty cache lines to memory for the given address range.
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//#define HAL_DCACHE_STORE( _base_ , _size_ )
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#define HAL_DCACHE_STORE_DEFINED // Disable default definition
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Enable the instruction cache
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// This uses a bit in the config register, which is TX39 specific.
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#define HAL_ICACHE_ENABLE_DEFINED
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#define HAL_ICACHE_ENABLE() \
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{ \
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asm volatile ("mfc0 $2,$3;" \
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"ori $2,$2,0x0020;" \
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"mtc0 $2,$3;" \
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: \
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: \
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: "$2" \
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); \
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\
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}
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// Disable the instruction cache
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#define HAL_ICACHE_DISABLE_DEFINED
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#define HAL_ICACHE_DISABLE() \
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{ \
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asm volatile ("mfc0 $2,$3;" \
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"la $3,0xFFFFFFDF;" \
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"and $2,$2,$3;" \
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"mtc0 $2,$3;" \
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"j 1f;" \
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"nop;" \
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".balign 16,0;" \
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"1:;" \
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: \
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: \
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: "$2", "$3" \
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); \
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\
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}
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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#define HAL_ICACHE_LOCK_DEFINED
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#define HAL_ICACHE_LOCK(_base_, _size_) \
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{ \
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asm volatile ("mfc0 $2,$7;" \
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"ori $2,$2,0x0200;" \
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"mtc0 $2,$7;" \
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: \
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: \
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: "$2" \
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); \
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}
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// Undo a previous lock operation
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#define HAL_ICACHE_UNLOCK_DEFINED
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#define HAL_ICACHE_UNLOCK(_base_, _size_) \
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{ \
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asm volatile ("mfc0 $2,$7;" \
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"la $3,0xFFFFFDFF;" \
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"and $2,$2,$3;" \
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"mtc0 $2,$7;" \
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: \
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: \
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: "$2", "$3" \
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); \
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}
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// Unlock entire cache
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#define HAL_ICACHE_UNLOCK_ALL_DEFINED
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#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// On the TX39, the instruction cache must be disabled to use the index-invalidate
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// cache operation.
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// Invalidate the entire cache
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// This uses the index-invalidate cache operation.
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#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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#define HAL_ICACHE_INVALIDATE_ALL() \
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{ \
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register CYG_ADDRESS _baddr_ = 0x80000000; \
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register CYG_ADDRESS _addr_ = 0x80000000; \
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register CYG_WORD _state_; \
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HAL_ICACHE_IS_ENABLED(_state_); \
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HAL_ICACHE_DISABLE(); \
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for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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{ \
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asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
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} \
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if( _state_ ) HAL_ICACHE_ENABLE(); \
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}
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// Invalidate cache lines in the given range without writing to memory.
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// This uses the index-invalidate cache operation since the TX39 does not
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// have hit-invalidate on the instruction cache.
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#define HAL_ICACHE_INVALIDATE_DEFINED
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#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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{ \
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register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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register CYG_WORD _size_ = (_asize_); \
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register CYG_WORD _state_; \
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HAL_ICACHE_IS_ENABLED(_state_); \
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HAL_ICACHE_DISABLE(); \
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for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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{ \
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asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
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} \
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if( _state_ ) HAL_ICACHE_ENABLE(); \
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}
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#endif // CYGPKG_HAL_MIPS_TX3904
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_IMP_CACHE_H
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// End of imp_cache.h
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