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#ifndef CYGONCE_VAR_CACHE_H
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#define CYGONCE_VAR_CACHE_H
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//=============================================================================
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//
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// var_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, nickg
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// Contributors: nickg
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// Date: 2001-05-24
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/var_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_cache.h>
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//-----------------------------------------------------------------------------
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// Cache sizes.
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// Data cache
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#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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#define HAL_DCACHE_WAYS 1 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 1 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// The uPD985xx mostly uses the default MIPS cache controls defined in
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// hal_cache.h Here we define the cache enable and disable macros. The only
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// control we appear to have is the kseg0 cache state in config0. So all
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// these macros at present manipulate this.
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#ifndef HAL_DCACHE_ENABLE_DEFINED
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( "mfc0 $2,$16\n" \
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"nop; nop; nop\n" \
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"la $3,0xFFFFFFF8\n" \
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"and $2,$2,$3\n" \
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"ori $2,$2,3\n" \
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"mtc0 $2,$16\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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: \
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: \
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: "$2", "$3" \
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); \
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CYG_MACRO_END
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#define HAL_DCACHE_ENABLE_DEFINED
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#endif
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// Disable the data cache
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#ifndef HAL_DCACHE_DISABLE_DEFINED
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( "mfc0 $2,$16\n" \
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"nop; nop; nop\n" \
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"la $3,0xFFFFFFF8\n" \
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"and $2,$2,$3\n" \
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"ori $2,$2,2\n" \
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"mtc0 $2,$16\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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"nop; nop; nop; nop;\n" \
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: \
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: \
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: "$2", "$3" \
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); \
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CYG_MACRO_END
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#define HAL_DCACHE_DISABLE_DEFINED
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#endif
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#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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CYG_WORD32 _cstate_; \
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asm volatile ( "mfc0 %0,$16\n" \
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"nop; nop; nop\n" \
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: "=r"(_cstate_) \
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); \
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if( (_cstate_ & 7) == 2 ) _state_ = 0; \
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else _state_ = 1; \
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CYG_MACRO_END
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#define HAL_DCACHE_IS_ENABLED_DEFINED
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#endif
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#ifndef HAL_ICACHE_ENABLE_DEFINED
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#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
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#define HAL_ICACHE_ENABLE_DEFINED
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#endif
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// Disable the instruction cache
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#ifndef HAL_ICACHE_DISABLE_DEFINED
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#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
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#define HAL_ICACHE_DISABLE_DEFINED
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#endif
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#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
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#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
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#define HAL_ICACHE_IS_ENABLED_DEFINED
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#endif
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//-----------------------------------------------------------------------------
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// The VR4300 has no cache locking facility so we define the guard macros
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// to disable the definitions in hal_arch.h.
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#define HAL_DCACHE_LOCK_DEFINED
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#define HAL_DCACHE_UNLOCK_DEFINED
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#define HAL_DCACHE_UNLOCK_ALL_DEFINED
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#define HAL_ICACHE_LOCK_DEFINED
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#define HAL_ICACHE_UNLOCK_DEFINED
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_VAR_CACHE_H
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// End of var_cache.h
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