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#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// VR4300 Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour
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// Date: 2001-05-24
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// Purpose: uPD985xx Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for variants of the NEC uPD985xx
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// architecture.
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//
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// Usage:
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// #include <cyg/hal/var_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <cyg/hal/var_arch.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// Interrupt controller stuff.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// Interrupts dealt with via the status and cause registers
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// must be numbered in bit order:
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#define CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW (0)
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// The first two are the "software interrupts" - you just set a bit.
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#define CYGNUM_HAL_INTERRUPT_SOFT_ZERO (0)
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#define CYGNUM_HAL_INTERRUPT_SOFT_ONE (1)
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#define CYGNUM_HAL_INTERRUPT_FREE_TWO (2)
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#define CYGNUM_HAL_INTERRUPT_USB (3)
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#define CYGNUM_HAL_INTERRUPT_ETHER (4)
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#define CYGNUM_HAL_INTERRUPT_FREE_FIVE (5)
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#define CYGNUM_HAL_INTERRUPT_SYSCTL (6)
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#define CYGNUM_HAL_INTERRUPT_COMPARE (7)
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// Number 6 "SYSCTL" is all external sources in the system controller and
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// will normally be decoded into one of 8-12 instead. If you use number 6
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// directly, then this will disable *all* system controller sources.
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// Startup code will ensure number 6 is unmasked by default, and it will
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// have an arbitration routine installed to call all of the subsequent
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// interrupts from the S_ISR register. This has to be an external routine
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// because the S_ISR register is read-clear, and the interrupt sources are
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// edge-triggered so they do not re-assert themselves - so we must address
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// multiple sources per actual interrupt, in a loop.
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#define CYGNUM_HAL_INTERRUPT_SYSCTL_LOW (8)
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#define CYGNUM_HAL_INTERRUPT_SYSCTL_HI (12)
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#define CYGNUM_HAL_INTERRUPT_TM0 (8) // TIMER CH0 interrupt.
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#define CYGNUM_HAL_INTERRUPT_TM1 (9) // TIMER CH1 interrupt.
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#define CYGNUM_HAL_INTERRUPT_UART (10) // UART interrupt.
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#define CYGNUM_HAL_INTERRUPT_EXT (11) // External Interrupt.
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#define CYGNUM_HAL_INTERRUPT_WU (12) // Wakeup Interrupt.
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#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 12
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#define CYGNUM_HAL_ISR_COUNT 13
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// The vector used by the Real time clock. The default here is to use
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// interrupt 5, which is connected to the counter/comparator registers
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// in many MIPS variants.
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#ifndef CYGNUM_HAL_INTERRUPT_RTC
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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#endif
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif // CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#ifndef __ASSEMBLER__
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// ------------------------------------------------------------------------
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// This is placed in memory at a fixed location because we must share it
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// with RedBoot, along with the VSR table and Virtual Vector table.
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// It has to be an array to get the correct code generation to access it
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// over all that distance.
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externC volatile cyg_uint32 hal_interrupt_sr_mask_shadow_base[];
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#define hal_interrupt_sr_mask_shadow (hal_interrupt_sr_mask_shadow_base[0])
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// We have to have local versions of these to preserve the mask bits in the
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// SR correctly when an interrupt occurs within one of these code sequences
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// which are doing a read-modify-write to the main interrupt bit of the SR.
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// Disable, it doesn't matter what the SR IM bits are - but it is possible
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// for control to return with interrupts enabled if a context switch occurs
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// away from the thread that disabled interrupts. Therefore we also make
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// sure the contents of the SR match the shadow variable at the end.
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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register int _tmp; \
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asm volatile ( \
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"mfc0 $8,$12; nop;" \
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"move %0,$8;" \
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"and $8,$8,0xfffffffe;" \
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"mtc0 $8,$12;" \
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"nop; nop; nop;" \
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: "=r"(_tmp) \
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: \
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: "$8" \
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); \
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/* interrupts disabled so can now inject the correct IM bits */ \
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(_old_) = _tmp & 1; \
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_tmp &= 0xffff00fe; \
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_tmp |= (hal_interrupt_sr_mask_shadow & 0xff00); \
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asm volatile ( \
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"mtc0 %0,$12;" \
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"nop; nop; nop;" \
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: \
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: "r"(_tmp) \
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); \
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CYG_MACRO_END
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// Enable and restore, we must pick up hal_interrupt_sr_mask_shadow because
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// it contains the truth. This is also for the convenience of the
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// mask/unmask macros below.
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#define HAL_ENABLE_INTERRUPTS() HAL_RESTORE_INTERRUPTS(1)
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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asm volatile ( \
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"mfc0 $8,$12; nop;" \
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"or $8,$8,%0;" /* inject IE bit */ \
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"and $8,$8,0xffff00ff;" /* clear IM bits */ \
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"or $8,$8,%1;" /* insert true IM */ \
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"mtc0 $8,$12;" \
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"nop; nop; nop;" \
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: \
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: "r"((_old_) & 1),"r"(hal_interrupt_sr_mask_shadow & 0xff00) \
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: "$8" \
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); \
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CYG_MACRO_END
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#define HAL_QUERY_INTERRUPTS( _state_ ) \
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CYG_MACRO_START \
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asm volatile ( \
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"mfc0 %0,$12; nop;" \
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"and %0,%0,0x1;" \
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: "=r"(_state_) \
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); \
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CYG_MACRO_END
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#define CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
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// ------------------------------------------------------------------------
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// For the bits which are in the SR, we only need to diddle the shadow
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// variable; restore interrupts will pick that up at the end of the macro.
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// Neat, huh.
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#ifndef CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
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// Vanilla versions here: trick versions with the workaround follow:
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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register int _intstate; \
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register int _shift; \
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HAL_DISABLE_INTERRUPTS( _intstate ); \
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if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
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/* mask starts at bit 8 */ \
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_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
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hal_interrupt_sr_mask_shadow &=~(1 << _shift); \
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} \
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else { \
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_shift = (_vector_) - CYGNUM_HAL_INTERRUPT_SYSCTL_LOW; \
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*S_IMR &=~(1 << _shift); \
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} \
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HAL_RESTORE_INTERRUPTS( _intstate ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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register int _intstate; \
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register int _shift; \
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HAL_DISABLE_INTERRUPTS( _intstate ); \
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if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
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/* mask starts at bit 8 */ \
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_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
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hal_interrupt_sr_mask_shadow |= (1 << _shift); \
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} \
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else { \
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_shift = (_vector_) - CYGNUM_HAL_INTERRUPT_SYSCTL_LOW; \
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*S_IMR |= (1 << _shift); \
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} \
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HAL_RESTORE_INTERRUPTS( _intstate ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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register int _intstate; \
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HAL_DISABLE_INTERRUPTS( _intstate ); \
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/* Default clears the bit in the cause register. But VR4120 doc */ \
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/* says this is a NOP so we ignore low numbered sources except the */ \
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/* software interrupt bits. */ \
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if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= (_vector_) || \
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CYGNUM_HAL_INTERRUPT_SYSCTL == (_vector_) ) { \
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register int i; \
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i = *S_ISR; /* This is read-clear! */ \
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} \
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else if ( CYGNUM_HAL_INTERRUPT_SOFT_ZERO == (_vector_) || \
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CYGNUM_HAL_INTERRUPT_SOFT_ONE == (_vector_) ) { \
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/* These two are acknowledged by writing the bit to zero in */ \
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/* the cause register. NB not the status register! */ \
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asm volatile ( \
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"mfc0 $3,$13\n" \
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"la $2,0x00000100\n" \
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"sllv $2,$2,%0\n" \
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"andi $2,$2,0x0300\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$13\n" \
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"nop; nop; nop\n" \
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: \
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: "r"((_vector_)-CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW) \
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: "$2", "$3" \
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); \
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} \
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HAL_RESTORE_INTERRUPTS( _intstate ); \
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CYG_MACRO_END
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#else // DEFINED: CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
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#ifdef __cplusplus
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| 278 |
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extern "C" {
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#endif
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| 280 |
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extern void cyg_hal_interrupt_unmask( int vec );
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extern void cyg_hal_interrupt_mask( int vec );
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| 282 |
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extern void cyg_hal_interrupt_acknowledge( int vec );
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| 283 |
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#ifdef __cplusplus
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| 284 |
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} /* extern "C" */
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| 285 |
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#endif
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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| 288 |
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CYG_MACRO_START \
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register int _intstate; \
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register int _shift; \
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HAL_DISABLE_INTERRUPTS( _intstate ); \
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if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
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/* mask starts at bit 8 */ \
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_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
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hal_interrupt_sr_mask_shadow &=~(1 << _shift); \
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} \
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| 297 |
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else { \
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| 298 |
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cyg_hal_interrupt_mask( (_vector_) ); \
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} \
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| 300 |
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HAL_RESTORE_INTERRUPTS( _intstate ); \
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| 301 |
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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| 306 |
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register int _intstate; \
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| 307 |
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register int _shift; \
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| 308 |
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HAL_DISABLE_INTERRUPTS( _intstate ); \
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| 309 |
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if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
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| 310 |
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/* mask starts at bit 8 */ \
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| 311 |
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_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
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| 312 |
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hal_interrupt_sr_mask_shadow |= (1 << _shift); \
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} \
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| 314 |
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else { \
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| 315 |
|
|
cyg_hal_interrupt_unmask( (_vector_) ); \
|
| 316 |
|
|
} \
|
| 317 |
|
|
HAL_RESTORE_INTERRUPTS( _intstate ); \
|
| 318 |
|
|
CYG_MACRO_END
|
| 319 |
|
|
|
| 320 |
|
|
|
| 321 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 322 |
|
|
CYG_MACRO_START \
|
| 323 |
|
|
register int _intstate; \
|
| 324 |
|
|
HAL_DISABLE_INTERRUPTS( _intstate ); \
|
| 325 |
|
|
/* Default clears the bit in the cause register. But VR4120 doc */ \
|
| 326 |
|
|
/* says this is a NOP so we ignore low numbered sources except the */ \
|
| 327 |
|
|
/* software interrupt bits. */ \
|
| 328 |
|
|
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= (_vector_) || \
|
| 329 |
|
|
CYGNUM_HAL_INTERRUPT_SYSCTL == (_vector_) ) { \
|
| 330 |
|
|
cyg_hal_interrupt_acknowledge( (_vector_) ); \
|
| 331 |
|
|
} \
|
| 332 |
|
|
else if ( CYGNUM_HAL_INTERRUPT_SOFT_ZERO == (_vector_) || \
|
| 333 |
|
|
CYGNUM_HAL_INTERRUPT_SOFT_ONE == (_vector_) ) { \
|
| 334 |
|
|
/* These two are acknowledged by writing the bit to zero in */ \
|
| 335 |
|
|
/* the cause register. NB not the status register! */ \
|
| 336 |
|
|
asm volatile ( \
|
| 337 |
|
|
"mfc0 $3,$13\n" \
|
| 338 |
|
|
"la $2,0x00000100\n" \
|
| 339 |
|
|
"sllv $2,$2,%0\n" \
|
| 340 |
|
|
"andi $2,$2,0x0300\n" \
|
| 341 |
|
|
"nor $2,$2,$0\n" \
|
| 342 |
|
|
"and $3,$3,$2\n" \
|
| 343 |
|
|
"mtc0 $3,$13\n" \
|
| 344 |
|
|
"nop; nop; nop\n" \
|
| 345 |
|
|
: \
|
| 346 |
|
|
: "r"((_vector_)-CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW) \
|
| 347 |
|
|
: "$2", "$3" \
|
| 348 |
|
|
); \
|
| 349 |
|
|
} \
|
| 350 |
|
|
HAL_RESTORE_INTERRUPTS( _intstate ); \
|
| 351 |
|
|
CYG_MACRO_END
|
| 352 |
|
|
|
| 353 |
|
|
#endif // CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
|
| 354 |
|
|
|
| 355 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
|
| 356 |
|
|
|
| 357 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
|
| 358 |
|
|
|
| 359 |
|
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 360 |
|
|
|
| 361 |
|
|
//--------------------------------------------------------------------------
|
| 362 |
|
|
// Useful for debugging...
|
| 363 |
|
|
|
| 364 |
|
|
#define HAL_READ_INTR_REGS( _status, _cause ) \
|
| 365 |
|
|
{ \
|
| 366 |
|
|
asm volatile ( \
|
| 367 |
|
|
"mfc0 %0,$12; nop;" \
|
| 368 |
|
|
: "=r"(_status) \
|
| 369 |
|
|
); \
|
| 370 |
|
|
asm volatile ( \
|
| 371 |
|
|
"mfc0 %0,$13; nop;" \
|
| 372 |
|
|
: "=r"(_cause) \
|
| 373 |
|
|
); \
|
| 374 |
|
|
}
|
| 375 |
|
|
|
| 376 |
|
|
//--------------------------------------------------------------------------
|
| 377 |
|
|
#endif // ! __ASSEMBLER__
|
| 378 |
|
|
|
| 379 |
|
|
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
|
| 380 |
|
|
// End of var_intr.h
|
