| 1 |
27 |
unneback |
#ifndef CYGONCE_HAL_PLF_INTR_H
|
| 2 |
|
|
#define CYGONCE_HAL_PLF_INTR_H
|
| 3 |
|
|
|
| 4 |
|
|
//==========================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// plf_intr.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// VRC437X Interrupt and clock support
|
| 9 |
|
|
//
|
| 10 |
|
|
//==========================================================================
|
| 11 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 21 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 26 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 30 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 31 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 32 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 33 |
|
|
// License. However the source code for this file must still be made available
|
| 34 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 37 |
|
|
// this file might be covered by the GNU General Public License.
|
| 38 |
|
|
//
|
| 39 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 40 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 41 |
|
|
// -------------------------------------------
|
| 42 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 43 |
|
|
//==========================================================================
|
| 44 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 45 |
|
|
//
|
| 46 |
|
|
// Author(s): nickg
|
| 47 |
|
|
// Contributors: nickg, jskov,
|
| 48 |
|
|
// gthomas, jlarmour
|
| 49 |
|
|
// Date: 1999-02-16
|
| 50 |
|
|
// Purpose: Define Interrupt support
|
| 51 |
|
|
// Description: The macros defined here provide the HAL APIs for handling
|
| 52 |
|
|
// interrupts and the clock for the VRC437X board.
|
| 53 |
|
|
//
|
| 54 |
|
|
// Usage:
|
| 55 |
|
|
// #include <cyg/hal/plf_intr.h>
|
| 56 |
|
|
// ...
|
| 57 |
|
|
//
|
| 58 |
|
|
//
|
| 59 |
|
|
//####DESCRIPTIONEND####
|
| 60 |
|
|
//
|
| 61 |
|
|
//==========================================================================
|
| 62 |
|
|
|
| 63 |
|
|
#include <pkgconf/hal.h>
|
| 64 |
|
|
|
| 65 |
|
|
#include <cyg/infra/cyg_type.h>
|
| 66 |
|
|
|
| 67 |
|
|
//--------------------------------------------------------------------------
|
| 68 |
|
|
// Interrupt controller stuff.
|
| 69 |
|
|
|
| 70 |
|
|
// The first 6 correspond to the interrupt lines in the status/cause regs
|
| 71 |
|
|
#define CYGNUM_HAL_INTERRUPT_VRC437X 0
|
| 72 |
|
|
#define CYGNUM_HAL_INTERRUPT_IPL0 1
|
| 73 |
|
|
#define CYGNUM_HAL_INTERRUPT_IPL1 2
|
| 74 |
|
|
#define CYGNUM_HAL_INTERRUPT_IPL2 3
|
| 75 |
|
|
#define CYGNUM_HAL_INTERRUPT_POWER 4
|
| 76 |
|
|
#define CYGNUM_HAL_INTERRUPT_COMPARE 5
|
| 77 |
|
|
// The next 32 correspond to the interrupt lines in the 4372 interrupt
|
| 78 |
|
|
// controller. These are decoded from the controller when an interrupt
|
| 79 |
|
|
// on any of the IPL[0:2] lines in signalled.
|
| 80 |
|
|
#define CYGNUM_HAL_INTERRUPT_REALTIME_A 6
|
| 81 |
|
|
#define CYGNUM_HAL_INTERRUPT_REALTIME_B 7
|
| 82 |
|
|
#define CYGNUM_HAL_INTERRUPT_DUART 8
|
| 83 |
|
|
#define CYGNUM_HAL_INTERRUPT_TIMER 9
|
| 84 |
|
|
#define CYGNUM_HAL_INTERRUPT_PARALLEL 10
|
| 85 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_INTA 11
|
| 86 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_INTB 12
|
| 87 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_INTC 13
|
| 88 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_INTD 14
|
| 89 |
|
|
#define CYGNUM_HAL_INTERRUPT_INT_9 15
|
| 90 |
|
|
#define CYGNUM_HAL_INTERRUPT_INT_10 16
|
| 91 |
|
|
#define CYGNUM_HAL_INTERRUPT_INT_11 17
|
| 92 |
|
|
#define CYGNUM_HAL_INTERRUPT_INT_12 18
|
| 93 |
|
|
#define CYGNUM_HAL_INTERRUPT_INT_13 19
|
| 94 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA_0 20
|
| 95 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA_1 21
|
| 96 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA_2 22
|
| 97 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA_3 23
|
| 98 |
|
|
#define CYGNUM_HAL_INTERRUPT_TICK_0 24
|
| 99 |
|
|
#define CYGNUM_HAL_INTERRUPT_TICK_1 25
|
| 100 |
|
|
#define CYGNUM_HAL_INTERRUPT_UNUSED_20 26
|
| 101 |
|
|
#define CYGNUM_HAL_INTERRUPT_UNUSED_21 27
|
| 102 |
|
|
#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28
|
| 103 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_PERR 29
|
| 104 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_SERR 30
|
| 105 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31
|
| 106 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32
|
| 107 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33
|
| 108 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_ADD 34
|
| 109 |
|
|
#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35
|
| 110 |
|
|
#define CYGNUM_HAL_INTERRUPT_UNUSED_30 36
|
| 111 |
|
|
#define CYGNUM_HAL_INTERRUPT_UNUSED_31 37
|
| 112 |
|
|
|
| 113 |
|
|
// Min/Max ISR numbers and how many there are
|
| 114 |
|
|
#define CYGNUM_HAL_ISR_MIN 0
|
| 115 |
|
|
#define CYGNUM_HAL_ISR_MAX 37
|
| 116 |
|
|
#define CYGNUM_HAL_ISR_COUNT 38
|
| 117 |
|
|
|
| 118 |
|
|
// The vector used by the Real time clock. The default here is to use
|
| 119 |
|
|
// interrupt 5, which is connected to the counter/comparator registers
|
| 120 |
|
|
// in many MIPS variants.
|
| 121 |
|
|
|
| 122 |
|
|
#ifndef CYGNUM_HAL_INTERRUPT_RTC
|
| 123 |
|
|
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
|
| 124 |
|
|
#endif
|
| 125 |
|
|
|
| 126 |
|
|
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
|
| 127 |
|
|
|
| 128 |
|
|
//--------------------------------------------------------------------------
|
| 129 |
|
|
// Vector translation.
|
| 130 |
|
|
// For chained interrupts we only have a single vector though which all
|
| 131 |
|
|
// are passed. For unchained interrupts we have a vector per interrupt.
|
| 132 |
|
|
// Vector 0 has a special catcher ISR for spurious interrupts from the VRC437X
|
| 133 |
|
|
// and vectors 1-3 are springboards, so we chain through vector 4.
|
| 134 |
|
|
|
| 135 |
|
|
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
|
| 136 |
|
|
|
| 137 |
|
|
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
|
| 138 |
|
|
{ \
|
| 139 |
|
|
if ((_vector_)==0) \
|
| 140 |
|
|
(_index_) = 0; \
|
| 141 |
|
|
else \
|
| 142 |
|
|
(_index_) = 4; \
|
| 143 |
|
|
}
|
| 144 |
|
|
#endif
|
| 145 |
|
|
|
| 146 |
|
|
//--------------------------------------------------------------------------
|
| 147 |
|
|
// controller access code
|
| 148 |
|
|
|
| 149 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_BASE 0xbc000000
|
| 150 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_POL (CYGHWR_HAL_MIPS_VRC4372_BASE+0x200)
|
| 151 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4372_BASE+0x204)
|
| 152 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_PINS (CYGHWR_HAL_MIPS_VRC4372_BASE+0x208)
|
| 153 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x20c)
|
| 154 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x210)
|
| 155 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x214)
|
| 156 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x218)
|
| 157 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x21c)
|
| 158 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x220)
|
| 159 |
|
|
|
| 160 |
|
|
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF 8
|
| 161 |
|
|
|
| 162 |
|
|
// Array which stores the configured priority levels for the configured
|
| 163 |
|
|
// interrupts.
|
| 164 |
|
|
externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
|
| 165 |
|
|
|
| 166 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 167 |
|
|
CYG_MACRO_START \
|
| 168 |
|
|
if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
|
| 169 |
|
|
{ \
|
| 170 |
|
|
asm volatile ( \
|
| 171 |
|
|
"mfc0 $3,$12\n" \
|
| 172 |
|
|
"la $2,0x00000400\n" \
|
| 173 |
|
|
"sllv $2,$2,%0\n" \
|
| 174 |
|
|
"nor $2,$2,$0\n" \
|
| 175 |
|
|
"and $3,$3,$2\n" \
|
| 176 |
|
|
"mtc0 $3,$12\n" \
|
| 177 |
|
|
"nop; nop; nop\n" \
|
| 178 |
|
|
: \
|
| 179 |
|
|
: "r"(_vector_) \
|
| 180 |
|
|
: "$2", "$3" \
|
| 181 |
|
|
); \
|
| 182 |
|
|
} \
|
| 183 |
|
|
else \
|
| 184 |
|
|
{ \
|
| 185 |
|
|
CYG_WORD32 _mask_; \
|
| 186 |
|
|
CYG_BYTE _shift_; \
|
| 187 |
|
|
HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
|
| 188 |
|
|
cyg_hal_interrupt_level[_vector_] * \
|
| 189 |
|
|
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
|
| 190 |
|
|
HAL_READ_UINT32( _maskreg_, _mask_ ); \
|
| 191 |
|
|
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
|
| 192 |
|
|
_mask_ &= ~(1<<_shift_); \
|
| 193 |
|
|
HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
|
| 194 |
|
|
} \
|
| 195 |
|
|
CYG_MACRO_END
|
| 196 |
|
|
|
| 197 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 198 |
|
|
CYG_MACRO_START \
|
| 199 |
|
|
if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
|
| 200 |
|
|
{ \
|
| 201 |
|
|
asm volatile ( \
|
| 202 |
|
|
"mfc0 $3,$12\n" \
|
| 203 |
|
|
"la $2,0x00000400\n" \
|
| 204 |
|
|
"sllv $2,$2,%0\n" \
|
| 205 |
|
|
"or $3,$3,$2\n" \
|
| 206 |
|
|
"mtc0 $3,$12\n" \
|
| 207 |
|
|
"nop; nop; nop\n" \
|
| 208 |
|
|
: \
|
| 209 |
|
|
: "r"(_vector_) \
|
| 210 |
|
|
: "$2", "$3" \
|
| 211 |
|
|
); \
|
| 212 |
|
|
} \
|
| 213 |
|
|
else \
|
| 214 |
|
|
{ \
|
| 215 |
|
|
CYG_WORD32 _mask_; \
|
| 216 |
|
|
CYG_BYTE _shift_; \
|
| 217 |
|
|
HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
|
| 218 |
|
|
cyg_hal_interrupt_level[_vector_] * \
|
| 219 |
|
|
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
|
| 220 |
|
|
HAL_READ_UINT32( _maskreg_, _mask_ ); \
|
| 221 |
|
|
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
|
| 222 |
|
|
_mask_ |= 1<<_shift_; \
|
| 223 |
|
|
HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
|
| 224 |
|
|
} \
|
| 225 |
|
|
CYG_MACRO_END
|
| 226 |
|
|
|
| 227 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 228 |
|
|
CYG_MACRO_START \
|
| 229 |
|
|
CYG_WORD32 _srvector_ = _vector_; \
|
| 230 |
|
|
if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
|
| 231 |
|
|
{ \
|
| 232 |
|
|
CYG_WORD32 _stat_; \
|
| 233 |
|
|
CYG_BYTE _shift_; \
|
| 234 |
|
|
HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 +\
|
| 235 |
|
|
cyg_hal_interrupt_level[_vector_] * \
|
| 236 |
|
|
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
|
| 237 |
|
|
HAL_READ_UINT32( _statreg_, _stat_ ); \
|
| 238 |
|
|
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
|
| 239 |
|
|
_stat_ &= ~(1<<_shift_); \
|
| 240 |
|
|
HAL_WRITE_UINT32( _statreg_, _stat_ ); \
|
| 241 |
|
|
_srvector_ = cyg_hal_interrupt_level[_vector_] + \
|
| 242 |
|
|
CYGNUM_HAL_INTERRUPT_IPL0; \
|
| 243 |
|
|
} \
|
| 244 |
|
|
asm volatile ( \
|
| 245 |
|
|
"mfc0 $3,$13\n" \
|
| 246 |
|
|
"la $2,0x00000400\n" \
|
| 247 |
|
|
"sllv $2,$2,%0\n" \
|
| 248 |
|
|
"nor $2,$2,$0\n" \
|
| 249 |
|
|
"and $3,$3,$2\n" \
|
| 250 |
|
|
"mtc0 $3,$13\n" \
|
| 251 |
|
|
"nop; nop; nop\n" \
|
| 252 |
|
|
: \
|
| 253 |
|
|
: "r"(_srvector_) \
|
| 254 |
|
|
: "$2", "$3" \
|
| 255 |
|
|
); \
|
| 256 |
|
|
CYG_MACRO_END
|
| 257 |
|
|
|
| 258 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
|
| 259 |
|
|
CYG_MACRO_START \
|
| 260 |
|
|
if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \
|
| 261 |
|
|
(_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \
|
| 262 |
|
|
{ \
|
| 263 |
|
|
CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \
|
| 264 |
|
|
CYG_WORD32 pol; \
|
| 265 |
|
|
CYG_WORD32 trig; \
|
| 266 |
|
|
HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
|
| 267 |
|
|
HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
|
| 268 |
|
|
if( _level_ ) \
|
| 269 |
|
|
{ \
|
| 270 |
|
|
pol &= ~mask; \
|
| 271 |
|
|
if( _up_ ) trig |= mask; \
|
| 272 |
|
|
else trig &= ~mask; \
|
| 273 |
|
|
} \
|
| 274 |
|
|
else \
|
| 275 |
|
|
{ \
|
| 276 |
|
|
pol |= mask; \
|
| 277 |
|
|
if( !(_up_) ) trig |= mask; \
|
| 278 |
|
|
else trig &= ~mask; \
|
| 279 |
|
|
} \
|
| 280 |
|
|
HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
|
| 281 |
|
|
HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
|
| 282 |
|
|
} \
|
| 283 |
|
|
CYG_MACRO_END
|
| 284 |
|
|
|
| 285 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
|
| 286 |
|
|
CYG_MACRO_START \
|
| 287 |
|
|
if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
|
| 288 |
|
|
{ \
|
| 289 |
|
|
cyg_uint32 _ilevel_ = _level_; \
|
| 290 |
|
|
while( _ilevel_ > 2 ) _ilevel_ -= 2; \
|
| 291 |
|
|
cyg_hal_interrupt_level[_vector_] = _ilevel_; \
|
| 292 |
|
|
} \
|
| 293 |
|
|
CYG_MACRO_END
|
| 294 |
|
|
|
| 295 |
|
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 296 |
|
|
|
| 297 |
|
|
//--------------------------------------------------------------------------
|
| 298 |
|
|
// Control-C support.
|
| 299 |
|
|
|
| 300 |
|
|
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
|
| 301 |
|
|
|
| 302 |
|
|
# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
|
| 303 |
|
|
|
| 304 |
|
|
externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
|
| 305 |
|
|
|
| 306 |
|
|
#define HAL_CTRLC_ISR hal_ctrlc_isr
|
| 307 |
|
|
|
| 308 |
|
|
#endif
|
| 309 |
|
|
|
| 310 |
|
|
//----------------------------------------------------------------------------
|
| 311 |
|
|
// Reset.
|
| 312 |
|
|
|
| 313 |
|
|
#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
|
| 314 |
|
|
|
| 315 |
|
|
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
|
| 316 |
|
|
|
| 317 |
|
|
//--------------------------------------------------------------------------
|
| 318 |
|
|
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
|
| 319 |
|
|
// End of plf_intr.h
|
