OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [am33/] [v2_0/] [include/] [var_arch.h] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_VAR_ARCH_H
2
#define CYGONCE_HAL_VAR_ARCH_H
3
 
4
//==========================================================================
5
//
6
//      var_arch.h
7
//
8
//      Architecture specific abstractions
9
//
10
//==========================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//==========================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    nickg
47
// Contributors: nickg, dmoseley
48
// Date:         1999-02-17
49
// Purpose:      Define architecture abstractions
50
// Description:  This file contains any extra or modified definitions for
51
//               this variant of the architecture.
52
// Usage:        #include <cyg/hal/var_arch.h>
53
//              
54
//####DESCRIPTIONEND####
55
//
56
//==========================================================================
57
 
58
#include <pkgconf/hal.h>
59
#include <cyg/infra/cyg_type.h>
60
 
61
//--------------------------------------------------------------------------
62
// Processor Status word bitmasks
63
 
64
#define HAL_ARCH_AM33_PSW_nSL           (1L << 16)
65
#define HAL_ARCH_AM33_PSW_ML            (1L << 19)
66
#define HAL_ARCH_AM33_PSW_FE            (1L << 20)
67
 
68
//--------------------------------------------------------------------------
69
// Processor saved states:
70
 
71
typedef struct HAL_SavedRegisters
72
{
73
    // These are common to all saved states and are in the order
74
    // stored and loaded by the movm instruction.
75
    CYG_ADDRWORD        vector;         /* Vector number/dummy          */
76
    CYG_ADDRWORD        lar;            /* Loop address register        */
77
    CYG_ADDRWORD        lir;            /* Loop instruction register    */
78
    CYG_ADDRWORD        mdr;            /* Multiply/Divide register     */
79
    CYG_ADDRWORD        a1;
80
    CYG_ADDRWORD        a0;
81
    CYG_ADDRWORD        d1;
82
    CYG_ADDRWORD        d0;
83
    CYG_ADDRWORD        a3;
84
    CYG_ADDRWORD        a2;
85
    CYG_ADDRWORD        d3;
86
    CYG_ADDRWORD        d2;
87
    CYG_ADDRWORD        mcvf;           /* MAC overflow flag            */
88
    CYG_ADDRWORD        mcrl;           /* MAC register low             */
89
    CYG_ADDRWORD        mcrh;           /* MAC register high            */
90
    CYG_ADDRWORD        mdrq;           /* Fast multiply/divide register*/
91
    CYG_ADDRWORD        e1;             /* extended registers           */
92
    CYG_ADDRWORD        e0;
93
    CYG_ADDRWORD        e7;
94
    CYG_ADDRWORD        e6;
95
    CYG_ADDRWORD        e5;
96
    CYG_ADDRWORD        e4;
97
    CYG_ADDRWORD        e3;
98
    CYG_ADDRWORD        e2;
99
 
100
    /* On interrupts the PC and PSW are pushed automatically by the     */
101
    /* CPU and SP is pushed for debugging reasons. On a thread switch   */
102
    /* the saved context is made to look the same.                      */
103
 
104
    CYG_ADDRWORD  sp;             /* Saved copy of SP in some states      */
105
    CYG_ADDRWORD  psw;            /* Status word                          */
106
    CYG_ADDRWORD  pc;             /* Program Counter                      */
107
 
108
} HAL_SavedRegisters;
109
 
110
//--------------------------------------------------------------------------
111
// Extra initialization for AM33 extended register set.
112
 
113
#define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_)     \
114
CYG_MACRO_START                                         \
115
    (_regs_)->e0        = (_id_)|0xeee0;                \
116
    (_regs_)->e1        = (_id_)|0xeee1;                \
117
    (_regs_)->e2        = (_id_)|0xeee2;                \
118
    (_regs_)->e3        = (_id_)|0xeee3;                \
119
    (_regs_)->e4        = (_id_)|0xeee4;                \
120
    (_regs_)->e5        = (_id_)|0xeee5;                \
121
    (_regs_)->e6        = (_id_)|0xeee6;                \
122
    (_regs_)->e7        = (_id_)|0xeee7;                \
123
    (_regs_)->mcrl      = 0;                            \
124
    (_regs_)->mcrh      = 0;                            \
125
    (_regs_)->mdrq      = 0;                            \
126
    (_regs_)->mcvf      = 0;                            \
127
CYG_MACRO_END
128
 
129
//--------------------------------------------------------------------------
130
// The following macros copy the extra AM33 registers between a
131
// HAL_SavedRegisters structure and a GDB register dump.
132
// The CYGMON version should handle the SSP and USP and MDRQ registers.
133
 
134
#ifdef CYGPKG_CYGMON
135
#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) am33_get_gdb_extra_registers( _regval_, _regs_ )
136
extern void am33_get_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs);
137
#else // CYGPKG_CYGMON
138
#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) \
139
CYG_MACRO_START                                         \
140
    (_regval_)[15] = (_regs_)->e0;                      \
141
    (_regval_)[16] = (_regs_)->e1;                      \
142
    (_regval_)[17] = (_regs_)->e2;                      \
143
    (_regval_)[18] = (_regs_)->e3;                      \
144
    (_regval_)[19] = (_regs_)->e4;                      \
145
    (_regval_)[20] = (_regs_)->e5;                      \
146
    (_regval_)[21] = (_regs_)->e6;                      \
147
    (_regval_)[22] = (_regs_)->e7;                      \
148
                                                        \
149
    (_regval_)[23] = (_regs_)->sp;                      \
150
    (_regval_)[24] = (_regs_)->sp;                      \
151
    (_regval_)[25] = (_regs_)->sp;                      \
152
                                                        \
153
    (_regval_)[26] = (_regs_)->mcrh;                    \
154
    (_regval_)[27] = (_regs_)->mcrl;                    \
155
    (_regval_)[28] = (_regs_)->mcvf;                    \
156
CYG_MACRO_END
157
#endif // CYGPKG_CYGMON
158
 
159
#ifdef CYGPKG_CYGMON
160
#define HAL_SET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) am33_set_gdb_extra_registers( _regs_, _regval_ )
161
extern void am33_set_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs);
162
#else // CYGPKG_CYGMON
163
#define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ) \
164
CYG_MACRO_START                                         \
165
    (_regs_)->e0 = (_regval_)[15];                      \
166
    (_regs_)->e1 = (_regval_)[16];                      \
167
    (_regs_)->e2 = (_regval_)[17];                      \
168
    (_regs_)->e3 = (_regval_)[18];                      \
169
    (_regs_)->e4 = (_regval_)[19];                      \
170
    (_regs_)->e5 = (_regval_)[20];                      \
171
    (_regs_)->e6 = (_regval_)[21];                      \
172
    (_regs_)->e7 = (_regval_)[22];                      \
173
                                                        \
174
    (_regs_)->sp = (_regval_)[23];                      \
175
    (_regs_)->sp = (_regval_)[24];                      \
176
    (_regs_)->sp = (_regval_)[25];                      \
177
                                                        \
178
    (_regs_)->mcrh = (_regval_)[26];                    \
179
    (_regs_)->mcrl = (_regval_)[27];                    \
180
    (_regs_)->mcvf = (_regval_)[28];                    \
181
CYG_MACRO_END
182
#endif // CYGPKG_CYGMON
183
 
184
//--------------------------------------------------------------------------
185
#endif // CYGONCE_HAL_VAR_ARCH_H
186
// End of var_arch.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.