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#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
##      variant.inc
##
##      AM33 assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   nickg
## Contributors:        nickg, dmoseley
## Date:        1999-04-06
## Purpose:     AM33 definitions.
## Description: This file contains various definitions and macros that are
##              useful for writing assembly code for the AM33 CPU variant.
## Usage:
##              #include 
##              ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
 
        .am33           # Enable AM33 instruction set
 
#include 
 
#include CYGHWR_MEMORY_LAYOUT_H
 
#------------------------------------------------------------------------------
# Register definitions
 
#define NMICR   0xD4000000      // NMI control register
#define DCR     0xC0000030      // Debug control register
#define ISR     0xC0000034      // Interrupt control register
#define TBR     0xC0000024      // Trap Base Register
#define CHCTR   0xC0000070      // Cache Control Register
 
#define DCR_DE  0x0001          // DE bit in DCR
 
##-----------------------------------------------------------------------------
## Register addresses and initialization values
 
#define SDRAMCONFIG             0xDA000000
 
#define INIT_SDRAMCONFIG        0x0000002f
 
#define SC0ICR                  0xD4002004
#define SC1ICR                  0xD4002014
#define SC2ICR                  0xD4002024
#define TM0MD                   0xD4003000
#define TM1MD                   0xD4003001
#define TM2MD                   0xD4003002
#define TM3MD                   0xD4003003
#define TM4MD                   0xD4003080
#define TM5MD                   0xD4003082
#define TM6MD                   0xD4003084
#define TM7MD                   0xD4003086
#define TM8MD                   0xD4003088
#define TM9MD                   0xD400308A
#define TM10MD                  0xD400308C
#define TM11MD                  0xD400308E
#define DM0CTR                  0xD2000000
#define DM1CTR                  0xD2000100
#define DM2CTR                  0xD2000200
#define DM3CTR                  0xD2000300
#define WDCTR                   0xC0001002
#define RTCRB                   0xD860000B
 
#------------------------------------------------------------------------------
# AM33 specific CPU initialization:
 
        # Initialize CPU
        .macro  hal_cpu_init
        # Set up the PSW
#if CYGHWR_HAL_MN10300_AM33_REVISION == 2
        mov     0x00100700,d0           # Enable the FPU
#else
        mov     0x00000700,d0
#endif
        mov     d0,epsw
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Don't change TBR for RAM startup if RAM base is not aligned for TBR.
// In that case, the only option is to rely on ROM startup TBR and patch
// into vectors through the hal_vsr_table.
//
#if !(defined(CYG_HAL_STARTUP_RAM) && (CYGMEM_REGION_ram & 0xffffff))
        mov     reset_vector,a0         # set TBR to vector table
        mov     a0,(TBR)
#endif
#endif
 
        # stop as many internal interrupt sources as possible
        mov     0,d0
        movhu   d0,(SC0ICR)
        movhu   d0,(SC1ICR)
        movhu   d0,(SC2ICR)
        movbu   d0,(TM0MD)
        movbu   d0,(TM1MD)
        movbu   d0,(TM2MD)
        movbu   d0,(TM3MD)
        movbu   d0,(TM4MD)
        movbu   d0,(TM5MD)
        movhu   d0,(TM6MD)
        movbu   d0,(TM7MD)
        movbu   d0,(TM8MD)
        movbu   d0,(TM9MD)
        movbu   d0,(TM10MD)
        movbu   d0,(TM11MD)
        movhu   d0,(WDCTR)
 
        movbu   (RTCRB),d0
        and     0x8F,d0
        movbu   d0,(RTCRB)
 
        mov     0x80000000,d0
        mov     d0,(DM0CTR)
        mov     d0,(DM1CTR)
        mov     d0,(DM2CTR)
        mov     d0,(DM3CTR)
 
        # disable all interrupts
        mov     _mn10300_interrupt_control,a0
        mov     _mn10300_interrupt_control+(41*4),a1
        mov     0x0010,d0
1:      movhu   d0,(a0)
        add     4,a0
        cmp     a0,a1
        bcc     1b
        .endm
 
#define CYGPKG_HAL_MN10300_CPU_INIT_DEFINED
 
#------------------------------------------------------------------------------
# CPU state save and restore macros
 
        .macro  hal_cpu_save_all
        movm    [all],(sp)                              # push all registers
        .endm
 
        .macro  hal_cpu_load_all
        movm    (sp),[all]                              # pop regs
        .endm
 
        .macro  hal_cpu_get_psw reg
        mov     epsw,\reg
        .endm
 
        .macro  hal_cpu_set_psw reg
        mov     \reg,epsw
        .endm
 
# Location of PC in saved context (HAL_SavedRegisters)
#define SAVED_CONTEXT_PC_OFFSET          104
 
#-----------------------------------------------------------------------------
# Clear the NMID bit in the epsw to allow NMIs to be delivered again.
 
        .macro  hal_cpu_clear_nmid
        and     0xFFFDFFFF,epsw                 # clear NMID bit
        .endm
 
 
#------------------------------------------------------------------------------
# MEMC macros.
 
#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
 
        .macro  hal_memc_init
        mov     INIT_SDRAMCONFIG,d0
        mov     d0,(SDRAMCONFIG)
        .endm
 
#define CYGPKG_HAL_MN10300_MEMC_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Cache macros.
 
#ifndef CYGPKG_HAL_MN10300_CACHE_DEFINED
 
        .macro  hal_cache_init
 
#if defined(CYG_HAL_STARTUP_ROM)
    # Note that the hardware seems to come up with the
    # caches containing random data. Hence they must be
    # invalidated before being enabled.
    # However, we only do this if we are in ROM. If we are
    # in RAM, then we leave the caches in the state chosen
    # by the ROM monitor. If we enable them when the monitor
    # is not expecting it, we can end up breaking things if the
    # monitor is not doing cache flushes.
        mov     CHCTR,a0
        mov     0x0030,d0
        mov     d0,(a0)                         # Invalidate the ICACHE and DCACHE
        mov     0x0003,d0
        mov     d0,(a0)                         # Enable both caches
#else
        nop
#endif
        .endm
 
#define CYGPKG_HAL_MN10300_CACHE_DEFINED
 
#endif
 
##-----------------------------------------------------------------------------
# Default interrupt decoding macros.
 
#ifndef CYGPKG_HAL_MN10300_INTC_DEFINED
 
 
 
        # initialize all interrupts to disabled
        .macro  hal_intc_init
        .endm
 
#define CYGPKG_HAL_MN10300_INTC_DEFINED
 
#endif
 
#ifndef CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
#define CYG_ISR_TABLE_SIZE      10
 
        .macro  hal_intc_decode dreg,areg,dreg1
        mov     _mn10300_interrupt_control,\areg
        movhu   (0x100,\areg),\dreg1            # dreg1 = IAGR
        mov     (0,a2),\dreg                    # dreg = vector priority
        mov     \dreg1,(0,a2)                   # store real vector in saved state
        asl     2,\dreg                         # dreg = byte index of isr
        add     12,\dreg                        # skip NMI vectors
        .endm
 
#else
 
#define CYG_ISR_TABLE_SIZE       57
 
        # decode the interrupt
        .macro  hal_intc_decode dreg,areg,dreg1
        mov     _mn10300_interrupt_control,\areg
        movhu   (0x100,\areg),\dreg             # dreg = IAGR
        mov     \dreg,(0,a2)                    # store real vector in saved state
        add     12,\dreg                        # skip NMI vectors
        .endm
 
#endif
 
#define CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED
 
#endif
 
 
#------------------------------------------------------------------------------
# Diagnostics macros.
 
#ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED
 
        .macro  hal_diag_init
        .endm
 
        .macro  hal_diag_excpt_start
        .endm
 
        .macro  hal_diag_intr_start
        .endm
 
        .macro  hal_diag_restore
        .endm
 
        .macro  hal_diag_led val
        movm    [d2,a2],(sp)
        mov     \val,d2
        movm    (sp),[d2,a2]
        .endm
 
 
#define CYGPKG_HAL_MN10300_DIAG_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
 
#ifndef CYGPKG_HAL_MN10300_MON_DEFINED
 
        .macro  hal_mon_init
        hal_mon_init_vectors
        hal_mon_init_vsr
        .endm
 
#if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
        .macro  hal_mon_init_vectors
        # direct external interrupts
        mov     _mn10300_interrupt_vectors,a0
        mov     __hardware_vector_0,d0
        movhu   d0,(0,a0)
        mov     __hardware_vector_1,d0
        movhu   d0,(4,a0)
        mov     __hardware_vector_2,d0
        movhu   d0,(8,a0)
        mov     __hardware_vector_3,d0
        movhu   d0,(12,a0)
        mov     __hardware_vector_4,d0
        movhu   d0,(16,a0)
        mov     __hardware_vector_5,d0
        movhu   d0,(20,a0)
        mov     __hardware_vector_6,d0
        movhu   d0,(24,a0)
        .endm
#else
        .macro  hal_mon_init_vectors
        .endm
#endif
 
        .extern nmi_vsr_trampoline
        .extern nmi_sysef_trampoline
 
        # init vsr table in SRAM where the ROM
        # vectors the interrupts.
 
#if defined(CYG_HAL_STARTUP_ROM)
        .macro  hal_mon_init_vsr
        mov     _hal_vsr_table,a0
        mov     __default_interrupt_vsr,d0
        mov     d0,(0,a0)
        mov     d0,(4,a0)
        mov     d0,(8,a0)
        mov     d0,(12,a0)
        mov     d0,(16,a0)
        mov     d0,(20,a0)
        mov     d0,(24,a0)
        mov     nmi_vsr_trampoline,d0
        mov     d0,(28,a0)
        mov     __default_trap_vsr,d0
        mov     d0,(32,a0)
        mov     nmi_sysef_trampoline,d0
        mov     d0,(44,a0)
        mov     __default_nmi_vsr,d0
        mov     d0,(36,a0)
        mov     d0,(40,a0)
        mov     d0,(48,a0)
        mov     d0,(52,a0)
        mov     d0,(56,a0)
        mov     d0,(60,a0)
        mov     d0,(64,a0)
        mov     d0,(68,a0)
        mov     d0,(72,a0)
        mov     d0,(76,a0)
        mov     d0,(80,a0)
        mov     d0,(84,a0)
        mov     d0,(88,a0)
        mov     d0,(92,a0)
        mov     d0,(96,a0)
        mov     d0,(100,a0)
        mov     d0,(104,a0)
        mov     d0,(108,a0)
        .endm
#elif defined(CYG_HAL_STARTUP_RAM)
        .macro  hal_mon_init_vsr
        mov     _hal_vsr_table,a0
        mov     __default_interrupt_vsr,d0
        mov     d0,(0,a0)
        mov     d0,(4,a0)
        mov     d0,(8,a0)
        mov     d0,(12,a0)
        mov     d0,(16,a0)
        mov     d0,(20,a0)
        mov     d0,(24,a0)
#if !(defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs))
        mov     nmi_vsr_trampoline,d0
        mov     d0,(28,a0)
        mov     nmi_sysef_trampoline,d0
        mov     d0,(44,a0)
#endif
        mov     __default_trap_vsr,d0
        mov     d0,(32,a0)
        mov     __default_nmi_vsr,d0
        mov     d0,(36,a0)
        mov     d0,(40,a0)
        mov     d0,(48,a0)
        mov     d0,(52,a0)
        mov     d0,(56,a0)
        mov     d0,(60,a0)
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        mov     d0,(64,a0)      # breakpoint VSR only if stubs included
#endif
        mov     d0,(68,a0)
        mov     d0,(72,a0)
        mov     d0,(76,a0)
        mov     d0,(80,a0)
        mov     d0,(84,a0)
        mov     d0,(88,a0)
        mov     d0,(92,a0)
        mov     d0,(96,a0)
        mov     d0,(100,a0)
        mov     d0,(104,a0)
        mov     d0,(108,a0)
        .endm
#else
        .macro  hal_mon_init_vsr
        .endif
#endif
 
#define CYGPKG_HAL_MN10300_MON_DEFINED
 
#define CYG_HAL_MN10300_VSR_TABLE_DEFINED
 
#endif
 
 
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [am33/] [v2_0/] [include/] [variant.inc] - Blame information for rev 174

Line No.	Rev	Author	Line
1	27	unneback	`#ifndef CYGONCE_HAL_VARIANT_INC`
2			`#define CYGONCE_HAL_VARIANT_INC`
3			`##=============================================================================`
4			`##`
5			`## variant.inc`
6			`##`
7			`## AM33 assembler header file`
8			`##`
9			`##=============================================================================`
10			`#####ECOSGPLCOPYRIGHTBEGIN####`
11			`## -------------------------------------------`
12			`## This file is part of eCos, the Embedded Configurable Operating System.`
13			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
14			`##`
15			`## eCos is free software; you can redistribute it and/or modify it under`
16			`## the terms of the GNU General Public License as published by the Free`
17			`## Software Foundation; either version 2 or (at your option) any later version.`
18			`##`
19			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
20			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
21			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
22			`## for more details.`
23			`##`
24			`## You should have received a copy of the GNU General Public License along`
25			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
26			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
27			`##`
28			`## As a special exception, if other files instantiate templates or use macros`
29			`## or inline functions from this file, or you compile this file and link it`
30			`## with other works to produce a work based on this file, this file does not`
31			`## by itself cause the resulting work to be covered by the GNU General Public`
32			`## License. However the source code for this file must still be made available`
33			`## in accordance with section (3) of the GNU General Public License.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based on`
36			`## this file might be covered by the GNU General Public License.`
37			`##`
38			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
39			`## at http://sources.redhat.com/ecos/ecos-license/`
40			`## -------------------------------------------`
41			`#####ECOSGPLCOPYRIGHTEND####`
42			`##=============================================================================`
43			`#######DESCRIPTIONBEGIN####`
44			`##`
45			`## Author(s): nickg`
46			`## Contributors: nickg, dmoseley`
47			`## Date: 1999-04-06`
48			`## Purpose: AM33 definitions.`
49			`## Description: This file contains various definitions and macros that are`
50			`## useful for writing assembly code for the AM33 CPU variant.`
51			`## Usage:`
52			`## #include`
53			`## ...`
54			`##`
55			`##`
56			`######DESCRIPTIONEND####`
57			`##`
58			`##=============================================================================`
59
60			`#include`
61
62			`.am33 # Enable AM33 instruction set`
63
64			`#include`
65
66			`#include CYGHWR_MEMORY_LAYOUT_H`
67
68			`#------------------------------------------------------------------------------`
69			`# Register definitions`
70
71			`#define NMICR 0xD4000000 // NMI control register`
72			`#define DCR 0xC0000030 // Debug control register`
73			`#define ISR 0xC0000034 // Interrupt control register`
74			`#define TBR 0xC0000024 // Trap Base Register`
75			`#define CHCTR 0xC0000070 // Cache Control Register`
76
77			`#define DCR_DE 0x0001 // DE bit in DCR`
78
79			`##-----------------------------------------------------------------------------`
80			`## Register addresses and initialization values`
81
82			`#define SDRAMCONFIG 0xDA000000`
83
84			`#define INIT_SDRAMCONFIG 0x0000002f`
85
86			`#define SC0ICR 0xD4002004`
87			`#define SC1ICR 0xD4002014`
88			`#define SC2ICR 0xD4002024`
89			`#define TM0MD 0xD4003000`
90			`#define TM1MD 0xD4003001`
91			`#define TM2MD 0xD4003002`
92			`#define TM3MD 0xD4003003`
93			`#define TM4MD 0xD4003080`
94			`#define TM5MD 0xD4003082`
95			`#define TM6MD 0xD4003084`
96			`#define TM7MD 0xD4003086`
97			`#define TM8MD 0xD4003088`
98			`#define TM9MD 0xD400308A`
99			`#define TM10MD 0xD400308C`
100			`#define TM11MD 0xD400308E`
101			`#define DM0CTR 0xD2000000`
102			`#define DM1CTR 0xD2000100`
103			`#define DM2CTR 0xD2000200`
104			`#define DM3CTR 0xD2000300`
105			`#define WDCTR 0xC0001002`
106			`#define RTCRB 0xD860000B`
107
108			`#------------------------------------------------------------------------------`
109			`# AM33 specific CPU initialization:`
110
111			`# Initialize CPU`
112			`.macro hal_cpu_init`
113			`# Set up the PSW`
114			`#if CYGHWR_HAL_MN10300_AM33_REVISION == 2`
115			`mov 0x00100700,d0 # Enable the FPU`
116			`#else`
117			`mov 0x00000700,d0`
118			`#endif`
119			`mov d0,epsw`
120			`#ifndef CYGSEM_HAL_USE_ROM_MONITOR`
121			`// Don't change TBR for RAM startup if RAM base is not aligned for TBR.`
122			`// In that case, the only option is to rely on ROM startup TBR and patch`
123			`// into vectors through the hal_vsr_table.`
124			`//`
125			`#if !(defined(CYG_HAL_STARTUP_RAM) && (CYGMEM_REGION_ram & 0xffffff))`
126			`mov reset_vector,a0 # set TBR to vector table`
127			`mov a0,(TBR)`
128			`#endif`
129			`#endif`
130
131			`# stop as many internal interrupt sources as possible`
132			`mov 0,d0`
133			`movhu d0,(SC0ICR)`
134			`movhu d0,(SC1ICR)`
135			`movhu d0,(SC2ICR)`
136			`movbu d0,(TM0MD)`
137			`movbu d0,(TM1MD)`
138			`movbu d0,(TM2MD)`
139			`movbu d0,(TM3MD)`
140			`movbu d0,(TM4MD)`
141			`movbu d0,(TM5MD)`
142			`movhu d0,(TM6MD)`
143			`movbu d0,(TM7MD)`
144			`movbu d0,(TM8MD)`
145			`movbu d0,(TM9MD)`
146			`movbu d0,(TM10MD)`
147			`movbu d0,(TM11MD)`
148			`movhu d0,(WDCTR)`
149
150			`movbu (RTCRB),d0`
151			`and 0x8F,d0`
152			`movbu d0,(RTCRB)`
153
154			`mov 0x80000000,d0`
155			`mov d0,(DM0CTR)`
156			`mov d0,(DM1CTR)`
157			`mov d0,(DM2CTR)`
158			`mov d0,(DM3CTR)`
159
160			`# disable all interrupts`
161			`mov _mn10300_interrupt_control,a0`
162			`mov _mn10300_interrupt_control+(41*4),a1`
163			`mov 0x0010,d0`
164			`1: movhu d0,(a0)`
165			`add 4,a0`
166			`cmp a0,a1`
167			`bcc 1b`
168			`.endm`
169
170			`#define CYGPKG_HAL_MN10300_CPU_INIT_DEFINED`
171
172			`#------------------------------------------------------------------------------`
173			`# CPU state save and restore macros`
174
175			`.macro hal_cpu_save_all`
176			`movm [all],(sp) # push all registers`
177			`.endm`
178
179			`.macro hal_cpu_load_all`
180			`movm (sp),[all] # pop regs`
181			`.endm`
182
183			`.macro hal_cpu_get_psw reg`
184			`mov epsw,\reg`
185			`.endm`
186
187			`.macro hal_cpu_set_psw reg`
188			`mov \reg,epsw`
189			`.endm`
190
191			`# Location of PC in saved context (HAL_SavedRegisters)`
192			`#define SAVED_CONTEXT_PC_OFFSET 104`
193
194			`#-----------------------------------------------------------------------------`
195			`# Clear the NMID bit in the epsw to allow NMIs to be delivered again.`
196
197			`.macro hal_cpu_clear_nmid`
198			`and 0xFFFDFFFF,epsw # clear NMID bit`
199			`.endm`
200
201
202			`#------------------------------------------------------------------------------`
203			`# MEMC macros.`
204
205			`#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED`
206
207			`.macro hal_memc_init`
208			`mov INIT_SDRAMCONFIG,d0`
209			`mov d0,(SDRAMCONFIG)`
210			`.endm`
211
212			`#define CYGPKG_HAL_MN10300_MEMC_DEFINED`
213
214			`#endif`
215
216			`#------------------------------------------------------------------------------`
217			`# Cache macros.`
218
219			`#ifndef CYGPKG_HAL_MN10300_CACHE_DEFINED`
220
221			`.macro hal_cache_init`
222
223			`#if defined(CYG_HAL_STARTUP_ROM)`
224			`# Note that the hardware seems to come up with the`
225			`# caches containing random data. Hence they must be`
226			`# invalidated before being enabled.`
227			`# However, we only do this if we are in ROM. If we are`
228			`# in RAM, then we leave the caches in the state chosen`
229			`# by the ROM monitor. If we enable them when the monitor`
230			`# is not expecting it, we can end up breaking things if the`
231			`# monitor is not doing cache flushes.`
232			`mov CHCTR,a0`
233			`mov 0x0030,d0`
234			`mov d0,(a0) # Invalidate the ICACHE and DCACHE`
235			`mov 0x0003,d0`
236			`mov d0,(a0) # Enable both caches`
237			`#else`
238			`nop`
239			`#endif`
240			`.endm`
241
242			`#define CYGPKG_HAL_MN10300_CACHE_DEFINED`
243
244			`#endif`
245
246			`##-----------------------------------------------------------------------------`
247			`# Default interrupt decoding macros.`
248
249			`#ifndef CYGPKG_HAL_MN10300_INTC_DEFINED`
250
251
252
253			`# initialize all interrupts to disabled`
254			`.macro hal_intc_init`
255			`.endm`
256
257			`#define CYGPKG_HAL_MN10300_INTC_DEFINED`
258
259			`#endif`
260
261			`#ifndef CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED`
262
263			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN`
264
265			`#define CYG_ISR_TABLE_SIZE 10`
266
267			`.macro hal_intc_decode dreg,areg,dreg1`
268			`mov _mn10300_interrupt_control,\areg`
269			`movhu (0x100,\areg),\dreg1 # dreg1 = IAGR`
270			`mov (0,a2),\dreg # dreg = vector priority`
271			`mov \dreg1,(0,a2) # store real vector in saved state`
272			`asl 2,\dreg # dreg = byte index of isr`
273			`add 12,\dreg # skip NMI vectors`
274			`.endm`
275
276			`#else`
277
278			`#define CYG_ISR_TABLE_SIZE 57`
279
280			`# decode the interrupt`
281			`.macro hal_intc_decode dreg,areg,dreg1`
282			`mov _mn10300_interrupt_control,\areg`
283			`movhu (0x100,\areg),\dreg # dreg = IAGR`
284			`mov \dreg,(0,a2) # store real vector in saved state`
285			`add 12,\dreg # skip NMI vectors`
286			`.endm`
287
288			`#endif`
289
290			`#define CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED`
291
292			`#endif`
293
294
295			`#------------------------------------------------------------------------------`
296			`# Diagnostics macros.`
297
298			`#ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED`
299
300			`.macro hal_diag_init`
301			`.endm`
302
303			`.macro hal_diag_excpt_start`
304			`.endm`
305
306			`.macro hal_diag_intr_start`
307			`.endm`
308
309			`.macro hal_diag_restore`
310			`.endm`
311
312			`.macro hal_diag_led val`
313			`movm [d2,a2],(sp)`
314			`mov \val,d2`
315			`movm (sp),[d2,a2]`
316			`.endm`
317
318
319			`#define CYGPKG_HAL_MN10300_DIAG_DEFINED`
320
321			`#endif`
322
323			`#------------------------------------------------------------------------------`
324			`# Monitor initialization.`
325
326			`#ifndef CYGPKG_HAL_MN10300_MON_DEFINED`
327
328			`.macro hal_mon_init`
329			`hal_mon_init_vectors`
330			`hal_mon_init_vsr`
331			`.endm`
332
333			`#if defined(CYG_HAL_STARTUP_ROM) \|\| !defined(CYGSEM_HAL_USE_ROM_MONITOR)`
334			`.macro hal_mon_init_vectors`
335			`# direct external interrupts`
336			`mov _mn10300_interrupt_vectors,a0`
337			`mov __hardware_vector_0,d0`
338			`movhu d0,(0,a0)`
339			`mov __hardware_vector_1,d0`
340			`movhu d0,(4,a0)`
341			`mov __hardware_vector_2,d0`
342			`movhu d0,(8,a0)`
343			`mov __hardware_vector_3,d0`
344			`movhu d0,(12,a0)`
345			`mov __hardware_vector_4,d0`
346			`movhu d0,(16,a0)`
347			`mov __hardware_vector_5,d0`
348			`movhu d0,(20,a0)`
349			`mov __hardware_vector_6,d0`
350			`movhu d0,(24,a0)`
351			`.endm`
352			`#else`
353			`.macro hal_mon_init_vectors`
354			`.endm`
355			`#endif`
356
357			`.extern nmi_vsr_trampoline`
358			`.extern nmi_sysef_trampoline`
359
360			`# init vsr table in SRAM where the ROM`
361			`# vectors the interrupts.`
362
363			`#if defined(CYG_HAL_STARTUP_ROM)`
364			`.macro hal_mon_init_vsr`
365			`mov _hal_vsr_table,a0`
366			`mov __default_interrupt_vsr,d0`
367			`mov d0,(0,a0)`
368			`mov d0,(4,a0)`
369			`mov d0,(8,a0)`
370			`mov d0,(12,a0)`
371			`mov d0,(16,a0)`
372			`mov d0,(20,a0)`
373			`mov d0,(24,a0)`
374			`mov nmi_vsr_trampoline,d0`
375			`mov d0,(28,a0)`
376			`mov __default_trap_vsr,d0`
377			`mov d0,(32,a0)`
378			`mov nmi_sysef_trampoline,d0`
379			`mov d0,(44,a0)`
380			`mov __default_nmi_vsr,d0`
381			`mov d0,(36,a0)`
382			`mov d0,(40,a0)`
383			`mov d0,(48,a0)`
384			`mov d0,(52,a0)`
385			`mov d0,(56,a0)`
386			`mov d0,(60,a0)`
387			`mov d0,(64,a0)`
388			`mov d0,(68,a0)`
389			`mov d0,(72,a0)`
390			`mov d0,(76,a0)`
391			`mov d0,(80,a0)`
392			`mov d0,(84,a0)`
393			`mov d0,(88,a0)`
394			`mov d0,(92,a0)`
395			`mov d0,(96,a0)`
396			`mov d0,(100,a0)`
397			`mov d0,(104,a0)`
398			`mov d0,(108,a0)`
399			`.endm`
400			`#elif defined(CYG_HAL_STARTUP_RAM)`
401			`.macro hal_mon_init_vsr`
402			`mov _hal_vsr_table,a0`
403			`mov __default_interrupt_vsr,d0`
404			`mov d0,(0,a0)`
405			`mov d0,(4,a0)`
406			`mov d0,(8,a0)`
407			`mov d0,(12,a0)`
408			`mov d0,(16,a0)`
409			`mov d0,(20,a0)`
410			`mov d0,(24,a0)`
411			`#if !(defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs))`
412			`mov nmi_vsr_trampoline,d0`
413			`mov d0,(28,a0)`
414			`mov nmi_sysef_trampoline,d0`
415			`mov d0,(44,a0)`
416			`#endif`
417			`mov __default_trap_vsr,d0`
418			`mov d0,(32,a0)`
419			`mov __default_nmi_vsr,d0`
420			`mov d0,(36,a0)`
421			`mov d0,(40,a0)`
422			`mov d0,(48,a0)`
423			`mov d0,(52,a0)`
424			`mov d0,(56,a0)`
425			`mov d0,(60,a0)`
426			`#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS`
427			`mov d0,(64,a0) # breakpoint VSR only if stubs included`
428			`#endif`
429			`mov d0,(68,a0)`
430			`mov d0,(72,a0)`
431			`mov d0,(76,a0)`
432			`mov d0,(80,a0)`
433			`mov d0,(84,a0)`
434			`mov d0,(88,a0)`
435			`mov d0,(92,a0)`
436			`mov d0,(96,a0)`
437			`mov d0,(100,a0)`
438			`mov d0,(104,a0)`
439			`mov d0,(108,a0)`
440			`.endm`
441			`#else`
442			`.macro hal_mon_init_vsr`
443			`.endif`
444			`#endif`
445
446			`#define CYGPKG_HAL_MN10300_MON_DEFINED`
447
448			`#define CYG_HAL_MN10300_VSR_TABLE_DEFINED`
449
450			`#endif`
451
452
453
454			`#------------------------------------------------------------------------------`
455			`#endif // ifndef CYGONCE_HAL_VARIANT_INC`
456			`# end of variant.inc`