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##=============================================================================
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##
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##      variant.S
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##
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##      MN10300 AM33 variant code
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s):   nickg
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## Contributors:        nickg
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## Date:        1997-10-16
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## Purpose:     MN10300 AM33 variant code
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## Description: This file contains variant specific assembly code for the AM33.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include 
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#include 
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##-----------------------------------------------------------------------------
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## NMI trampoline VSRs. All NMI interrupts are routed here initially, where we
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## decode the NMICR and ISR register contents and vector to the
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## correct VSR later in the table.
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        .text
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        .extern hal_lsbit_table
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        .globl nmi_vsr_trampoline
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nmi_vsr_trampoline:
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        movhu   (NMICR),d0              # D0 = NMI control register
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        and     0x7,d0                  # LS 3 bits only
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        mov     3,d1                    # search from bit 3
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        bsch    d0,d1                   # get ms bit in d1
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        bcs     2f                      # jump if no bits there
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        add     9,d1                    # D1 = offset into VSR table
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        jmp     3f                      # go to rest of code
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        .globl nmi_sysef_trampoline
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nmi_sysef_trampoline:
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        movhu   (ISR),d0                # D0 = Interrupt Status Register
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        mov     d0,d1                   # D1 = copy of D0
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        add     -1,d1                   # D1 = D0-1
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        not     d1                      # D1 = ~(D0-1) = -D0
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        and     d1,d0                   # D0 = D0 & -D0 = ls bit only
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        mov     16,d1                   # D1 = start of search bit
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        bsch    d0,d1                   # search for 1 bit in d0
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        bcs     2f                      # jump if failed
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        add     12,d1                   # d1 = offset in VSR table
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3:
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        asl     2,d1                    # D1 = word offset in vsr table
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        mov     _hal_vsr_table,a0       # A0 = VSR table base
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        add     d1,a0                   # A0 = address of table entry we want
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        mov     (a0),a0                 # A0 = VSR to call
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        jmp     (a0)                    # Call it
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2:
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        # no bits set in ISR or NMICR when we expected them.
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        # This should never happen, but if it does, use an otherwise
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        # unused VSR table entry to indicate this.
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        mov     27,d1                   # use last VSR table entry.
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        jmp     3b
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##-----------------------------------------------------------------------------
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#define HAL_CHCTR               0xC0000070
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#define HAL_DCACHE_PURGE_WAY0   0xC8400000
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#define HAL_CHCTR_DCEN          0x0002
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#define HAL_CHCTR_DCBUSY        0x0008
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        .text
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        .globl  _cyg_hal_dcache_store
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_cyg_hal_dcache_store:
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        movm    [d2,d3],(sp)
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        mov     HAL_CHCTR,a0                    # A0 = control reg
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        mov     HAL_DCACHE_PURGE_WAY0,a1        # A1 = purge base address
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        # Disable DCACHE if it is enabled
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        movhu   (a0),d2                         # D2 = old value of control reg
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        btst    HAL_CHCTR_DCEN,d2               # check for cache enabled
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        beq     1f                              # if not, skip disable
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        mov     d2,d3                           # make a copy of CHCTR
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        and     ~HAL_CHCTR_DCEN,d3              # clear DCEN bit
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        movhu   d3,(a0)                         # store in reg
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2:      movhu   (a0),d3                         # get CHCTR
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        btst    HAL_CHCTR_DCBUSY,d3             # test DCBUSY bit
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        bne     2b                              # loop while set
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1:
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        # The cache is now disabled
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        and     0x000003f0,d0                   # isolate index bits of base addr
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        add     d0,a1                           # offset a1 to base address
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        add     63,d1                           # adjust size to whole multiple of
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        and     0xFFFFFFC0,d1                   # set size.
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3:
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        mov     (0x0000,a1),d0                  # purge way 0
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        mov     (0x1000,a1),d0                  # purge way 1
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        mov     (0x2000,a1),d0                  # purge way 2
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        mov     (0x3000,a1),d0                  # purge way 3
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        add     16,a1                           # advance to next set
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        sub     64,d1                           # decrement count
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        bne     3b                              # loop while non zero
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        # Restore original cache state from saved CHCTR in D2
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        movhu   d2,(a0)
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        movm    (sp),[d2,d3]                    # restore work regs
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        rets
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##-----------------------------------------------------------------------------
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## end of variant.S
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