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#ifndef CYGONCE_HAL_HAL_ARCH_H
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#define CYGONCE_HAL_HAL_ARCH_H
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//==========================================================================
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//
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// hal_arch.h
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//
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// Architecture specific abstractions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, dmoseley
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// Date: 1999-02-18
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// Purpose: Define architecture abstractions
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// Usage: #include <cyg/hal/hal_arch.h>
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/var_arch.h>
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//--------------------------------------------------------------------------
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// Exception handling function.
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// This function is defined by the kernel according to this prototype. It is
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// invoked from the HAL to deal with any CPU exceptions that the HAL does
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// not want to deal with itself. It usually invokes the kernel's exception
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// delivery mechanism.
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externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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//--------------------------------------------------------------------------
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// Bit manipulation routines
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externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
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#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
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//--------------------------------------------------------------------------
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// Context Initialization
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// Initialize the context of a thread.
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// Arguments:
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// _sp_ name of variable containing current sp, will be written with new sp
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// _thread_ thread object address, passed as argument to entry point
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// _entry_ entry point address.
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// _id_ bit pattern used in initializing registers, for debugging.
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#ifndef HAL_THREAD_INIT_CONTEXT_EXTRA
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#define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_)
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#endif
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#define HAL_THREAD_INIT_CONTEXT( _sp_, _thread_, _entry_, _id_ ) \
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{ \
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register HAL_SavedRegisters *_regs_; \
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_regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)&~15) - \
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sizeof(HAL_SavedRegisters)*2); \
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HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_); \
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_regs_->d0 = (CYG_WORD)(_thread_); \
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_regs_->d1 = (_id_)|0xddd1; \
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_regs_->d2 = (_id_)|0xddd2; \
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_regs_->d3 = (_id_)|0xddd3; \
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_regs_->a0 = (_id_)|0xaaa0; \
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_regs_->a1 = (_id_)|0xaaa1; \
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_regs_->a2 = (_id_)|0xaaa2; \
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_regs_->a3 = (_id_)|0xaaa3; \
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_regs_->mdr = 0; \
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_regs_->lir = 0; \
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_regs_->lar = 0; \
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_regs_->psw = 0x0000F00; \
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_regs_->pc = (CYG_WORD)(_entry_); \
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_sp_ = (CYG_ADDRESS)_regs_; \
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}
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//--------------------------------------------------------------------------
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// Context switch macros.
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// The arguments are pointers to locations where the stack pointer
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// of the current thread is to be stored, and from where the sp of the
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// next thread is to be fetched.
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externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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externC void hal_thread_load_context( CYG_ADDRESS to )
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__attribute__ ((noreturn));
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#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
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(CYG_ADDRESS)_fspptr_);
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#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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//--------------------------------------------------------------------------
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// Execution reorder barrier.
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// When optimizing the compiler can reorder code. In multithreaded systems
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// where the order of actions is vital, this can sometimes cause problems.
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// This macro may be inserted into places where reordering should not happen.
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#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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//--------------------------------------------------------------------------
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// Breakpoint support
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// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
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// happen if executed.
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// HAL_BREAKINST is the value of the breakpoint instruction and
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// HAL_BREAKINST_SIZE is its size in bytes.
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// HAL_BREAKINST_TYPE is the type.
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#define HAL_BREAKPOINT(_label_) \
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asm volatile (" .globl _" #_label_ ";" \
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"_"#_label_":" \
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".byte 0xFF" \
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);
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#define HAL_BREAKINST 0xFF
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#define HAL_BREAKINST_SIZE 1
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#define HAL_BREAKINST_TYPE cyg_uint8
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//--------------------------------------------------------------------------
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// Thread register state manipulation for GDB support.
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// Translate a stack pointer as saved by the thread context macros above into
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// a pointer to a HAL_SavedRegisters structure.
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#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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(_regs_) = (HAL_SavedRegisters *)(_sp_)
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#ifndef HAL_GET_GDB_EXTRA_REGISTERS
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#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ )
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#endif
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#ifndef HAL_SET_GDB_EXTRA_REGISTERS
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#define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ )
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#endif
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// Copy a set of registers from a HAL_SavedRegisters structure into a
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// GDB ordered array.
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//
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// The CYGMON version should differ by also handling SP and PSW
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// since we will be using a different stack.
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#ifdef CYGPKG_CYGMON
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#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
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{ \
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CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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\
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_regval_[0] = (_regs_)->d0; \
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_regval_[1] = (_regs_)->d1; \
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_regval_[2] = (_regs_)->d2; \
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_regval_[3] = (_regs_)->d3; \
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_regval_[4] = (_regs_)->a0; \
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_regval_[5] = (_regs_)->a1; \
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_regval_[6] = (_regs_)->a2; \
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_regval_[7] = (_regs_)->a3; \
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\
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_regval_[8] = (_regs_)->sp; \
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_regval_[9] = (_regs_)->pc; \
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_regval_[10] = (_regs_)->mdr; \
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_regval_[11] = (_regs_)->psw; \
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\
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_regval_[12] = (_regs_)->lar; \
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_regval_[13] = (_regs_)->lir; \
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HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \
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}
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#else
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#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
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{ \
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CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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\
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_regval_[0] = (_regs_)->d0; \
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_regval_[1] = (_regs_)->d1; \
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_regval_[2] = (_regs_)->d2; \
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_regval_[3] = (_regs_)->d3; \
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_regval_[4] = (_regs_)->a0; \
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_regval_[5] = (_regs_)->a1; \
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_regval_[6] = (_regs_)->a2; \
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_regval_[7] = (_regs_)->a3; \
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\
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_regval_[8] = (_regs_)->sp = (CYG_ADDRWORD)(_regs_) + \
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sizeof(HAL_SavedRegisters); \
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_regval_[9] = (_regs_)->pc; \
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_regval_[10] = (_regs_)->mdr; \
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_regval_[11] = (_regs_)->psw; \
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\
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_regval_[12] = (_regs_)->lar; \
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_regval_[13] = (_regs_)->lir; \
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HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \
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}
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#endif
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// Copy a GDB ordered array into a HAL_SavedRegisters structure.
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//
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// The CYGMON version should differ by also handling SP and PSW
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// since we will be using a different stack.
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#ifdef CYGPKG_CYGMON
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#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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{ \
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CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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\
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(_regs_)->d0 = _regval_[0]; \
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(_regs_)->d1 = _regval_[1]; \
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(_regs_)->d2 = _regval_[2]; \
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(_regs_)->d3 = _regval_[3]; \
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(_regs_)->a0 = _regval_[4]; \
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(_regs_)->a1 = _regval_[5]; \
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(_regs_)->a2 = _regval_[6]; \
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(_regs_)->a3 = _regval_[7]; \
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\
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(_regs_)->sp = _regval_[8]; \
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(_regs_)->pc = _regval_[9]; \
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(_regs_)->mdr = _regval_[10]; \
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(_regs_)->psw = _regval_[11]; \
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\
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(_regs_)->lar = _regval_[12]; \
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(_regs_)->lir = _regval_[13]; \
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\
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HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \
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}
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#else
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#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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{ \
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| 260 |
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CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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\
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| 262 |
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(_regs_)->d0 = _regval_[0]; \
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(_regs_)->d1 = _regval_[1]; \
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(_regs_)->d2 = _regval_[2]; \
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| 265 |
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(_regs_)->d3 = _regval_[3]; \
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| 266 |
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(_regs_)->a0 = _regval_[4]; \
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| 267 |
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(_regs_)->a1 = _regval_[5]; \
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| 268 |
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(_regs_)->a2 = _regval_[6]; \
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| 269 |
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(_regs_)->a3 = _regval_[7]; \
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\
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| 271 |
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(_regs_)->pc = _regval_[9]; \
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(_regs_)->mdr = _regval_[10]; \
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| 273 |
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\
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| 274 |
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(_regs_)->lar = _regval_[12]; \
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| 275 |
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(_regs_)->lir = _regval_[13]; \
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\
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| 277 |
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/* We do not allow the SP or PSW to be set. Changing the SP will \
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* mess up the saved state. No PSW is saved on thread context \
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* switches, so there is nowhere to save it to. \
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*/ \
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\
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| 282 |
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HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \
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}
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#endif
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| 285 |
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| 286 |
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//-------------------------------------------------------------------------
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| 287 |
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// HAL setjmp
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| 288 |
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// Note: These definitions are repeated in context.S. If changes are required
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| 289 |
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// remember to update both sets.
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| 290 |
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| 291 |
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#define CYGARC_JMP_BUF_SP 0
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| 292 |
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#define CYGARC_JMP_BUF_D2 1
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| 293 |
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#define CYGARC_JMP_BUF_D3 2
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| 294 |
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#define CYGARC_JMP_BUF_A2 3
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| 295 |
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#define CYGARC_JMP_BUF_A3 4
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| 296 |
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#define CYGARC_JMP_BUF_LR 5
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| 297 |
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| 298 |
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#define CYGARC_JMP_BUF_SIZE 6
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| 299 |
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| 300 |
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typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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| 301 |
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| 302 |
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externC int hal_setjmp(hal_jmp_buf env);
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| 303 |
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externC void hal_longjmp(hal_jmp_buf env, int val);
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| 304 |
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| 305 |
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//-------------------------------------------------------------------------
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| 306 |
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// Idle thread code.
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| 307 |
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// This macro is called in the idle thread loop, and gives the HAL the
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| 308 |
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// chance to insert code. Typical idle thread behaviour might be to halt the
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| 309 |
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// processor.
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| 310 |
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| 311 |
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externC void hal_idle_thread_action(cyg_uint32 loop_count);
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| 312 |
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| 313 |
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#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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| 314 |
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| 315 |
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//-----------------------------------------------------------------------------
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| 316 |
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// Minimal and sensible stack sizes: the intention is that applications
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| 317 |
|
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// will use these to provide a stack size in the first instance prior to
|
| 318 |
|
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// proper analysis. Idle thread stack should be this big.
|
| 319 |
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|
|
| 320 |
|
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// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
|
| 321 |
|
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// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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| 322 |
|
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// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
|
| 323 |
|
|
|
| 324 |
|
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// We define quite large stack needs for SPARClite, for it requires 576
|
| 325 |
|
|
// bytes (144 words) to process an interrupt and thread-switch, and
|
| 326 |
|
|
// momentarily, but needed in case of recursive interrupts, it needs 208
|
| 327 |
|
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// words - if a sequence of saves to push out other regsets is interrupted.
|
| 328 |
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|
|
| 329 |
|
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// This is not a config option because it should not be adjusted except
|
| 330 |
|
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// under "enough rope" sort of disclaimers.
|
| 331 |
|
|
|
| 332 |
|
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// Worst case stack frame size: return link + 4 args + 4 pushed registers.
|
| 333 |
|
|
#define CYGNUM_HAL_STACK_FRAME_SIZE (40)
|
| 334 |
|
|
|
| 335 |
|
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// Stack needed for a context switch:
|
| 336 |
|
|
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (60)
|
| 337 |
|
|
|
| 338 |
|
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// Interrupt + call to ISR, interrupt_end() and the DSR
|
| 339 |
|
|
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (128)
|
| 340 |
|
|
|
| 341 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 342 |
|
|
|
| 343 |
|
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// An interrupt stack which is large enough for all possible interrupt
|
| 344 |
|
|
// conditions (and only used for that purpose) exists. "User" stacks
|
| 345 |
|
|
// can be much smaller
|
| 346 |
|
|
|
| 347 |
|
|
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
|
| 348 |
|
|
CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
|
| 349 |
|
|
CYGNUM_HAL_STACK_FRAME_SIZE*16)
|
| 350 |
|
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#define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048)
|
| 351 |
|
|
|
| 352 |
|
|
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 353 |
|
|
|
| 354 |
|
|
// No separate interrupt stack exists. Make sure all threads contain
|
| 355 |
|
|
// a stack sufficiently large.
|
| 356 |
|
|
|
| 357 |
|
|
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
|
| 358 |
|
|
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
|
| 359 |
|
|
|
| 360 |
|
|
#endif
|
| 361 |
|
|
|
| 362 |
|
|
//--------------------------------------------------------------------------
|
| 363 |
|
|
// Macros for switching context between two eCos instances (jump from
|
| 364 |
|
|
// code in ROM to code in RAM or vice versa).
|
| 365 |
|
|
#define CYGARC_HAL_SAVE_GP()
|
| 366 |
|
|
#define CYGARC_HAL_RESTORE_GP()
|
| 367 |
|
|
|
| 368 |
|
|
//--------------------------------------------------------------------------
|
| 369 |
|
|
#endif // CYGONCE_HAL_HAL_ARCH_H
|
| 370 |
|
|
// EOF hal_arch.h
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