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#ifndef CYGONCE_HAL_HAL_INTR_H
#define CYGONCE_HAL_HAL_INTR_H
//==========================================================================
//
//      hal_intr.h
//
//      HAL Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, jlarmour
// Date:         1999-02-18
// Purpose:      Define Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock.
// Usage:
//               #include <cyg/hal/hal_intr.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
 
#include <cyg/hal/var_intr.h>
 
//--------------------------------------------------------------------------
// Static data used by HAL
 
// ISR tables
externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
// VSR table
externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
 
// MN10300 interrupt control registers, mapped by linker script.
externC volatile cyg_uint16     mn10300_interrupt_control[];
 
//--------------------------------------------------------------------------
// Default ISR
// The #define is used to test whether this routine exists, and to allow
// us to call it.
 
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#define HAL_DEFAULT_ISR hal_default_isr
 
//--------------------------------------------------------------------------
// Interrupt state storage
 
typedef cyg_uint32 CYG_INTERRUPT_STATE;
 
//--------------------------------------------------------------------------
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
// Routine to execute DSRs using separate interrupt stack
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
    hal_interrupt_stack_call_pending_DSRs()
 
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
// use them to declare these extern however you want:
//       extern char HAL_INTERRUPT_STACK_BASE[];
//       extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt control macros
 
#define HAL_DISABLE_INTERRUPTS(_old_)   \
        asm volatile (                  \
            "mov        psw,%0;"        \
            "mov        0xF7FF,d0;"     \
            "and        %0,d0;"         \
            "mov        d0,psw;"        \
            "and        0x0800,%0;"     \
            : "=d"(_old_)               \
            :                           \
            : "d0"                      \
            );
 
#define HAL_ENABLE_INTERRUPTS()         \
        asm volatile (                  \
            "mov        psw,d0;"        \
            "or         0x0800,d0;"     \
            "mov        d0,psw;"        \
            :                           \
            :                           \
            : "d0"                      \
            );
 
#define HAL_RESTORE_INTERRUPTS(_old_)   \
        asm volatile (                  \
            "mov        psw,d1;"        \
            "and        0xF7FF,d1;"     \
            "or         %0,d1;"         \
            "mov        d1,psw;"        \
            :                           \
            : "d"(_old_)                \
            : "d1"                      \
            );
 
#define HAL_QUERY_INTERRUPTS(_old_)     \
        asm volatile (                  \
            "mov        psw,%0;"        \
            "and        0x0800,%0;"     \
            : "=d"(_old_)               \
            );
 
//--------------------------------------------------------------------------
// Translate a vector number into an ISR table index.
// If we have chained interrupts we have just a single ISR per priority
// level. On the MN103000 there are several interrupts per controller,
// so we have to decode to one of 100 vectors. On the MN103002 there is
// only one interrupt per controller, so we can have just one ISR per
// controller, except for the NMI vectors which occupy the first 3 slots.
 
#ifndef HAL_TRANSLATE_VECTOR
 
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
{                                                                          \
    if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR )                    \
        (_index_) = (_vector_);                                            \
    else                                                                   \
    {                                                                      \
        /* ICRs are 16 bit regs at 32 bit spacing */                       \
        cyg_ucount16 _ix_ = ((_vector_)>>2)<<1;                            \
                                                                           \
        /* read the appropriate interrupt control register */              \
        cyg_uint16 _icr_ = mn10300_interrupt_control[_ix_];                \
                                                                           \
        /* extract interrupt priority level */                             \
        _index_ = CYGNUM_HAL_INTERRUPT_RESERVED_3 + ((_icr_ >> 12) & 0x7); \
    }                                                                      \
}
 
#else
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
 
#endif
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
 
#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                                \
CYG_MACRO_START                                                                 \
    cyg_uint32 _index_;                                                         \
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                                 \
                                                                                \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR )       \
        (_state_) = 0;                                                          \
    else                                                                        \
        (_state_) = 1;                                                          \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )               \
CYG_MACRO_START                                                                 \
    cyg_uint32 _index_;                                                         \
    HAL_TRANSLATE_VECTOR(_vector_,_index_);                                     \
                                                                                \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR )       \
    {                                                                           \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_;                   \
        hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_;                     \
        hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_;                 \
    }                                                                           \
CYG_MACRO_END
 
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
CYG_MACRO_START                                                         \
    cyg_uint32 _index_;                                                 \
    HAL_TRANSLATE_VECTOR(_vector_,_index_);                             \
                                                                        \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ )         \
    {                                                                   \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
        hal_interrupt_data[_index_] = 0;                                \
        hal_interrupt_objects[_index_] = 0;                             \
    }                                                                   \
CYG_MACRO_END
 
#define HAL_VSR_GET( _vector_, _pvsr_ )                                 \
    *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
 
 
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )                       \
    if( _poldvsr_ != NULL )                                             \
        *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];            \
    hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;
 
 
//--------------------------------------------------------------------------
// Interrupt controller access
// Read interrupt control registers back after writing to them. This
// ensures that the written value is not sitting in the store buffers
// when interrupts are re-enabled.
#define HAL_INTERRUPT_MASK( _vector_ )                                  \
{                                                                       \
    /* ICRs are 16 bit regs at 32 bit spacing */                        \
    cyg_ucount16 _index_ = ((_vector_)>>2)<<1;                          \
                                                                        \
    /* read the appropriate interrupt control register */               \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];              \
                                                                        \
    /* clear interrupt enable bit for this vector */                    \
    _icr_ &= ~(0x0100<<((_vector_)&3));                                 \
                                                                        \
    /* restore the interrupt control register */                        \
    mn10300_interrupt_control[_index_] = _icr_;                         \
    _icr_ = mn10300_interrupt_control[_index_];                         \
}
 
#define HAL_INTERRUPT_UNMASK( _vector_ )                                \
{                                                                       \
    /* ICRs are 16 bit regs at 32 bit spacing */                        \
    cyg_ucount16 _index_ = (_vector_>>2)<<1;                            \
                                                                        \
    /* read the appropriate interrupt control register */               \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];              \
                                                                        \
    /* set interrupt enable bit for this vector */                      \
    _icr_ |= (0x0100<<(_vector_&3));                                    \
                                                                        \
    /* restore the interrupt control register */                        \
    mn10300_interrupt_control[_index_] = _icr_;                         \
    _icr_ = mn10300_interrupt_control[_index_];                         \
}
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )                   \
{                                                               \
    /* ICRs are 16 bit regs at 32 bit spacing */                \
    cyg_ucount16 _index_ = ((_vector_)>>2)<<1;                  \
                                                                \
    /* read the appropriate interrupt control register */       \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];      \
                                                                \
    /* clear interrupt request bit for this vector */           \
    _icr_ &= ~(0x0010<<((_vector_)&3));                         \
                                                                \
    /* set interrupt detect bit for this vector */              \
    _icr_ |= (0x0001<<((_vector_)&3));                          \
                                                                \
    /* restore the interrupt control register */                \
    mn10300_interrupt_control[_index_] = _icr_;                 \
    _icr_ = mn10300_interrupt_control[_index_];                 \
}
 
#if !defined(HAL_INTERRUPT_CONFIGURE)
 
#error HAL_INTERRUPT_CONFIGURE not defined by variant
 
#endif
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
{                                                               \
    /* ICRs are 16 bit regs at 32 bit spacing */                \
    cyg_ucount16 _index_ = (_vector_>>2)<<1;                    \
                                                                \
    /* read the appropriate interrupt control register */       \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];      \
                                                                \
    /* set interrupt level for this group of vectors */         \
    _icr_ &= 0x0FFF;                                            \
    _icr_ |= (_level_)<<12;                                     \
                                                                \
    /* restore the interrupt control register */                \
    mn10300_interrupt_control[_index_] = _icr_;                 \
    _icr_ = mn10300_interrupt_control[_index_];                 \
}
 
//--------------------------------------------------------------------------
// Clock control.
// This is almost all handled in the var_intr.h.
 
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
#endif
 
//--------------------------------------------------------------------------
// Memory region top
//
#if CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP
 
externC cyg_uint8 *hal_mn10300_mem_real_region_top( cyg_uint8 *_regionend_ );
 
# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \
    hal_mn10300_mem_real_region_top( _regionend_ )
#endif
 
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
// EOF hal_intr.h

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [arch/] [v2_0/] [include/] [hal_intr.h] - Blame information for rev 631

Line No.	Rev	Author	Line
1	27	unneback	`#ifndef CYGONCE_HAL_HAL_INTR_H`
2			`#define CYGONCE_HAL_HAL_INTR_H`
3			`//==========================================================================`
4			`//`
5			`// hal_intr.h`
6			`//`
7			`// HAL Interrupt and clock support`
8			`//`
9			`//==========================================================================`
10			`//####ECOSGPLCOPYRIGHTBEGIN####`
11			`// -------------------------------------------`
12			`// This file is part of eCos, the Embedded Configurable Operating System.`
13			`// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
14			`//`
15			`// eCos is free software; you can redistribute it and/or modify it under`
16			`// the terms of the GNU General Public License as published by the Free`
17			`// Software Foundation; either version 2 or (at your option) any later version.`
18			`//`
19			`// eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
20			`// WARRANTY; without even the implied warranty of MERCHANTABILITY or`
21			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
22			`// for more details.`
23			`//`
24			`// You should have received a copy of the GNU General Public License along`
25			`// with eCos; if not, write to the Free Software Foundation, Inc.,`
26			`// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
27			`//`
28			`// As a special exception, if other files instantiate templates or use macros`
29			`// or inline functions from this file, or you compile this file and link it`
30			`// with other works to produce a work based on this file, this file does not`
31			`// by itself cause the resulting work to be covered by the GNU General Public`
32			`// License. However the source code for this file must still be made available`
33			`// in accordance with section (3) of the GNU General Public License.`
34			`//`
35			`// This exception does not invalidate any other reasons why a work based on`
36			`// this file might be covered by the GNU General Public License.`
37			`//`
38			`// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
39			`// at http://sources.redhat.com/ecos/ecos-license/`
40			`// -------------------------------------------`
41			`//####ECOSGPLCOPYRIGHTEND####`
42			`//==========================================================================`
43			`//#####DESCRIPTIONBEGIN####`
44			`//`
45			`// Author(s): nickg`
46			`// Contributors: nickg, jlarmour`
47			`// Date: 1999-02-18`
48			`// Purpose: Define Interrupt support`
49			`// Description: The macros defined here provide the HAL APIs for handling`
50			`// interrupts and the clock.`
51			`// Usage:`
52			`// #include <cyg/hal/hal_intr.h>`
53			`// ...`
54			`//`
55			`//`
56			`//####DESCRIPTIONEND####`
57			`//`
58			`//==========================================================================`
59
60			`#include <pkgconf/hal.h>`
61
62			`#include <cyg/infra/cyg_type.h>`
63			`#include <cyg/hal/hal_io.h>`
64
65			`#include <cyg/hal/var_intr.h>`
66
67			`//--------------------------------------------------------------------------`
68			`// Static data used by HAL`
69
70			`// ISR tables`
71			`externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];`
72			`externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];`
73			`externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];`
74
75			`// VSR table`
76			`externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];`
77
78			`// MN10300 interrupt control registers, mapped by linker script.`
79			`externC volatile cyg_uint16 mn10300_interrupt_control[];`
80
81			`//--------------------------------------------------------------------------`
82			`// Default ISR`
83			`// The #define is used to test whether this routine exists, and to allow`
84			`// us to call it.`
85
86			`externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);`
87
88			`#define HAL_DEFAULT_ISR hal_default_isr`
89
90			`//--------------------------------------------------------------------------`
91			`// Interrupt state storage`
92
93			`typedef cyg_uint32 CYG_INTERRUPT_STATE;`
94
95			`//--------------------------------------------------------------------------`
96
97			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
98
99			`// Routine to execute DSRs using separate interrupt stack`
100			`externC void hal_interrupt_stack_call_pending_DSRs(void);`
101			`#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \`
102			`hal_interrupt_stack_call_pending_DSRs()`
103
104			`// these are offered solely for stack usage testing`
105			`// if they are not defined, then there is no interrupt stack.`
106			`#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base`
107			`#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack`
108			`// use them to declare these extern however you want:`
109			`// extern char HAL_INTERRUPT_STACK_BASE[];`
110			`// extern char HAL_INTERRUPT_STACK_TOP[];`
111			`// is recommended`
112
113			`#endif`
114
115			`//--------------------------------------------------------------------------`
116			`// Interrupt control macros`
117
118			`#define HAL_DISABLE_INTERRUPTS(_old_) \`
119			`asm volatile ( \`
120			`"mov psw,%0;" \`
121			`"mov 0xF7FF,d0;" \`
122			`"and %0,d0;" \`
123			`"mov d0,psw;" \`
124			`"and 0x0800,%0;" \`
125			`: "=d"(_old_) \`
126			`: \`
127			`: "d0" \`
128			`);`
129
130			`#define HAL_ENABLE_INTERRUPTS() \`
131			`asm volatile ( \`
132			`"mov psw,d0;" \`
133			`"or 0x0800,d0;" \`
134			`"mov d0,psw;" \`
135			`: \`
136			`: \`
137			`: "d0" \`
138			`);`
139
140			`#define HAL_RESTORE_INTERRUPTS(_old_) \`
141			`asm volatile ( \`
142			`"mov psw,d1;" \`
143			`"and 0xF7FF,d1;" \`
144			`"or %0,d1;" \`
145			`"mov d1,psw;" \`
146			`: \`
147			`: "d"(_old_) \`
148			`: "d1" \`
149			`);`
150
151			`#define HAL_QUERY_INTERRUPTS(_old_) \`
152			`asm volatile ( \`
153			`"mov psw,%0;" \`
154			`"and 0x0800,%0;" \`
155			`: "=d"(_old_) \`
156			`);`
157
158			`//--------------------------------------------------------------------------`
159			`// Translate a vector number into an ISR table index.`
160			`// If we have chained interrupts we have just a single ISR per priority`
161			`// level. On the MN103000 there are several interrupts per controller,`
162			`// so we have to decode to one of 100 vectors. On the MN103002 there is`
163			`// only one interrupt per controller, so we can have just one ISR per`
164			`// controller, except for the NMI vectors which occupy the first 3 slots.`
165
166			`#ifndef HAL_TRANSLATE_VECTOR`
167
168			`#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)`
169
170			`#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \`
171			`{ \`
172			`if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR ) \`
173			`(_index_) = (_vector_); \`
174			`else \`
175			`{ \`
176			`/* ICRs are 16 bit regs at 32 bit spacing */ \`
177			`cyg_ucount16 _ix_ = ((_vector_)>>2)<<1; \`
178			`\`
179			`/* read the appropriate interrupt control register */ \`
180			`cyg_uint16 _icr_ = mn10300_interrupt_control[_ix_]; \`
181			`\`
182			`/* extract interrupt priority level */ \`
183			`_index_ = CYGNUM_HAL_INTERRUPT_RESERVED_3 + ((_icr_ >> 12) & 0x7); \`
184			`} \`
185			`}`
186
187			`#else`
188
189			`#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)`
190
191			`#endif`
192
193			`#endif`
194
195			`//--------------------------------------------------------------------------`
196			`// Interrupt and VSR attachment macros`
197
198			`#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \`
199			`CYG_MACRO_START \`
200			`cyg_uint32 _index_; \`
201			`HAL_TRANSLATE_VECTOR ((_vector_), _index_); \`
202			`\`
203			`if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \`
204			`(_state_) = 0; \`
205			`else \`
206			`(_state_) = 1; \`
207			`CYG_MACRO_END`
208
209			`#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \`
210			`CYG_MACRO_START \`
211			`cyg_uint32 _index_; \`
212			`HAL_TRANSLATE_VECTOR(_vector_,_index_); \`
213			`\`
214			`if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \`
215			`{ \`
216			`hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \`
217			`hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \`
218			`hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \`
219			`} \`
220			`CYG_MACRO_END`
221
222			`#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \`
223			`CYG_MACRO_START \`
224			`cyg_uint32 _index_; \`
225			`HAL_TRANSLATE_VECTOR(_vector_,_index_); \`
226			`\`
227			`if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \`
228			`{ \`
229			`hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \`
230			`hal_interrupt_data[_index_] = 0; \`
231			`hal_interrupt_objects[_index_] = 0; \`
232			`} \`
233			`CYG_MACRO_END`
234
235			`#define HAL_VSR_GET( _vector_, _pvsr_ ) \`
236			`((CYG_ADDRESS )_pvsr_) = hal_vsr_table[_vector_];`
237
238
239			`#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \`
240			`if( _poldvsr_ != NULL ) \`
241			`(CYG_ADDRESS )_poldvsr_ = hal_vsr_table[_vector_]; \`
242			`hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;`
243
244
245			`//--------------------------------------------------------------------------`
246			`// Interrupt controller access`
247			`// Read interrupt control registers back after writing to them. This`
248			`// ensures that the written value is not sitting in the store buffers`
249			`// when interrupts are re-enabled.`
250			`#define HAL_INTERRUPT_MASK( _vector_ ) \`
251			`{ \`
252			`/* ICRs are 16 bit regs at 32 bit spacing */ \`
253			`cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \`
254			`\`
255			`/* read the appropriate interrupt control register */ \`
256			`cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \`
257			`\`
258			`/* clear interrupt enable bit for this vector */ \`
259			`_icr_ &= ~(0x0100<<((_vector_)&3)); \`
260			`\`
261			`/* restore the interrupt control register */ \`
262			`mn10300_interrupt_control[_index_] = _icr_; \`
263			`_icr_ = mn10300_interrupt_control[_index_]; \`
264			`}`
265
266			`#define HAL_INTERRUPT_UNMASK( _vector_ ) \`
267			`{ \`
268			`/* ICRs are 16 bit regs at 32 bit spacing */ \`
269			`cyg_ucount16 _index_ = (_vector_>>2)<<1; \`
270			`\`
271			`/* read the appropriate interrupt control register */ \`
272			`cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \`
273			`\`
274			`/* set interrupt enable bit for this vector */ \`
275			`_icr_ \|= (0x0100<<(_vector_&3)); \`
276			`\`
277			`/* restore the interrupt control register */ \`
278			`mn10300_interrupt_control[_index_] = _icr_; \`
279			`_icr_ = mn10300_interrupt_control[_index_]; \`
280			`}`
281
282			`#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \`
283			`{ \`
284			`/* ICRs are 16 bit regs at 32 bit spacing */ \`
285			`cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \`
286			`\`
287			`/* read the appropriate interrupt control register */ \`
288			`cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \`
289			`\`
290			`/* clear interrupt request bit for this vector */ \`
291			`_icr_ &= ~(0x0010<<((_vector_)&3)); \`
292			`\`
293			`/* set interrupt detect bit for this vector */ \`
294			`_icr_ \|= (0x0001<<((_vector_)&3)); \`
295			`\`
296			`/* restore the interrupt control register */ \`
297			`mn10300_interrupt_control[_index_] = _icr_; \`
298			`_icr_ = mn10300_interrupt_control[_index_]; \`
299			`}`
300
301			`#if !defined(HAL_INTERRUPT_CONFIGURE)`
302
303			`#error HAL_INTERRUPT_CONFIGURE not defined by variant`
304
305			`#endif`
306
307			`#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \`
308			`{ \`
309			`/* ICRs are 16 bit regs at 32 bit spacing */ \`
310			`cyg_ucount16 _index_ = (_vector_>>2)<<1; \`
311			`\`
312			`/* read the appropriate interrupt control register */ \`
313			`cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \`
314			`\`
315			`/* set interrupt level for this group of vectors */ \`
316			`_icr_ &= 0x0FFF; \`
317			`_icr_ \|= (_level_)<<12; \`
318			`\`
319			`/* restore the interrupt control register */ \`
320			`mn10300_interrupt_control[_index_] = _icr_; \`
321			`_icr_ = mn10300_interrupt_control[_index_]; \`
322			`}`
323
324			`//--------------------------------------------------------------------------`
325			`// Clock control.`
326			`// This is almost all handled in the var_intr.h.`
327
328			`#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY`
329			`#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)`
330			`#endif`
331
332			`//--------------------------------------------------------------------------`
333			`// Memory region top`
334			`//`
335			`#if CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP`
336
337			`externC cyg_uint8 hal_mn10300_mem_real_region_top( cyg_uint8 _regionend_ );`
338
339			`# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \`
340			`hal_mn10300_mem_real_region_top( _regionend_ )`
341			`#endif`
342
343
344			`//--------------------------------------------------------------------------`
345			`#endif // ifndef CYGONCE_HAL_HAL_INTR_H`
346			`// EOF hal_intr.h`