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##=============================================================================
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##
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## vectors.S
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##
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## MN10300 exception vectors
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors: nickg, dmoseley, dhowells
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## Date: 1997-10-16
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## Purpose: MN10300 exception vectors
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## Description: This file defines the code placed into the exception
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## vectors. It also contains the first level default VSRs
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## that save and restore state for both exceptions and
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## interrupts.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#ifdef CYGPKG_REDBOOT
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#include
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#endif
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#ifdef CYGPKG_KERNEL
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#include
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#endif
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#include
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#include
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##-----------------------------------------------------------------------------
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// .file "vectors.S"
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#ifdef CYGPKG_CYGMON
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##-----------------------------------------------------------------------------
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## Macros for Stack handling when running Cygmon
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.macro hal_cygmon_switch_app_stack
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#
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# Switch to interrupt stack to handle exception
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#
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# First, save some scratch registers
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mov a2(a2_save)
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mov a3,(a3_save)
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# Copy the exception frame
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mov __cygmon_interrupt_stack-8,a2
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mov (sp),a3 // Copy over the saved EPSW
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mov a3,(a2)
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mov (4,sp),a3 // Copy over the saved PC
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mov a3,(4,a2)
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# Save the pre-exception sp in the register image
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add -4,a2 # space for SP
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mov sp,a3
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add 8,a3 # adjust for exception frame
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mov a3,(a2)
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# Actually switch the stack
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mov a2,sp
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# Now, restore the scratch registers
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mov (a2_save),a2
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mov (a3_save),a3
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.endm
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.macro hal_cygmon_restore_app_stack
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// For cygmon we are switching stacks immediately on exception.
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// We must wait until the very end before restoring the original stack.
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# Save some scratch registers
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mov a2,(a2_save)
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mov a3,(a3_save)
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# We need to restore the application stack pointer, but we also
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# need to restore the exception frame.
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mov (sp),a2
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add 4,sp // remove saved sp
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add -8,a2 // adjust for exception frame
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mov (sp),a3 // Copy the saved EPSW
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mov a3,(a2)
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mov (4,sp),a3 // Copy the saved PC
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mov a3,(4,a2)
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mov a2,sp // Restore the frame-adjusted SP
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# Restore the scratch registers
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mov (a2_save),a2
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mov (a3_save),a3
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.endm
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#endif // CYGPKG_CYGMON
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##-----------------------------------------------------------------------------
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#define EXCEPTION_HANDLER(VECTOR,NAME,HANDLER) .org VECTOR; \
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NAME##_vector: \
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jmp HANDLER
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.section ".vectors","ax"
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.globl reset_vector
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.org 0x000
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reset_vector:
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# Reset vector
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jmp _start
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EXCEPTION_HANDLER(0x008, nmi ,__nmi)
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EXCEPTION_HANDLER(0x010, trap ,__trap)
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EXCEPTION_HANDLER(0x100, ins_tlb_miss_exception ,__unknown)
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EXCEPTION_HANDLER(0x108, data_tlb_miss_exception ,__unknown)
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EXCEPTION_HANDLER(0x110, ins_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x118, data_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x160, priv_ins_exception ,__unknown)
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EXCEPTION_HANDLER(0x168, unimpl_ins_exception ,__unknown)
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EXCEPTION_HANDLER(0x170, unimpl_ext_ins_exception ,__unknown)
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EXCEPTION_HANDLER(0x180, misalignment_exception ,__unknown)
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EXCEPTION_HANDLER(0x188, bus_error ,__unknown)
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EXCEPTION_HANDLER(0x190, illegal_ins_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x198, illegal_data_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x1a0, iospace_ins_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x1a8, priv_space_ins_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x1b0, priv_space_data_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x1b8, data_space_ins_access_exception ,__unknown)
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EXCEPTION_HANDLER(0x1c0, fpu_disabled_exception ,__unknown)
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EXCEPTION_HANDLER(0x1c8, fpu_unimplemented_exception ,__unknown)
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EXCEPTION_HANDLER(0x1d0, fpu_operation_exception ,__unknown)
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EXCEPTION_HANDLER(0x200, double_fault ,__unknown)
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EXCEPTION_HANDLER(0x240, wdt_overflow ,__unknown)
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EXCEPTION_HANDLER(0x248, nmi_pin ,__nmi)
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EXCEPTION_HANDLER(0x280, maskable_int0 ,__unknown)
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EXCEPTION_HANDLER(0x288, maskable_int1 ,__unknown)
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EXCEPTION_HANDLER(0x290, maskable_int2 ,__unknown)
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EXCEPTION_HANDLER(0x298, maskable_int3 ,__unknown)
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EXCEPTION_HANDLER(0x2a0, maskable_int4 ,__unknown)
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EXCEPTION_HANDLER(0x2a8, maskable_int5 ,__unknown)
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EXCEPTION_HANDLER(0x2b0, maskable_int6 ,__unknown)
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| 182 |
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// We need to put the syscall handler at 0x300
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// For cygmon, we will use the am33 "syscall 0" as the syscall trap.
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EXCEPTION_HANDLER(0x300, syscall0 ,__nmi)
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EXCEPTION_HANDLER(0x308, syscall1 ,__unknown)
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EXCEPTION_HANDLER(0x310, syscall2 ,__unknown)
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EXCEPTION_HANDLER(0x318, syscall3 ,__unknown)
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EXCEPTION_HANDLER(0x320, syscall4 ,__unknown)
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| 189 |
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EXCEPTION_HANDLER(0x328, syscall5 ,__unknown)
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EXCEPTION_HANDLER(0x330, syscall6 ,__unknown)
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EXCEPTION_HANDLER(0x338, syscall7 ,__unknown)
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| 192 |
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EXCEPTION_HANDLER(0x340, syscall8 ,__unknown)
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| 193 |
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EXCEPTION_HANDLER(0x348, syscall9 ,__unknown)
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| 194 |
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EXCEPTION_HANDLER(0x350, syscalla ,__unknown)
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EXCEPTION_HANDLER(0x358, syscallb ,__unknown)
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EXCEPTION_HANDLER(0x360, syscallc ,__unknown)
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| 197 |
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EXCEPTION_HANDLER(0x368, syscalld ,__unknown)
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EXCEPTION_HANDLER(0x370, syscalle ,__unknown)
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EXCEPTION_HANDLER(0x378, syscallf ,__unknown)
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| 200 |
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| 201 |
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##-----------------------------------------------------------------------------
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| 202 |
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## unknown interrupt or exception vector
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| 203 |
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__unknown:
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| 204 |
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#ifdef CYG_HAL_HANDLE_UNKNOWN_INT_DEFINED
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hal_handle_unknown_int
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#endif
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| 208 |
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##-----------------------------------------------------------------------------
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## NMI vector
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.globl __nmi
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| 212 |
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__nmi:
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| 213 |
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#ifdef CYGPKG_CYGMON
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hal_cygmon_switch_app_stack
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#else
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| 216 |
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add -4,sp # space for SP
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| 217 |
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#endif
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| 218 |
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hal_cpu_save_all # push all registers
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| 219 |
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mov (_hal_vsr_table+28),a0
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jmp (a0)
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| 222 |
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##-----------------------------------------------------------------------------
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| 223 |
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## Trap vector
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| 224 |
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| 225 |
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.globl __trap
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| 226 |
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__trap:
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| 227 |
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#ifdef CYGPKG_CYGMON
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| 228 |
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add -4,sp # space for PSW
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| 229 |
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hal_cygmon_switch_app_stack
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| 230 |
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#else
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| 231 |
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add -8,sp # space for SP and PSW
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| 232 |
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#endif
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| 233 |
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hal_cpu_save_all # push all registers
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| 234 |
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mov (_hal_vsr_table+32),a0
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| 235 |
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jmp (a0)
|
| 236 |
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|
| 237 |
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##-----------------------------------------------------------------------------
|
| 238 |
|
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## Macro to define a hardware VSR
|
| 239 |
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| 240 |
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.macro hardware_vector name
|
| 241 |
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.globl __hardware_vector_\name
|
| 242 |
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__hardware_vector_\name:
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| 243 |
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#ifdef CYGPKG_CYGMON
|
| 244 |
|
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hal_cygmon_switch_app_stack
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| 245 |
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#else
|
| 246 |
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add -4,sp # space for SP
|
| 247 |
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#endif
|
| 248 |
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hal_cpu_save_all
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| 249 |
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mov \name,d0 # d0 = vector id
|
| 250 |
|
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mov d0,(0,sp) # save in dummy stack loc
|
| 251 |
|
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mov _hal_vsr_table,a0 # a0 = vsr table
|
| 252 |
|
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add \name<<2,a0 # a0 = &required vsr
|
| 253 |
|
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mov (a0),a0 # a0 = required vsr
|
| 254 |
|
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jmp (a0) # go there
|
| 255 |
|
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.endm
|
| 256 |
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|
| 257 |
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##-----------------------------------------------------------------------------
|
| 258 |
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## Hardware Vectors. These are pointed to by the registers in
|
| 259 |
|
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## mn10300_interrupt_vectors and must be in the range 0x4000XXXX.
|
| 260 |
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|
| 261 |
|
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hardware_vector 0
|
| 262 |
|
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hardware_vector 1
|
| 263 |
|
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hardware_vector 2
|
| 264 |
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hardware_vector 3
|
| 265 |
|
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hardware_vector 4
|
| 266 |
|
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hardware_vector 5
|
| 267 |
|
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hardware_vector 6
|
| 268 |
|
|
|
| 269 |
|
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##-----------------------------------------------------------------------------
|
| 270 |
|
|
## Startup code
|
| 271 |
|
|
|
| 272 |
|
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.text
|
| 273 |
|
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|
| 274 |
|
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.globl _start
|
| 275 |
|
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_start:
|
| 276 |
|
|
|
| 277 |
|
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#ifdef HAL_EARLY_INIT
|
| 278 |
|
|
HAL_EARLY_INIT
|
| 279 |
|
|
#endif
|
| 280 |
|
|
# set up stack
|
| 281 |
|
|
|
| 282 |
|
|
mov __interrupt_stack,a0
|
| 283 |
|
|
sub 8,a0
|
| 284 |
|
|
mov a0,sp
|
| 285 |
|
|
|
| 286 |
|
|
# Initialize hardware
|
| 287 |
|
|
hal_cpu_init
|
| 288 |
|
|
hal_mmu_init
|
| 289 |
|
|
hal_memc_init
|
| 290 |
|
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hal_diag_init
|
| 291 |
|
|
hal_intc_init
|
| 292 |
|
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hal_cache_init
|
| 293 |
|
|
hal_timer_init
|
| 294 |
|
|
hal_mon_init
|
| 295 |
|
|
|
| 296 |
|
|
#ifdef CYG_HAL_STARTUP_ROM
|
| 297 |
|
|
|
| 298 |
|
|
# Copy data from ROM to RAM
|
| 299 |
|
|
|
| 300 |
|
|
mov __rom_data_start,a0
|
| 301 |
|
|
mov __ram_data_end,a1
|
| 302 |
|
|
mov __ram_data_start,a2
|
| 303 |
|
|
|
| 304 |
|
|
cmp a2,a1
|
| 305 |
|
|
beq 8f
|
| 306 |
|
|
1:
|
| 307 |
|
|
movbu (a0),d0
|
| 308 |
|
|
movbu d0,(a2)
|
| 309 |
|
|
inc a0
|
| 310 |
|
|
inc a2
|
| 311 |
|
|
cmp a2,a1
|
| 312 |
|
|
bne 1b
|
| 313 |
|
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8:
|
| 314 |
|
|
|
| 315 |
|
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#endif
|
| 316 |
|
|
|
| 317 |
|
|
# Clear BSS
|
| 318 |
|
|
mov __bss_start,a0
|
| 319 |
|
|
mov __bss_end,a1
|
| 320 |
|
|
|
| 321 |
|
|
cmp a0,a1
|
| 322 |
|
|
beq 8f
|
| 323 |
|
|
clr d0
|
| 324 |
|
|
1:
|
| 325 |
|
|
movbu d0,(a0)
|
| 326 |
|
|
inc a0
|
| 327 |
|
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cmp a0,a1
|
| 328 |
|
|
bne 1b
|
| 329 |
|
|
8:
|
| 330 |
|
|
|
| 331 |
|
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# Call variant and platform HAL
|
| 332 |
|
|
# initialization routines.
|
| 333 |
|
|
|
| 334 |
|
|
.extern _hal_variant_init
|
| 335 |
|
|
call _hal_variant_init,[],0
|
| 336 |
|
|
|
| 337 |
|
|
.extern _hal_platform_init
|
| 338 |
|
|
call _hal_platform_init,[],0
|
| 339 |
|
|
|
| 340 |
|
|
# Call constructors
|
| 341 |
|
|
|
| 342 |
|
|
.extern _cyg_hal_invoke_constructors
|
| 343 |
|
|
call _cyg_hal_invoke_constructors,[],0
|
| 344 |
|
|
|
| 345 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
| 346 |
|
|
.extern _initialize_stub
|
| 347 |
|
|
call _initialize_stub,[],0
|
| 348 |
|
|
#endif
|
| 349 |
|
|
|
| 350 |
|
|
#ifdef CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT
|
| 351 |
|
|
.extern hal_ctrlc_isr_init
|
| 352 |
|
|
call hal_ctrlc_isr_init,[],0
|
| 353 |
|
|
#endif
|
| 354 |
|
|
|
| 355 |
|
|
# Call cyg_start
|
| 356 |
|
|
clr d0
|
| 357 |
|
|
mov d0,(4,sp)
|
| 358 |
|
|
|
| 359 |
|
|
.extern _cyg_start
|
| 360 |
|
|
call _cyg_start,[],0
|
| 361 |
|
|
|
| 362 |
|
|
9:
|
| 363 |
|
|
bra 9b # Loop if we return
|
| 364 |
|
|
|
| 365 |
|
|
##-----------------------------------------------------------------------------
|
| 366 |
|
|
## The following macros are defined depending on whether the HAL is configured
|
| 367 |
|
|
## to support the kernel or not.
|
| 368 |
|
|
|
| 369 |
|
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
|
| 370 |
|
|
|
| 371 |
|
|
.extern _cyg_scheduler_sched_lock
|
| 372 |
|
|
|
| 373 |
|
|
# Increment the scheduler lock
|
| 374 |
|
|
|
| 375 |
|
|
.macro increment_sched_lock reg=d0
|
| 376 |
|
|
mov (_cyg_scheduler_sched_lock),\reg
|
| 377 |
|
|
inc \reg
|
| 378 |
|
|
mov \reg,(_cyg_scheduler_sched_lock)
|
| 379 |
|
|
.endm
|
| 380 |
|
|
|
| 381 |
|
|
#else
|
| 382 |
|
|
|
| 383 |
|
|
.macro increment_sched_lock reg=d0
|
| 384 |
|
|
.endm
|
| 385 |
|
|
|
| 386 |
|
|
#endif
|
| 387 |
|
|
|
| 388 |
|
|
##-----------------------------------------------------------------------------
|
| 389 |
|
|
## Default interrupt VSR
|
| 390 |
|
|
|
| 391 |
|
|
.text
|
| 392 |
|
|
.globl __default_interrupt_vsr
|
| 393 |
|
|
__default_interrupt_vsr:
|
| 394 |
|
|
|
| 395 |
|
|
# We come here with all the registers pushed
|
| 396 |
|
|
# onto the stack.
|
| 397 |
|
|
|
| 398 |
|
|
hal_diag_intr_start
|
| 399 |
|
|
|
| 400 |
|
|
increment_sched_lock
|
| 401 |
|
|
|
| 402 |
|
|
#if defined(CYGPKG_CYGMON)
|
| 403 |
|
|
// For Cygmon, we saved this back when we originally switched stacks.
|
| 404 |
|
|
mov (sp),a2 # A2 = saved thread state
|
| 405 |
|
|
#elif defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK)
|
| 406 |
|
|
# Increment interrupt nesting counter
|
| 407 |
|
|
mov __interrupt_stack,a0 # A0 = interrupt stack top
|
| 408 |
|
|
mov sp,a2 # A2 = SP
|
| 409 |
|
|
cmp __interrupt_stack_base,a2 # compare with base of stack
|
| 410 |
|
|
blt 1f # if lt switch to int stack
|
| 411 |
|
|
cmp a0,a2 # compare sp with stack top
|
| 412 |
|
|
ble 8f # if le already on istack
|
| 413 |
|
|
1:
|
| 414 |
|
|
mov a0,sp # switch to new SP
|
| 415 |
|
|
8:
|
| 416 |
|
|
movm [a2],(sp) # save old SP
|
| 417 |
|
|
|
| 418 |
|
|
#else
|
| 419 |
|
|
mov sp,a2 # A2 = saved thread state
|
| 420 |
|
|
#endif
|
| 421 |
|
|
|
| 422 |
|
|
# Here A2 -> saved thread state on the threads own
|
| 423 |
|
|
# stack. We will be executing either on the same stack
|
| 424 |
|
|
# or on the interrupt stack, depending on config options.
|
| 425 |
|
|
|
| 426 |
|
|
hal_intc_decode d3,a3,d0
|
| 427 |
|
|
|
| 428 |
|
|
# Here D3 contains the table byte offset of the vector to
|
| 429 |
|
|
# call.
|
| 430 |
|
|
|
| 431 |
|
|
#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
|
| 432 |
|
|
|
| 433 |
|
|
# Call cyg_instrument to record that this interrupt is being raised.
|
| 434 |
|
|
|
| 435 |
|
|
.extern _cyg_instrument
|
| 436 |
|
|
add -16,sp # make space for return link + args
|
| 437 |
|
|
mov 0x0301,d0 # d0 = type = INTR,RAISE
|
| 438 |
|
|
mov (0,a2),d1 # d1 = arg1 = vector
|
| 439 |
|
|
mov d3,(12,sp) # (12,sp) = arg2 = table offset
|
| 440 |
|
|
calls _cyg_instrument # call instrumentation
|
| 441 |
|
|
add 16,sp # pop space
|
| 442 |
|
|
|
| 443 |
|
|
#endif
|
| 444 |
|
|
|
| 445 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
|
| 446 |
|
|
.extern _cyg_hal_gdb_isr
|
| 447 |
|
|
add -16,sp # make space for return link + args
|
| 448 |
|
|
mov (0,a2),d0 # d0 = vector
|
| 449 |
|
|
mov (SAVED_CONTEXT_PC_OFFSET,a2),d1 # d1 = pc
|
| 450 |
|
|
calls _cyg_hal_gdb_isr # call GDB isr function
|
| 451 |
|
|
cmp 0x00,d0 # Call ISR proper?
|
| 452 |
|
|
beq 2f # (d0 is 0 when skipping
|
| 453 |
|
|
# to avoid DSR call)
|
| 454 |
|
|
add 16,sp # pop space
|
| 455 |
|
|
#endif
|
| 456 |
|
|
|
| 457 |
|
|
#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
|
| 458 |
|
|
|
| 459 |
|
|
# To allow nested interrupts, we set the IE bit. We do
|
| 460 |
|
|
# not touch the IPL bits, so only higher priority interrupts
|
| 461 |
|
|
# will be nested on top of us. Also, new interrupts will not
|
| 462 |
|
|
# be delivered until the ISR calls
|
| 463 |
|
|
# Cyg_Interrupt::acknowledge_interrupt(). At some future point
|
| 464 |
|
|
# we may want to do the ack stuff here to allow immediate nesting.
|
| 465 |
|
|
|
| 466 |
|
|
or 0x0800,psw
|
| 467 |
|
|
|
| 468 |
|
|
#endif
|
| 469 |
|
|
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
|
| 470 |
|
|
|
| 471 |
|
|
# If we have Ctrl-C support enabled, save a pointer to the
|
| 472 |
|
|
# saved CPU state here so we can plant a breakpoint there if
|
| 473 |
|
|
# this is a ^C.
|
| 474 |
|
|
|
| 475 |
|
|
.extern _hal_saved_interrupt_state
|
| 476 |
|
|
mov a2,(_hal_saved_interrupt_state)
|
| 477 |
|
|
|
| 478 |
|
|
#endif
|
| 479 |
|
|
|
| 480 |
|
|
mov _hal_interrupt_handlers,a0 # a0 = isr table
|
| 481 |
|
|
mov (d3,a0),a0 # a0 = isr
|
| 482 |
|
|
|
| 483 |
|
|
mov _hal_interrupt_data,a1 # a1 = data table
|
| 484 |
|
|
mov (d3,a1),d1 # d1 = isr data
|
| 485 |
|
|
|
| 486 |
|
|
mov (0,a2),d0 # d0 = vector. (d3 is...
|
| 487 |
|
|
# ...adjusted for table reads)
|
| 488 |
|
|
|
| 489 |
|
|
add -16,sp # make space for return link
|
| 490 |
|
|
|
| 491 |
|
|
calls (a0) # call isr
|
| 492 |
|
|
|
| 493 |
|
|
# on return d0 bit 1 will indicate whether a DSR is
|
| 494 |
|
|
# to be posted. Pass this together with a pointer to
|
| 495 |
|
|
# the interrupt object we have just used to the
|
| 496 |
|
|
# interrupt tidy up routine.
|
| 497 |
|
|
|
| 498 |
|
|
# D3 is defined to be saved across procedure calls, and
|
| 499 |
|
|
# should still contain the vector byte index. Similarly,
|
| 500 |
|
|
# A2 should still point to the saved machine state.
|
| 501 |
|
|
|
| 502 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
|
| 503 |
|
|
# If interrupt was caused by GDB, the ISR call above
|
| 504 |
|
|
# is skipped by jumping here.
|
| 505 |
|
|
2:
|
| 506 |
|
|
#endif
|
| 507 |
|
|
|
| 508 |
|
|
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK) && !defined(CYGPKG_CYGMON)
|
| 509 |
|
|
|
| 510 |
|
|
# If we are returning from the last nested interrupt, move back
|
| 511 |
|
|
# to the thread stack. interrupt_end() must be called on the
|
| 512 |
|
|
# thread stack since it potentially causes a context switch.
|
| 513 |
|
|
|
| 514 |
|
|
add 16,sp # pop call frame from int stack
|
| 515 |
|
|
movm (sp),[a3] # pop old sp
|
| 516 |
|
|
mov a3,sp # put in SP
|
| 517 |
|
|
|
| 518 |
|
|
add -16,sp # make call frame for call
|
| 519 |
|
|
|
| 520 |
|
|
#endif
|
| 521 |
|
|
|
| 522 |
|
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
|
| 523 |
|
|
|
| 524 |
|
|
# We only need to call _interrupt_end() when there is a kernel
|
| 525 |
|
|
# present to do any tidying up.
|
| 526 |
|
|
|
| 527 |
|
|
# Using the vector offset in D3, get the interrupt object pointer
|
| 528 |
|
|
# into D1.
|
| 529 |
|
|
mov _hal_interrupt_objects,a0 # a0 = object table
|
| 530 |
|
|
mov (d3,a0),d1 # d1 = object
|
| 531 |
|
|
|
| 532 |
|
|
# Even when this is not the last nested interrupt, we must call
|
| 533 |
|
|
# _interrupt_end() to post the DSR and decrement the scheduler
|
| 534 |
|
|
# lock.
|
| 535 |
|
|
|
| 536 |
|
|
mov a2,(12,sp) # arg3 = saved state.
|
| 537 |
|
|
|
| 538 |
|
|
calls _interrupt_end # call interrupt end fn
|
| 539 |
|
|
#endif
|
| 540 |
|
|
|
| 541 |
|
|
add 16,sp # pop return link
|
| 542 |
|
|
|
| 543 |
|
|
# show_interrupts
|
| 544 |
|
|
|
| 545 |
|
|
hal_diag_restore
|
| 546 |
|
|
|
| 547 |
|
|
hal_cpu_load_all
|
| 548 |
|
|
#ifdef CYGPKG_CYGMON
|
| 549 |
|
|
hal_cygmon_restore_app_stack
|
| 550 |
|
|
#else
|
| 551 |
|
|
add 4,sp
|
| 552 |
|
|
#endif
|
| 553 |
|
|
rti # and return
|
| 554 |
|
|
|
| 555 |
|
|
##-----------------------------------------------------------------------------
|
| 556 |
|
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
| 557 |
|
|
## Note: this can only be called from code running on a thread stack
|
| 558 |
|
|
|
| 559 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 560 |
|
|
.extern _cyg_interrupt_call_pending_DSRs
|
| 561 |
|
|
.global _hal_interrupt_stack_call_pending_DSRs
|
| 562 |
|
|
|
| 563 |
|
|
_hal_interrupt_stack_call_pending_DSRs:
|
| 564 |
|
|
movm [d2,a2],(sp) # save some work regs
|
| 565 |
|
|
mov __interrupt_stack,a0 # interrupt stack pointer
|
| 566 |
|
|
mov sp,a2 # save current SP
|
| 567 |
|
|
mov a0,sp # set SP to interrupt stack
|
| 568 |
|
|
hal_cpu_get_psw d2 # save PSW
|
| 569 |
|
|
hal_cpu_int_enable # enable interrupts
|
| 570 |
|
|
|
| 571 |
|
|
# Call kernel code to invoke DSRs.
|
| 572 |
|
|
calls _cyg_interrupt_call_pending_DSRs
|
| 573 |
|
|
|
| 574 |
|
|
# On return the old SP in a2 and the old PSW in d2 will
|
| 575 |
|
|
# have been preserved by the calling conventions.
|
| 576 |
|
|
|
| 577 |
|
|
hal_cpu_int_merge d2 # Restore previous PSW
|
| 578 |
|
|
mov a2,sp # restore old SP
|
| 579 |
|
|
movm (sp),[d2,a2] # Retrieve old work regs
|
| 580 |
|
|
ret [],0 # and return
|
| 581 |
|
|
|
| 582 |
|
|
#endif
|
| 583 |
|
|
|
| 584 |
|
|
##-----------------------------------------------------------------------------
|
| 585 |
|
|
## Default NMI VSR
|
| 586 |
|
|
|
| 587 |
|
|
.globl _cyg_hal_exception_handler
|
| 588 |
|
|
|
| 589 |
|
|
.text
|
| 590 |
|
|
.globl __default_nmi_vsr
|
| 591 |
|
|
__default_nmi_vsr:
|
| 592 |
|
|
|
| 593 |
|
|
# We come here with all the registers saved
|
| 594 |
|
|
# on the stack.
|
| 595 |
|
|
|
| 596 |
|
|
#ifdef CYG_HAL_DIAG_EXCPT_END
|
| 597 |
|
|
hal_diag_excpt_start
|
| 598 |
|
|
#endif
|
| 599 |
|
|
|
| 600 |
|
|
# Decode the cause of the NMI and cancel all the bits in all
|
| 601 |
|
|
# the registers. We need to clear any bits set in the ISR and
|
| 602 |
|
|
# then clear any bits set in the NMICR. Note that we can only
|
| 603 |
|
|
# access the ISR if the DCR:DE bit is set.
|
| 604 |
|
|
|
| 605 |
|
|
movhu (NMICR),d0 # D0 = NMI Control register
|
| 606 |
|
|
|
| 607 |
|
|
movhu (DCR),d1 # D1 = Debug Control Register
|
| 608 |
|
|
mov d1,d2 # D2 = copy of DCR
|
| 609 |
|
|
movhu (ISR),d3 # D3 = Interrupt Status Register
|
| 610 |
|
|
|
| 611 |
|
|
or DCR_DE,d1 # Set DE bit
|
| 612 |
|
|
movhu d1,(DCR)
|
| 613 |
|
|
|
| 614 |
|
|
movhu d3,(ISR) # clear ISR bits
|
| 615 |
|
|
|
| 616 |
|
|
movhu d2,(DCR) # restore DCR to original value
|
| 617 |
|
|
|
| 618 |
|
|
movhu d0,(NMICR) # clear NMI bits
|
| 619 |
|
|
and 0x7,d0 # LS 3 bits only
|
| 620 |
|
|
|
| 621 |
|
|
mov hal_lsbit_table,a0
|
| 622 |
|
|
movbu (d0,a0),d1 # D1 = NMI code
|
| 623 |
|
|
## 0 = NMI
|
| 624 |
|
|
## 1 = Watchdog
|
| 625 |
|
|
## 2 = System Error
|
| 626 |
|
|
|
| 627 |
|
|
add 9,d1 # offset into exception number space
|
| 628 |
|
|
|
| 629 |
|
|
#if defined(CYGPKG_CYGMON) || defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
|
| 630 |
|
|
# Check to see if this was a syscall.
|
| 631 |
|
|
# If so, set d1 appropriately
|
| 632 |
|
|
#define TBR 0xC0000024
|
| 633 |
|
|
mov (TBR), d0
|
| 634 |
|
|
and 0x00FFFFFF, d0
|
| 635 |
|
|
cmp 0x300, d0
|
| 636 |
|
|
bne 0f
|
| 637 |
|
|
|
| 638 |
|
|
# This was apparently a syscall.
|
| 639 |
|
|
mov SIGSYSCALL, d1
|
| 640 |
|
|
|
| 641 |
|
|
0:
|
| 642 |
|
|
#endif
|
| 643 |
|
|
hal_cpu_clear_nmid
|
| 644 |
|
|
|
| 645 |
|
|
mov d1,(sp) # save initial vector in spare save slot
|
| 646 |
|
|
|
| 647 |
|
|
mov sp,a1 # a1 = saved state
|
| 648 |
|
|
|
| 649 |
|
|
mov a1,d0 # d0 = arg1 = saved state
|
| 650 |
|
|
|
| 651 |
|
|
add -16,sp # return link + args
|
| 652 |
|
|
mov d3,d1 # d1 = arg2 = ISR value
|
| 653 |
|
|
|
| 654 |
|
|
calls _cyg_hal_exception_handler # call C code
|
| 655 |
|
|
|
| 656 |
|
|
add 16,sp # pop args
|
| 657 |
|
|
|
| 658 |
|
|
#ifdef CYG_HAL_DIAG_EXCPT_END
|
| 659 |
|
|
hal_diag_excpt_end
|
| 660 |
|
|
#endif
|
| 661 |
|
|
|
| 662 |
|
|
hal_cpu_load_all
|
| 663 |
|
|
|
| 664 |
|
|
#ifdef CYGPKG_CYGMON
|
| 665 |
|
|
hal_cygmon_restore_app_stack
|
| 666 |
|
|
#else
|
| 667 |
|
|
add 4,sp
|
| 668 |
|
|
#endif
|
| 669 |
|
|
|
| 670 |
|
|
rti
|
| 671 |
|
|
|
| 672 |
|
|
.globl hal_lsbit_table
|
| 673 |
|
|
hal_lsbit_table:
|
| 674 |
|
|
.byte 0, 0, 1, 0
|
| 675 |
|
|
.byte 2, 0, 1, 0
|
| 676 |
|
|
.byte 3, 0, 1, 0
|
| 677 |
|
|
.byte 2, 0, 1, 0
|
| 678 |
|
|
|
| 679 |
|
|
#ifdef CYGPKG_CYGMON
|
| 680 |
|
|
.section ".bss"
|
| 681 |
|
|
d0_save:
|
| 682 |
|
|
.long 0
|
| 683 |
|
|
d1_save:
|
| 684 |
|
|
.long 0
|
| 685 |
|
|
d2_save:
|
| 686 |
|
|
.long 0
|
| 687 |
|
|
d3_save:
|
| 688 |
|
|
.long 0
|
| 689 |
|
|
a0_save:
|
| 690 |
|
|
.long 0
|
| 691 |
|
|
a1_save:
|
| 692 |
|
|
.long 0
|
| 693 |
|
|
a2_save:
|
| 694 |
|
|
.long 0
|
| 695 |
|
|
a3_save:
|
| 696 |
|
|
.long 0
|
| 697 |
|
|
sp_save:
|
| 698 |
|
|
.long 0
|
| 699 |
|
|
#endif
|
| 700 |
|
|
|
| 701 |
|
|
##-----------------------------------------------------------------------------
|
| 702 |
|
|
## Default TRAP VSR
|
| 703 |
|
|
|
| 704 |
|
|
.text
|
| 705 |
|
|
.globl __default_trap_vsr
|
| 706 |
|
|
__default_trap_vsr:
|
| 707 |
|
|
|
| 708 |
|
|
#ifdef CYG_HAL_DIAG_EXCPT_END
|
| 709 |
|
|
hal_diag_excpt_start
|
| 710 |
|
|
#endif
|
| 711 |
|
|
|
| 712 |
|
|
# We come here with all the registers saved
|
| 713 |
|
|
# on the stack.
|
| 714 |
|
|
mov 8,d1
|
| 715 |
|
|
mov d1,(sp) # set the VSR vector number
|
| 716 |
|
|
mov sp,a1 # a1 = saved state
|
| 717 |
|
|
mov a1,d0 # d0 = arg1 = saved state
|
| 718 |
|
|
|
| 719 |
|
|
add -16,sp # return link + arg
|
| 720 |
|
|
mov 3,d1 # d1 = arg2 = ISR value (3 == TRAP trap)
|
| 721 |
|
|
calls _cyg_hal_exception_handler # call C code
|
| 722 |
|
|
add 16,sp # pop args
|
| 723 |
|
|
|
| 724 |
|
|
#ifdef CYG_HAL_DIAG_EXCPT_END
|
| 725 |
|
|
hal_diag_excpt_end
|
| 726 |
|
|
#endif
|
| 727 |
|
|
hal_cpu_load_all
|
| 728 |
|
|
#ifdef CYGPKG_CYGMON
|
| 729 |
|
|
hal_cygmon_restore_app_stack
|
| 730 |
|
|
add 4,sp
|
| 731 |
|
|
#else
|
| 732 |
|
|
add 8,sp
|
| 733 |
|
|
#endif
|
| 734 |
|
|
rets
|
| 735 |
|
|
|
| 736 |
|
|
##-----------------------------------------------------------------------------
|
| 737 |
|
|
## VSR table. The VSRs pointed to by this table are called from the stubs
|
| 738 |
|
|
## connected to the hardware.
|
| 739 |
|
|
|
| 740 |
|
|
#ifndef CYG_HAL_MN10300_VSR_TABLE_DEFINED
|
| 741 |
|
|
|
| 742 |
|
|
.data
|
| 743 |
|
|
|
| 744 |
|
|
.globl _hal_vsr_table
|
| 745 |
|
|
_hal_vsr_table:
|
| 746 |
|
|
.long __default_interrupt_vsr
|
| 747 |
|
|
.long __default_interrupt_vsr
|
| 748 |
|
|
.long __default_interrupt_vsr
|
| 749 |
|
|
.long __default_interrupt_vsr
|
| 750 |
|
|
.long __default_interrupt_vsr
|
| 751 |
|
|
.long __default_interrupt_vsr
|
| 752 |
|
|
.long __default_interrupt_vsr
|
| 753 |
|
|
.long __default_nmi_vsr
|
| 754 |
|
|
.long __default_trap_vsr
|
| 755 |
|
|
|
| 756 |
|
|
.long __default_nmi_vsr
|
| 757 |
|
|
.long __default_nmi_vsr
|
| 758 |
|
|
.long __default_nmi_vsr
|
| 759 |
|
|
|
| 760 |
|
|
.long __default_nmi_vsr
|
| 761 |
|
|
.long __default_nmi_vsr
|
| 762 |
|
|
.long __default_nmi_vsr
|
| 763 |
|
|
.long __default_nmi_vsr
|
| 764 |
|
|
.long __default_nmi_vsr
|
| 765 |
|
|
.long __default_nmi_vsr
|
| 766 |
|
|
.long __default_nmi_vsr
|
| 767 |
|
|
.long __default_nmi_vsr
|
| 768 |
|
|
.long __default_nmi_vsr
|
| 769 |
|
|
.long __default_nmi_vsr
|
| 770 |
|
|
.long __default_nmi_vsr
|
| 771 |
|
|
.long __default_nmi_vsr
|
| 772 |
|
|
.long __default_nmi_vsr
|
| 773 |
|
|
.long __default_nmi_vsr
|
| 774 |
|
|
.long __default_nmi_vsr
|
| 775 |
|
|
.long __default_nmi_vsr
|
| 776 |
|
|
#endif
|
| 777 |
|
|
|
| 778 |
|
|
##-----------------------------------------------------------------------------
|
| 779 |
|
|
## Interrupt tables
|
| 780 |
|
|
|
| 781 |
|
|
.data
|
| 782 |
|
|
|
| 783 |
|
|
.extern _hal_default_isr
|
| 784 |
|
|
|
| 785 |
|
|
.globl _hal_interrupt_handlers
|
| 786 |
|
|
_hal_interrupt_handlers:
|
| 787 |
|
|
.rept CYG_ISR_TABLE_SIZE
|
| 788 |
|
|
.long _hal_default_isr
|
| 789 |
|
|
.endr
|
| 790 |
|
|
|
| 791 |
|
|
.globl _hal_interrupt_data
|
| 792 |
|
|
_hal_interrupt_data:
|
| 793 |
|
|
.rept CYG_ISR_TABLE_SIZE
|
| 794 |
|
|
.long 0
|
| 795 |
|
|
.endr
|
| 796 |
|
|
|
| 797 |
|
|
.globl _hal_interrupt_objects
|
| 798 |
|
|
_hal_interrupt_objects:
|
| 799 |
|
|
.rept CYG_ISR_TABLE_SIZE
|
| 800 |
|
|
.long 0
|
| 801 |
|
|
.endr
|
| 802 |
|
|
|
| 803 |
|
|
|
| 804 |
|
|
##-----------------------------------------------------------------------------
|
| 805 |
|
|
## Temporary interrupt stack
|
| 806 |
|
|
|
| 807 |
|
|
.section ".bss"
|
| 808 |
|
|
|
| 809 |
|
|
.balign 16
|
| 810 |
|
|
.global _cyg_interrupt_stack_base
|
| 811 |
|
|
_cyg_interrupt_stack_base:
|
| 812 |
|
|
__interrupt_stack_base:
|
| 813 |
|
|
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
|
| 814 |
|
|
.byte 0
|
| 815 |
|
|
.endr
|
| 816 |
|
|
.balign 16
|
| 817 |
|
|
.global _cyg_interrupt_stack
|
| 818 |
|
|
_cyg_interrupt_stack:
|
| 819 |
|
|
__interrupt_stack:
|
| 820 |
|
|
|
| 821 |
|
|
#ifdef CYGPKG_CYGMON
|
| 822 |
|
|
.balign 16
|
| 823 |
|
|
.global __cygmon_interrupt_stack_base
|
| 824 |
|
|
__cygmon_interrupt_stack_base:
|
| 825 |
|
|
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
|
| 826 |
|
|
.byte 0
|
| 827 |
|
|
.endr
|
| 828 |
|
|
.balign 16
|
| 829 |
|
|
.global __cygmon_interrupt_stack
|
| 830 |
|
|
__cygmon_interrupt_stack:
|
| 831 |
|
|
#endif
|
| 832 |
|
|
|
| 833 |
|
|
.long 0,0,0,0,0,0,0,0
|
| 834 |
|
|
|
| 835 |
|
|
##-----------------------------------------------------------------------------
|
| 836 |
|
|
|
| 837 |
|
|
.data
|
| 838 |
|
|
hal_diag_data
|
| 839 |
|
|
|
| 840 |
|
|
##-----------------------------------------------------------------------------
|
| 841 |
|
|
## end of vectors.S
|
| 842 |
|
|
|
