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#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
##      platform.inc
##
##      ASB2303 board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   dmoseley
## Contributors:dmoseley
## Date:        2000-08-11
## Purpose:     ASB board definitions.
## Description: This file contains various definitions and macros that are
##              useful for writing assembly code for the ASB board.
## Usage:
##              #include 
##              ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
 
#------------------------------------------------------------------------------
# Diagnostics macros.
 
#include 
 
        .macro  hal_diag_data
        .globl  hal_diag_led_state
hal_diag_led_state:     .long   0xffffffff
hal_diag_intr_count:    .long   0
        .endm
 
#define HAL_EARLY_INIT hal_led_init
.macro hal_led_init
        # Setup Port 0 as all output
        # Do this the very first thing so we have LED debugging available early
        mov     HAL_GPIO_MODE_ALL_OUTPUT,d0
        mov     HAL_GPIO_0_MODE,a0
        mov     d0,(a0)
.endm
 
        .macro  hal_diag_init
        hal_led_init
        jmp     1f
 
hal_diag_digits:
        .byte   0x81    # 0
        .byte   0xf3    # 1
        .byte   0x49    # 2
        .byte   0x61    # 3
        .byte   0x33    # 4
        .byte   0x25    # 5
        .byte   0x05    # 6
        .byte   0xf1    # 7
        .byte   0x01    # 8
        .byte   0x21    # 9
        .byte   0x11    # A
        .byte   0x07    # B
        .byte   0x8d    # C
        .byte   0x43    # D
        .byte   0x0d    # E
        .byte   0x1d    # F
 
hal_diag_hex_digits:
        .ascii  "0123456789ABCDEF"
 
1:
        hal_diag_led 0
        .endm
 
        .macro  hal_diag_excpt_start
        mov     HAL_LED_ADDRESS,a0
        mov     (a0),d0
        xor     0x01000000,d0
        mov     d0,(a0)
        .endm
 
        .macro  hal_diag_intr_start
        mov     (hal_diag_intr_count),d1
        inc     d1
        cmp     100,d1
        bne     x\@
        clr     d1
        mov     HAL_LED_ADDRESS,a0
        mov     (a0),d0
        xor     0x00010000,d0
        mov     d0,(a0)
x\@:
        mov     d1,(hal_diag_intr_count)
        .endm
 
        .macro  hal_diag_restore
        mov     (hal_diag_intr_count),d0
        and     0x1000,d0
        beq     x\@
        mov     HAL_LED_ADDRESS,a0
        mov     (a0),d0
        and     0xfffeffff,d0
        mov     d0,(a0)
x\@:
        .endm
 
        .macro  hal_diag_led val
        movm    [d2,d3,a2],(sp)
0:      mov     hal_diag_digits,a2
        mov     \val,d2
        and     0xf,d2
        add     d2,a2
        movbu   (a2),d3
        mov     HAL_LED_ADDRESS,a2
        mov     (a2),d2
        asl     8,d2
        or      d3,d2
        mov     d2,(a2)
        movm    (sp),[d2,d3,a2]
        .endm
 
#define CYGPKG_HAL_MN10300_DIAG_DEFINED
 
#------------------------------------------------------------------------------
# MEMC macros.
 
#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
 
// These settings follow the recommended settings in the
// "MN103E010 Evaluation Board User's Guide"
 
#define BCCR                    0xC0002000
#define BCCR_INIT               0x12040580
 
#define SBBASE0                 0xD8C00100
#define SBBASE1                 0xD8C00110
#define SBBASE2                 0xD8C00120
#define SBBASE3                 0xD8C00130
#define SBBASE4                 0xD8C00140
#define SBBASE5                 0xD8C00150
#define SBBASE6                 0xD8C00160
#define SBBASE7                 0xD8C00170
 
#define SBBASE0_INIT_SYSFL      0x8000FE01
#define SBBASE0_INIT_BPROM      0x8400FE01
#define SBBASE1_INIT_SYSFL      0x8400FE01
#define SBBASE1_INIT_BPROM      0x8000FE01
#define SBBASE2_INIT            0x8600FF81
#define SBBASE3_INIT            0x00000000
#define SBBASE4_INIT            0x00000000
#define SBBASE5_INIT            0x00000000
#define SBBASE6_INIT            0x00000000
#define SBBASE7_INIT            0x00000000
 
#define SBCTRL00                0xD8C00200
#define SBCTRL10                0xD8C00210
#define SBCTRL20                0xD8C00220
#define SBCTRL30                0xD8C00230
#define SBCTRL40                0xD8C00240
#define SBCTRL50                0xD8C00250
#define SBCTRL60                0xD8C00260
#define SBCTRL70                0xD8C00270
 
#define SBCTRL00_INIT           0x21111000
#define SBCTRL10_INIT           0x21111000
#define SBCTRL20_INIT           0x21111000
#define SBCTRL30_INIT           0x00000000
#define SBCTRL40_INIT           0x00000000
#define SBCTRL50_INIT           0x00000000 // 0x21111100
#define SBCTRL60_INIT           0x00000000 // 0x11110000
#define SBCTRL70_INIT           0x00000000
 
#define SBCTRL01                0xD8C00204
#define SBCTRL11                0xD8C00214
#define SBCTRL21                0xD8C00224
#define SBCTRL31                0xD8C00234
#define SBCTRL41                0xD8C00244
#define SBCTRL51                0xD8C00254
#define SBCTRL61                0xD8C00264
#define SBCTRL71                0xD8C00274
 
#define SBCTRL01_INIT           0x00100200
#define SBCTRL11_INIT           0x00100200
#define SBCTRL21_INIT           0x00100200
#define SBCTRL31_INIT           0x00000000
#define SBCTRL41_INIT           0x00000000
#define SBCTRL51_INIT           0x00000000
#define SBCTRL61_INIT           0x00000000
#define SBCTRL71_INIT           0x00000000
 
#define SBCTRL02                0xD8C00208
#define SBCTRL12                0xD8C00218
#define SBCTRL22                0xD8C00228
#define SBCTRL32                0xD8C00238
#define SBCTRL42                0xD8C00248
#define SBCTRL52                0xD8C00258
#define SBCTRL62                0xD8C00268
#define SBCTRL72                0xD8C00278
 
#define SBCTRL02_INIT           0x00000004
#define SBCTRL12_INIT           0x04000004
#define SBCTRL22_INIT           0x00000004
#define SBCTRL32_INIT           0x00000000
#define SBCTRL42_INIT           0x00000000
#define SBCTRL52_INIT           0x00000000
#define SBCTRL62_INIT           0x00000000
#define SBCTRL72_INIT           0x00000000
 
#define SDBASE0                 0xDA000008
#define SDBASE1                 0xDA00000C
#define SDRAMBUS                0xDA000000
 
// 16MB SDRAM
#define SDBASE0_8M_INIT         0x9000FF81
#define SDBASE1_8M_INIT         0x9080FF81
#define SDRAMBUS_8M_INIT        0xA8990654
 
// 32MB SDRAM
#define SDBASE0_16M_INIT        0x9000FF01
#define SDBASE1_16M_INIT        0x9100FF01
#define SDRAMBUS_16M_INIT       0xA89a0654
 
// 64MB SDRAM
#define SDBASE0_32M_INIT        0x9000fe01
#define SDBASE1_32M_INIT        0x9200fe01
#define SDRAMBUS_32M_INIT       0xa89b0654
 
        .macro  hal_memc_init
        mov     BCCR,a0
        mov     BCCR_INIT,d0
        mov     d0,(a0)
 
        // reduce the span of the ROM banks first
        mov     (SBBASE0),d0
        btst    1,d0
        beq     0f
        mov     0x8000FE01,d0
        mov     d0,(SBBASE0)
0:
        mov     (SBBASE1),d0
        btst    1,d0
        beq     0f
        mov     0x8000FE01,d0
        mov     d0,(SBBASE1)
0:
 
        mov     SBBASE2,a0
        mov     SBBASE2_INIT,d0
        mov     d0,(a0)
 
        mov     SBBASE3,a0
        mov     SBBASE3_INIT,d0
        mov     d0,(a0)
 
        mov     SBBASE4,a0
        mov     SBBASE4_INIT,d0
        mov     d0,(a0)
 
        mov     SBBASE5,a0
        mov     SBBASE5_INIT,d0
        mov     d0,(a0)
 
        mov     SBBASE6,a0
        mov     SBBASE6_INIT,d0
        mov     d0,(a0)
 
        mov     SBBASE7,a0
        mov     SBBASE7_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL00,a0
        mov     SBCTRL00_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL10,a0
        mov     SBCTRL10_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL20,a0
        mov     SBCTRL20_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL30,a0
        mov     SBCTRL30_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL40,a0
        mov     SBCTRL40_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL50,a0
        mov     SBCTRL50_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL60,a0
        mov     SBCTRL60_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL70,a0
        mov     SBCTRL70_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL01,a0
        mov     SBCTRL01_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL11,a0
        mov     SBCTRL11_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL21,a0
        mov     SBCTRL21_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL31,a0
        mov     SBCTRL31_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL41,a0
        mov     SBCTRL41_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL51,a0
        mov     SBCTRL51_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL61,a0
        mov     SBCTRL61_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL71,a0
        mov     SBCTRL71_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL02,a0
        mov     SBCTRL02_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL12,a0
        mov     SBCTRL12_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL22,a0
        mov     SBCTRL22_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL32,a0
        mov     SBCTRL32_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL42,a0
        mov     SBCTRL42_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL52,a0
        mov     SBCTRL52_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL62,a0
        mov     SBCTRL62_INIT,d0
        mov     d0,(a0)
 
        mov     SBCTRL72,a0
        mov     SBCTRL72_INIT,d0
        mov     d0,(a0)
 
#ifndef CYG_HAL_STARTUP_RAM
 
        // Setup for 64MB initially and determine final mem config below.
        mov     SDRAMBUS,a0
        mov     (a0),d0
        and     0xfffffffb,d0  // disable refresh
        mov     d0,(a0)
 
        mov     SDBASE0,a0
        mov     SDBASE0_32M_INIT,d0
        mov     d0,(a0)
        mov     SDBASE1,a0
        mov     SDBASE1_32M_INIT,d0
        mov     d0,(a0)
        mov     SDRAMBUS,a0
        mov     SDRAMBUS_32M_INIT,d0
        mov     d0,(a0)
 
        mov     0x1000,d0
0:
        sub     1,d0
        bne     0b
 
        // Check for 16MB and 32MB shadowing to determine actual amount of
        // memory installed. This assumes 2x8M, 2x16M, or 2x32M configs.
        mov     0,d0
        mov     d0,(0x90800000)
        mov     d0,(0x91000000)
        mov     0xaaaaaaaa,d0
        mov     d0,(0x90000000)
        mov     (0x90800000),d1
        cmp     d0,d1
        bne     1f
 
        // 16MB installed
        mov     SDRAMBUS,a0
        mov     (a0),d0
        and     0xfffffffb,d0  // disable refresh
        mov     d0,(a0)
        mov     SDBASE0,a1
        mov     SDBASE0_8M_INIT,d1
        mov     d1,(a1)
        mov     SDBASE1,a1
        mov     SDBASE1_8M_INIT,d1
        mov     d1,(a1)
        mov     SDRAMBUS_8M_INIT,d0
        mov     d0,(a0)
        jmp     2f
1:
        mov     (0x91000000),d1
        cmp     d0,d1
        bne     2f
 
        // 32MB installed
        mov     SDRAMBUS,a0
        mov     (a0),d0
        and     0xfffffffb,d0  // disable refresh
        mov     d0,(a0)
        mov     SDBASE0,a1
        mov     SDBASE0_16M_INIT,d1
        mov     d1,(a1)
        mov     SDBASE1,a1
        mov     SDBASE1_16M_INIT,d1
        mov     d1,(a1)
        mov     SDRAMBUS_16M_INIT,d0
        mov     d0,(a0)
2:
#endif // ! CYG_HAL_STARTUP_RAM
 
        // now the ROMs need putting into the right place
        // - this is tricky because when we're booting from the system flash,
        //   it has had its base address pre-swapped by the CPU
        // - we need to copy a small piece of code to the SRAM and execute it
        //   there
 
        // copy the ROM address adjustor to the SRAM
__hal_plf_base_ref:
        mov     pc,a3
        mov     a3,a0
        add     __hal_plf_rom_swap_start-__hal_plf_base_ref,a0
        add     __hal_plf_rom_swap_end-__hal_plf_base_ref,a3
        mov     0x8C000000,a1
0:      movbu   (a0),d0
        movbu   d0,(a1)
        inc     a0
        inc     a1
        cmp     a0,a3
        bcc     0b
        mov     0x8C000000,a1
        jmp     (a1)
 
        ////////////////////////////////////////////////////////////////
__hal_plf_rom_swap_start:
        // put boot PROM at 0x80000000, and system flash at 0x84000000
        mov     SBBASE0_INIT_BPROM,d0
        mov     d0,(SBBASE0)
 
        mov     SBBASE1_INIT_BPROM,d0
        mov     d0,(SBBASE1)
 
        // memory bank 0
        mov     SBCTRL00_INIT,d0
        mov     d0,(SBCTRL00)
        mov     SBCTRL01_INIT,d0
        mov     d0,(SBCTRL01)
        mov     SBCTRL02_INIT,d0
        mov     d0,(SBCTRL02)
 
        // memory bank 1
        mov     SBCTRL10_INIT,d0
        mov     d0,(SBCTRL10)
        mov     SBCTRL11_INIT,d0
        mov     d0,(SBCTRL11)
        mov     SBCTRL12_INIT,d0
        mov     d0,(SBCTRL12)
 
        // jump forward so we start running from the 80000000/84000000 base address
        mov     __hal_plf_rom_swap_reentry,a0
        jmp     (a0)
__hal_plf_rom_swap_end:
        ////////////////////////////////////////////////////////////////
 
__hal_plf_rom_swap_reentry:
        // clear the on-CPU 16Kb SRAM
        clr     d0
        mov     16384/4-4,d1
        mov     0x8C000000,a0
0:
        mov     d0,(a0,d1)
        sub     4,d1
        bnc     0b
 
        .endm
 
#define CYGPKG_HAL_MN10300_MEMC_DEFINED
 
#endif
 
 
//-----------------------------------------------------------------------------
// Syscall support.
// RedBoot provides syscall handling for this board
// These must be kept in sync with the rest of the tree.
#define SIGSYS     12
#define SIGSYSCALL SIGSYS
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [asb/] [v2_0/] [include/] [platform.inc] - Blame information for rev 174

Line No.	Rev	Author	Line
1	27	unneback	`#ifndef CYGONCE_HAL_PLATFORM_INC`
2			`#define CYGONCE_HAL_PLATFORM_INC`
3			`##=============================================================================`
4			`##`
5			`## platform.inc`
6			`##`
7			`## ASB2303 board assembler header file`
8			`##`
9			`##=============================================================================`
10			`#####ECOSGPLCOPYRIGHTBEGIN####`
11			`## -------------------------------------------`
12			`## This file is part of eCos, the Embedded Configurable Operating System.`
13			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
14			`##`
15			`## eCos is free software; you can redistribute it and/or modify it under`
16			`## the terms of the GNU General Public License as published by the Free`
17			`## Software Foundation; either version 2 or (at your option) any later version.`
18			`##`
19			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
20			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
21			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
22			`## for more details.`
23			`##`
24			`## You should have received a copy of the GNU General Public License along`
25			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
26			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
27			`##`
28			`## As a special exception, if other files instantiate templates or use macros`
29			`## or inline functions from this file, or you compile this file and link it`
30			`## with other works to produce a work based on this file, this file does not`
31			`## by itself cause the resulting work to be covered by the GNU General Public`
32			`## License. However the source code for this file must still be made available`
33			`## in accordance with section (3) of the GNU General Public License.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based on`
36			`## this file might be covered by the GNU General Public License.`
37			`##`
38			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
39			`## at http://sources.redhat.com/ecos/ecos-license/`
40			`## -------------------------------------------`
41			`#####ECOSGPLCOPYRIGHTEND####`
42			`##=============================================================================`
43			`#######DESCRIPTIONBEGIN####`
44			`##`
45			`## Author(s): dmoseley`
46			`## Contributors:dmoseley`
47			`## Date: 2000-08-11`
48			`## Purpose: ASB board definitions.`
49			`## Description: This file contains various definitions and macros that are`
50			`## useful for writing assembly code for the ASB board.`
51			`## Usage:`
52			`## #include`
53			`## ...`
54			`##`
55			`##`
56			`######DESCRIPTIONEND####`
57			`##`
58			`##=============================================================================`
59
60			`#include`
61			`#include`
62
63			`#------------------------------------------------------------------------------`
64			`# Diagnostics macros.`
65
66			`#include`
67
68			`.macro hal_diag_data`
69			`.globl hal_diag_led_state`
70			`hal_diag_led_state: .long 0xffffffff`
71			`hal_diag_intr_count: .long 0`
72			`.endm`
73
74			`#define HAL_EARLY_INIT hal_led_init`
75			`.macro hal_led_init`
76			`# Setup Port 0 as all output`
77			`# Do this the very first thing so we have LED debugging available early`
78			`mov HAL_GPIO_MODE_ALL_OUTPUT,d0`
79			`mov HAL_GPIO_0_MODE,a0`
80			`mov d0,(a0)`
81			`.endm`
82
83			`.macro hal_diag_init`
84			`hal_led_init`
85			`jmp 1f`
86
87			`hal_diag_digits:`
88			`.byte 0x81 # 0`
89			`.byte 0xf3 # 1`
90			`.byte 0x49 # 2`
91			`.byte 0x61 # 3`
92			`.byte 0x33 # 4`
93			`.byte 0x25 # 5`
94			`.byte 0x05 # 6`
95			`.byte 0xf1 # 7`
96			`.byte 0x01 # 8`
97			`.byte 0x21 # 9`
98			`.byte 0x11 # A`
99			`.byte 0x07 # B`
100			`.byte 0x8d # C`
101			`.byte 0x43 # D`
102			`.byte 0x0d # E`
103			`.byte 0x1d # F`
104
105			`hal_diag_hex_digits:`
106			`.ascii "0123456789ABCDEF"`
107
108			`1:`
109			`hal_diag_led 0`
110			`.endm`
111
112			`.macro hal_diag_excpt_start`
113			`mov HAL_LED_ADDRESS,a0`
114			`mov (a0),d0`
115			`xor 0x01000000,d0`
116			`mov d0,(a0)`
117			`.endm`
118
119			`.macro hal_diag_intr_start`
120			`mov (hal_diag_intr_count),d1`
121			`inc d1`
122			`cmp 100,d1`
123			`bne x\@`
124			`clr d1`
125			`mov HAL_LED_ADDRESS,a0`
126			`mov (a0),d0`
127			`xor 0x00010000,d0`
128			`mov d0,(a0)`
129			`x\@:`
130			`mov d1,(hal_diag_intr_count)`
131			`.endm`
132
133			`.macro hal_diag_restore`
134			`mov (hal_diag_intr_count),d0`
135			`and 0x1000,d0`
136			`beq x\@`
137			`mov HAL_LED_ADDRESS,a0`
138			`mov (a0),d0`
139			`and 0xfffeffff,d0`
140			`mov d0,(a0)`
141			`x\@:`
142			`.endm`
143
144			`.macro hal_diag_led val`
145			`movm [d2,d3,a2],(sp)`
146			`0: mov hal_diag_digits,a2`
147			`mov \val,d2`
148			`and 0xf,d2`
149			`add d2,a2`
150			`movbu (a2),d3`
151			`mov HAL_LED_ADDRESS,a2`
152			`mov (a2),d2`
153			`asl 8,d2`
154			`or d3,d2`
155			`mov d2,(a2)`
156			`movm (sp),[d2,d3,a2]`
157			`.endm`
158
159			`#define CYGPKG_HAL_MN10300_DIAG_DEFINED`
160
161			`#------------------------------------------------------------------------------`
162			`# MEMC macros.`
163
164			`#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED`
165
166			`// These settings follow the recommended settings in the`
167			`// "MN103E010 Evaluation Board User's Guide"`
168
169			`#define BCCR 0xC0002000`
170			`#define BCCR_INIT 0x12040580`
171
172			`#define SBBASE0 0xD8C00100`
173			`#define SBBASE1 0xD8C00110`
174			`#define SBBASE2 0xD8C00120`
175			`#define SBBASE3 0xD8C00130`
176			`#define SBBASE4 0xD8C00140`
177			`#define SBBASE5 0xD8C00150`
178			`#define SBBASE6 0xD8C00160`
179			`#define SBBASE7 0xD8C00170`
180
181			`#define SBBASE0_INIT_SYSFL 0x8000FE01`
182			`#define SBBASE0_INIT_BPROM 0x8400FE01`
183			`#define SBBASE1_INIT_SYSFL 0x8400FE01`
184			`#define SBBASE1_INIT_BPROM 0x8000FE01`
185			`#define SBBASE2_INIT 0x8600FF81`
186			`#define SBBASE3_INIT 0x00000000`
187			`#define SBBASE4_INIT 0x00000000`
188			`#define SBBASE5_INIT 0x00000000`
189			`#define SBBASE6_INIT 0x00000000`
190			`#define SBBASE7_INIT 0x00000000`
191
192			`#define SBCTRL00 0xD8C00200`
193			`#define SBCTRL10 0xD8C00210`
194			`#define SBCTRL20 0xD8C00220`
195			`#define SBCTRL30 0xD8C00230`
196			`#define SBCTRL40 0xD8C00240`
197			`#define SBCTRL50 0xD8C00250`
198			`#define SBCTRL60 0xD8C00260`
199			`#define SBCTRL70 0xD8C00270`
200
201			`#define SBCTRL00_INIT 0x21111000`
202			`#define SBCTRL10_INIT 0x21111000`
203			`#define SBCTRL20_INIT 0x21111000`
204			`#define SBCTRL30_INIT 0x00000000`
205			`#define SBCTRL40_INIT 0x00000000`
206			`#define SBCTRL50_INIT 0x00000000 // 0x21111100`
207			`#define SBCTRL60_INIT 0x00000000 // 0x11110000`
208			`#define SBCTRL70_INIT 0x00000000`
209
210			`#define SBCTRL01 0xD8C00204`
211			`#define SBCTRL11 0xD8C00214`
212			`#define SBCTRL21 0xD8C00224`
213			`#define SBCTRL31 0xD8C00234`
214			`#define SBCTRL41 0xD8C00244`
215			`#define SBCTRL51 0xD8C00254`
216			`#define SBCTRL61 0xD8C00264`
217			`#define SBCTRL71 0xD8C00274`
218
219			`#define SBCTRL01_INIT 0x00100200`
220			`#define SBCTRL11_INIT 0x00100200`
221			`#define SBCTRL21_INIT 0x00100200`
222			`#define SBCTRL31_INIT 0x00000000`
223			`#define SBCTRL41_INIT 0x00000000`
224			`#define SBCTRL51_INIT 0x00000000`
225			`#define SBCTRL61_INIT 0x00000000`
226			`#define SBCTRL71_INIT 0x00000000`
227
228			`#define SBCTRL02 0xD8C00208`
229			`#define SBCTRL12 0xD8C00218`
230			`#define SBCTRL22 0xD8C00228`
231			`#define SBCTRL32 0xD8C00238`
232			`#define SBCTRL42 0xD8C00248`
233			`#define SBCTRL52 0xD8C00258`
234			`#define SBCTRL62 0xD8C00268`
235			`#define SBCTRL72 0xD8C00278`
236
237			`#define SBCTRL02_INIT 0x00000004`
238			`#define SBCTRL12_INIT 0x04000004`
239			`#define SBCTRL22_INIT 0x00000004`
240			`#define SBCTRL32_INIT 0x00000000`
241			`#define SBCTRL42_INIT 0x00000000`
242			`#define SBCTRL52_INIT 0x00000000`
243			`#define SBCTRL62_INIT 0x00000000`
244			`#define SBCTRL72_INIT 0x00000000`
245
246			`#define SDBASE0 0xDA000008`
247			`#define SDBASE1 0xDA00000C`
248			`#define SDRAMBUS 0xDA000000`
249
250			`// 16MB SDRAM`
251			`#define SDBASE0_8M_INIT 0x9000FF81`
252			`#define SDBASE1_8M_INIT 0x9080FF81`
253			`#define SDRAMBUS_8M_INIT 0xA8990654`
254
255			`// 32MB SDRAM`
256			`#define SDBASE0_16M_INIT 0x9000FF01`
257			`#define SDBASE1_16M_INIT 0x9100FF01`
258			`#define SDRAMBUS_16M_INIT 0xA89a0654`
259
260			`// 64MB SDRAM`
261			`#define SDBASE0_32M_INIT 0x9000fe01`
262			`#define SDBASE1_32M_INIT 0x9200fe01`
263			`#define SDRAMBUS_32M_INIT 0xa89b0654`
264
265			`.macro hal_memc_init`
266			`mov BCCR,a0`
267			`mov BCCR_INIT,d0`
268			`mov d0,(a0)`
269
270			`// reduce the span of the ROM banks first`
271			`mov (SBBASE0),d0`
272			`btst 1,d0`
273			`beq 0f`
274			`mov 0x8000FE01,d0`
275			`mov d0,(SBBASE0)`
276			`0:`
277			`mov (SBBASE1),d0`
278			`btst 1,d0`
279			`beq 0f`
280			`mov 0x8000FE01,d0`
281			`mov d0,(SBBASE1)`
282			`0:`
283
284			`mov SBBASE2,a0`
285			`mov SBBASE2_INIT,d0`
286			`mov d0,(a0)`
287
288			`mov SBBASE3,a0`
289			`mov SBBASE3_INIT,d0`
290			`mov d0,(a0)`
291
292			`mov SBBASE4,a0`
293			`mov SBBASE4_INIT,d0`
294			`mov d0,(a0)`
295
296			`mov SBBASE5,a0`
297			`mov SBBASE5_INIT,d0`
298			`mov d0,(a0)`
299
300			`mov SBBASE6,a0`
301			`mov SBBASE6_INIT,d0`
302			`mov d0,(a0)`
303
304			`mov SBBASE7,a0`
305			`mov SBBASE7_INIT,d0`
306			`mov d0,(a0)`
307
308			`mov SBCTRL00,a0`
309			`mov SBCTRL00_INIT,d0`
310			`mov d0,(a0)`
311
312			`mov SBCTRL10,a0`
313			`mov SBCTRL10_INIT,d0`
314			`mov d0,(a0)`
315
316			`mov SBCTRL20,a0`
317			`mov SBCTRL20_INIT,d0`
318			`mov d0,(a0)`
319
320			`mov SBCTRL30,a0`
321			`mov SBCTRL30_INIT,d0`
322			`mov d0,(a0)`
323
324			`mov SBCTRL40,a0`
325			`mov SBCTRL40_INIT,d0`
326			`mov d0,(a0)`
327
328			`mov SBCTRL50,a0`
329			`mov SBCTRL50_INIT,d0`
330			`mov d0,(a0)`
331
332			`mov SBCTRL60,a0`
333			`mov SBCTRL60_INIT,d0`
334			`mov d0,(a0)`
335
336			`mov SBCTRL70,a0`
337			`mov SBCTRL70_INIT,d0`
338			`mov d0,(a0)`
339
340			`mov SBCTRL01,a0`
341			`mov SBCTRL01_INIT,d0`
342			`mov d0,(a0)`
343
344			`mov SBCTRL11,a0`
345			`mov SBCTRL11_INIT,d0`
346			`mov d0,(a0)`
347
348			`mov SBCTRL21,a0`
349			`mov SBCTRL21_INIT,d0`
350			`mov d0,(a0)`
351
352			`mov SBCTRL31,a0`
353			`mov SBCTRL31_INIT,d0`
354			`mov d0,(a0)`
355
356			`mov SBCTRL41,a0`
357			`mov SBCTRL41_INIT,d0`
358			`mov d0,(a0)`
359
360			`mov SBCTRL51,a0`
361			`mov SBCTRL51_INIT,d0`
362			`mov d0,(a0)`
363
364			`mov SBCTRL61,a0`
365			`mov SBCTRL61_INIT,d0`
366			`mov d0,(a0)`
367
368			`mov SBCTRL71,a0`
369			`mov SBCTRL71_INIT,d0`
370			`mov d0,(a0)`
371
372			`mov SBCTRL02,a0`
373			`mov SBCTRL02_INIT,d0`
374			`mov d0,(a0)`
375
376			`mov SBCTRL12,a0`
377			`mov SBCTRL12_INIT,d0`
378			`mov d0,(a0)`
379
380			`mov SBCTRL22,a0`
381			`mov SBCTRL22_INIT,d0`
382			`mov d0,(a0)`
383
384			`mov SBCTRL32,a0`
385			`mov SBCTRL32_INIT,d0`
386			`mov d0,(a0)`
387
388			`mov SBCTRL42,a0`
389			`mov SBCTRL42_INIT,d0`
390			`mov d0,(a0)`
391
392			`mov SBCTRL52,a0`
393			`mov SBCTRL52_INIT,d0`
394			`mov d0,(a0)`
395
396			`mov SBCTRL62,a0`
397			`mov SBCTRL62_INIT,d0`
398			`mov d0,(a0)`
399
400			`mov SBCTRL72,a0`
401			`mov SBCTRL72_INIT,d0`
402			`mov d0,(a0)`
403
404			`#ifndef CYG_HAL_STARTUP_RAM`
405
406			`// Setup for 64MB initially and determine final mem config below.`
407			`mov SDRAMBUS,a0`
408			`mov (a0),d0`
409			`and 0xfffffffb,d0 // disable refresh`
410			`mov d0,(a0)`
411
412			`mov SDBASE0,a0`
413			`mov SDBASE0_32M_INIT,d0`
414			`mov d0,(a0)`
415			`mov SDBASE1,a0`
416			`mov SDBASE1_32M_INIT,d0`
417			`mov d0,(a0)`
418			`mov SDRAMBUS,a0`
419			`mov SDRAMBUS_32M_INIT,d0`
420			`mov d0,(a0)`
421
422			`mov 0x1000,d0`
423			`0:`
424			`sub 1,d0`
425			`bne 0b`
426
427			`// Check for 16MB and 32MB shadowing to determine actual amount of`
428			`// memory installed. This assumes 2x8M, 2x16M, or 2x32M configs.`
429			`mov 0,d0`
430			`mov d0,(0x90800000)`
431			`mov d0,(0x91000000)`
432			`mov 0xaaaaaaaa,d0`
433			`mov d0,(0x90000000)`
434			`mov (0x90800000),d1`
435			`cmp d0,d1`
436			`bne 1f`
437
438			`// 16MB installed`
439			`mov SDRAMBUS,a0`
440			`mov (a0),d0`
441			`and 0xfffffffb,d0 // disable refresh`
442			`mov d0,(a0)`
443			`mov SDBASE0,a1`
444			`mov SDBASE0_8M_INIT,d1`
445			`mov d1,(a1)`
446			`mov SDBASE1,a1`
447			`mov SDBASE1_8M_INIT,d1`
448			`mov d1,(a1)`
449			`mov SDRAMBUS_8M_INIT,d0`
450			`mov d0,(a0)`
451			`jmp 2f`
452			`1:`
453			`mov (0x91000000),d1`
454			`cmp d0,d1`
455			`bne 2f`
456
457			`// 32MB installed`
458			`mov SDRAMBUS,a0`
459			`mov (a0),d0`
460			`and 0xfffffffb,d0 // disable refresh`
461			`mov d0,(a0)`
462			`mov SDBASE0,a1`
463			`mov SDBASE0_16M_INIT,d1`
464			`mov d1,(a1)`
465			`mov SDBASE1,a1`
466			`mov SDBASE1_16M_INIT,d1`
467			`mov d1,(a1)`
468			`mov SDRAMBUS_16M_INIT,d0`
469			`mov d0,(a0)`
470			`2:`
471			`#endif // ! CYG_HAL_STARTUP_RAM`
472
473			`// now the ROMs need putting into the right place`
474			`// - this is tricky because when we're booting from the system flash,`
475			`// it has had its base address pre-swapped by the CPU`
476			`// - we need to copy a small piece of code to the SRAM and execute it`
477			`// there`
478
479			`// copy the ROM address adjustor to the SRAM`
480			`__hal_plf_base_ref:`
481			`mov pc,a3`
482			`mov a3,a0`
483			`add __hal_plf_rom_swap_start-__hal_plf_base_ref,a0`
484			`add __hal_plf_rom_swap_end-__hal_plf_base_ref,a3`
485			`mov 0x8C000000,a1`
486			`0: movbu (a0),d0`
487			`movbu d0,(a1)`
488			`inc a0`
489			`inc a1`
490			`cmp a0,a3`
491			`bcc 0b`
492			`mov 0x8C000000,a1`
493			`jmp (a1)`
494
495			`////////////////////////////////////////////////////////////////`
496			`__hal_plf_rom_swap_start:`
497			`// put boot PROM at 0x80000000, and system flash at 0x84000000`
498			`mov SBBASE0_INIT_BPROM,d0`
499			`mov d0,(SBBASE0)`
500
501			`mov SBBASE1_INIT_BPROM,d0`
502			`mov d0,(SBBASE1)`
503
504			`// memory bank 0`
505			`mov SBCTRL00_INIT,d0`
506			`mov d0,(SBCTRL00)`
507			`mov SBCTRL01_INIT,d0`
508			`mov d0,(SBCTRL01)`
509			`mov SBCTRL02_INIT,d0`
510			`mov d0,(SBCTRL02)`
511
512			`// memory bank 1`
513			`mov SBCTRL10_INIT,d0`
514			`mov d0,(SBCTRL10)`
515			`mov SBCTRL11_INIT,d0`
516			`mov d0,(SBCTRL11)`
517			`mov SBCTRL12_INIT,d0`
518			`mov d0,(SBCTRL12)`
519
520			`// jump forward so we start running from the 80000000/84000000 base address`
521			`mov __hal_plf_rom_swap_reentry,a0`
522			`jmp (a0)`
523			`__hal_plf_rom_swap_end:`
524			`////////////////////////////////////////////////////////////////`
525
526			`__hal_plf_rom_swap_reentry:`
527			`// clear the on-CPU 16Kb SRAM`
528			`clr d0`
529			`mov 16384/4-4,d1`
530			`mov 0x8C000000,a0`
531			`0:`
532			`mov d0,(a0,d1)`
533			`sub 4,d1`
534			`bnc 0b`
535
536			`.endm`
537
538			`#define CYGPKG_HAL_MN10300_MEMC_DEFINED`
539
540			`#endif`
541
542
543			`//-----------------------------------------------------------------------------`
544			`// Syscall support.`
545			`// RedBoot provides syscall handling for this board`
546			`// These must be kept in sync with the rest of the tree.`
547			`#define SIGSYS 12`
548			`#define SIGSYSCALL SIGSYS`
549
550			`#------------------------------------------------------------------------------`
551			`#endif // ifndef CYGONCE_HAL_PLATFORM_INC`
552			`# end of platform.inc`