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#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##
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## platform.inc
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##
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## ASB2305 board assembler header file
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##
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##=============================================================================
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#####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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##
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## As a special exception, if other files instantiate templates or use macros
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## or inline functions from this file, or you compile this file and link it
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## with other works to produce a work based on this file, this file does not
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## by itself cause the resulting work to be covered by the GNU General Public
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## License. However the source code for this file must still be made available
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## in accordance with section (3) of the GNU General Public License.
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##
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## This exception does not invalidate any other reasons why a work based on
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## this file might be covered by the GNU General Public License.
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##
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## at http://sources.redhat.com/ecos/ecos-license/
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## -------------------------------------------
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#####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): dhowells
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## Contributors:dmoseley
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## Date: 2001-05-17
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## Purpose: ASB2305 board definitions.
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the ASB2305 board.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#------------------------------------------------------------------------------
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# Diagnostics macros.
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#include
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.macro hal_diag_data
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hal_diag_intr_count: .long 0
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.endm
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#define HAL_EARLY_INIT hal_early_init
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.macro hal_early_init
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# turn on the sofware status LED
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movbu (0xDB000008),d0
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or 0x80,d0
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movbu d0,(0xDB000008)
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movhu (0xDB000000),d0
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and 0x3FFF,d0
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or 0x4000,d0
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movhu d0,(0xDB000000)
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# enable system flash memory write
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movbu (0xDB000008),d0
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and 0xdf,d0
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movbu d0,(0xDB000008)
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movhu (0xDB000000),d0
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and 0xF3FF,d0
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or 0x0400,d0
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movhu d0,(0xDB000000)
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.endm
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.macro hal_diag_init
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mov 0x5f17ff7f,d0 # 'rh -'
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mov d0,(_hal_led_old_display)
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mov d0,(HAL_LED_ADDRESS)
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.endm
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#define CYGPKG_HAL_MN10300_DIAG_DEFINED
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.macro hal_handle_unknown_int
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mov _hal_diag_digits,a2
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mov (0xC0000024),d0 // Get TBR
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mov 0x6D00,d1 // 7-seg LED: =ABC
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mov d0,d2 // 0xnnnnnAnn
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lsr 8,d2
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and 0xf,d2
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movbu (a2,d2),d2
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or d2,d1
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asl 8,d1
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mov d0,d2 // 0xnnnnnnBn
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lsr 4,d2
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and 0xf,d2
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movbu (a2,d2),d2
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or d2,d1
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asl 8,d1
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and 0xf,d0 // 0xnnnnnnnC
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movbu (a2,d0),d2
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or d2,d1
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mov (_hal_led_old_display),d0
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and 0x00010000,d0
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or d1,d0
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mov d0,(_hal_led_old_display)
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mov d0,(HAL_LED_ADDRESS)
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.endm
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#define CYG_HAL_HANDLE_UNKNOWN_INT_DEFINED
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.macro hal_diag_excpt_start
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hal_handle_unknown_int
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.endm
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.macro hal_diag_excpt_end
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mov 0x5f17ff01,d0
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mov d0,(_hal_led_old_display)
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mov d0,(HAL_LED_ADDRESS)
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.endm
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#define CYG_HAL_DIAG_EXCPT_END
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.macro hal_diag_intr_start
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mov (hal_diag_intr_count),d1
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inc d1
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cmp 100,d1
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bne x\@
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clr d1
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mov (_hal_led_old_display),d0
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xor 0x00010000,d0
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mov d0,(_hal_led_old_display)
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mov d0,(HAL_LED_ADDRESS)
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x\@:
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mov d1,(hal_diag_intr_count)
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.endm
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.macro hal_diag_restore
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.endm
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.macro hal_diag_led val
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movm [d2,d3,a2],(sp)
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0: mov _hal_diag_digits,a2
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mov \val,d2
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and 0xf,d2
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add d2,a2
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movbu (a2),d3
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mov (_hal_led_old_display),d2
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asl 8,d2
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or d3,d2
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mov d2,(HAL_LED_ADDRESS)
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mov d2,(_hal_led_old_display)
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movm (sp),[d2,d3,a2]
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.endm
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.macro hal_cpu_stop
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// mov 0x10,d0
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// movhu d0,(0xC0000040) // enter STOP mode (register CPUM)
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.endm
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#define CYG_HAL_CPU_STOP_DEFINED
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#------------------------------------------------------------------------------
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# MEMC macros.
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#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
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// These settings follow the recommended settings in the
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// "MN103E010 Evaluation Board User's Guide"
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#define BCCR 0xC0002000
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#define BCCR_INIT 0x12040580
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#define SBBASE0 0xD8C00100
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#define SBBASE0_INIT_SYSFL 0x8000FE01
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#define SBBASE0_INIT_BPROM 0x8400FE01
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#define SBBASE1 0xD8C00110
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#define SBBASE1_INIT_SYSFL 0x8400FE01
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#define SBBASE1_INIT_BPROM 0x8000FE01
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#define SBBASE2 0xD8C00120
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#define SBBASE2_INIT 0x8600FF81
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#define SBBASE3 0xD8C00130
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#define SBBASE3_INIT 0x8680FF81
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#define SBBASE4 0xD8C00140
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#define SBBASE4_INIT 0x9800F801
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#define SBBASE5 0xD8C00150
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#define SBBASE5_INIT 0x00000000
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#define SBBASE6 0xD8C00160
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#define SBBASE6_INIT 0x00000000
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#define SBBASE7 0xD8C00170
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#define SBBASE7_INIT 0x00000000
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#define SBCTRL00 0xD8C00200
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#define SBCTRL00_INIT 0x21111000
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#define SBCTRL10 0xD8C00210
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#define SBCTRL10_INIT 0x21111000
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#define SBCTRL20 0xD8C00220
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#define SBCTRL20_INIT 0x21111000
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#define SBCTRL30 0xD8C00230
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#define SBCTRL30_INIT 0x11111000
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#define SBCTRL40 0xD8C00240
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#define SBCTRL40_INIT 0x00140000
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#define SBCTRL50 0xD8C00250
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#define SBCTRL50_INIT 0x22100000
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#define SBCTRL60 0xD8C00260
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#define SBCTRL60_INIT 0x22100000
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#define SBCTRL70 0xD8C00270
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#define SBCTRL70_INIT 0x22100000
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#define SBCTRL01 0xD8C00204
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#define SBCTRL01_INIT 0x00100200
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#define SBCTRL11 0xD8C00214
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#define SBCTRL11_INIT 0x00100200
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#define SBCTRL21 0xD8C00224
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#define SBCTRL21_INIT 0x00100200
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#define SBCTRL31 0xD8C00234
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#define SBCTRL31_INIT 0x00100100
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#define SBCTRL41 0xD8C00244
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#define SBCTRL41_INIT 0x11011100
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#define SBCTRL51 0xD8C00254
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#define SBCTRL51_INIT 0x00001100
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#define SBCTRL61 0xD8C00264
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#define SBCTRL61_INIT 0x00001100
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#define SBCTRL71 0xD8C00274
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#define SBCTRL71_INIT 0x00001100
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#define SBCTRL02 0xD8C00208
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#define SBCTRL02_INIT 0x00000004
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#define SBCTRL12 0xD8C00218
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#define SBCTRL12_INIT 0x04000004
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#define SBCTRL22 0xD8C00228
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#define SBCTRL22_INIT 0x00000004
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#define SBCTRL32 0xD8C00238
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#define SBCTRL32_INIT 0x00000002
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#define SBCTRL42 0xD8C00248
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#define SBCTRL42_INIT 0x01000001
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#define SBCTRL52 0xD8C00258
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#define SBCTRL52_INIT 0x0000000F
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#define SBCTRL62 0xD8C00268
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#define SBCTRL62_INIT 0x0000000F
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#define SBCTRL72 0xD8C00278
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#define SBCTRL72_INIT 0x0000000F
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| 260 |
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#define SDBASE0 0xDA000008
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#define SDBASE1 0xDA00000C
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#define SDRAMBUS 0xDA000000
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| 264 |
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// 16MB SDRAM
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#define SDBASE0_8M_INIT 0x9000FF81
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#define SDBASE1_8M_INIT 0x9080FF81
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#define SDRAMBUS_8M_INIT 0xA8990654
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| 268 |
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| 269 |
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// 32MB SDRAM
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| 270 |
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#define SDBASE0_16M_INIT 0x9000FF01
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| 271 |
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#define SDBASE1_16M_INIT 0x9100FF01
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| 272 |
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#define SDRAMBUS_16M_INIT 0xA89a0654
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| 273 |
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| 274 |
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// 64MB SDRAM
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| 275 |
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#define SDBASE0_32M_INIT 0x9000fe01
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| 276 |
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#define SDBASE1_32M_INIT 0x9200fe01
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| 277 |
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#define SDRAMBUS_32M_INIT 0xa89b0654
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| 278 |
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| 279 |
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.macro hal_memc_init
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mov BCCR,a0
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| 281 |
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mov BCCR_INIT,d0
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| 282 |
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mov d0,(a0)
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| 283 |
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| 284 |
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// reduce the span of the ROM banks first
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| 285 |
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mov (SBBASE0),d0
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| 286 |
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btst 1,d0
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| 287 |
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beq 0f
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| 288 |
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mov 0x8000FE01,d0
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| 289 |
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mov d0,(SBBASE0)
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| 290 |
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0:
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| 291 |
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mov (SBBASE1),d0
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| 292 |
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btst 1,d0
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| 293 |
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beq 0f
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| 294 |
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mov 0x8000FE01,d0
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| 295 |
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mov d0,(SBBASE1)
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| 296 |
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0:
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| 297 |
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| 298 |
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// memory bank 2
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| 299 |
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mov SBBASE2_INIT,d0
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| 300 |
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mov d0,(SBBASE2)
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| 301 |
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mov SBCTRL20_INIT,d0
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| 302 |
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mov d0,(SBCTRL20)
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| 303 |
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mov SBCTRL21_INIT,d0
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| 304 |
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mov d0,(SBCTRL21)
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| 305 |
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mov SBCTRL22_INIT,d0
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| 306 |
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mov d0,(SBCTRL22)
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| 307 |
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| 308 |
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// memory bank 3
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| 309 |
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mov SBBASE3_INIT,d0
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| 310 |
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mov d0,(SBBASE3)
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| 311 |
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mov SBCTRL30_INIT,d0
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| 312 |
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mov d0,(SBCTRL30)
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| 313 |
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mov SBCTRL31_INIT,d0
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| 314 |
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mov d0,(SBCTRL31)
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| 315 |
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mov SBCTRL32_INIT,d0
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| 316 |
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mov d0,(SBCTRL32)
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| 317 |
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| 318 |
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// memory bank 4
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| 319 |
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mov SBBASE4_INIT,d0
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| 320 |
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mov d0,(SBBASE4)
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| 321 |
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mov SBCTRL40_INIT,d0
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| 322 |
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mov d0,(SBCTRL40)
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| 323 |
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mov SBCTRL41_INIT,d0
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| 324 |
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mov d0,(SBCTRL41)
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| 325 |
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mov SBCTRL42_INIT,d0
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| 326 |
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mov d0,(SBCTRL42)
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| 327 |
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| 328 |
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// memory bank 5
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| 329 |
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#if SBBASE5_INIT != 0
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| 330 |
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mov SBBASE5_INIT,d0
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| 331 |
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mov d0,(SBBASE5)
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| 332 |
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mov SBCTRL50_INIT,d0
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| 333 |
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mov d0,(SBCTRL50)
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| 334 |
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mov SBCTRL51_INIT,d0
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| 335 |
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mov d0,(SBCTRL51)
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| 336 |
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mov SBCTRL52_INIT,d0
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| 337 |
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mov d0,(SBCTRL52)
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| 338 |
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#endif
|
| 339 |
|
|
|
| 340 |
|
|
// memory bank 6
|
| 341 |
|
|
#if SBBASE6_INIT != 0
|
| 342 |
|
|
mov SBBASE6_INIT,d0
|
| 343 |
|
|
mov d0,(SBBASE6)
|
| 344 |
|
|
mov SBCTRL60_INIT,d0
|
| 345 |
|
|
mov d0,(SBCTRL60)
|
| 346 |
|
|
mov SBCTRL61_INIT,d0
|
| 347 |
|
|
mov d0,(SBCTRL61)
|
| 348 |
|
|
mov SBCTRL62_INIT,d0
|
| 349 |
|
|
mov d0,(SBCTRL62)
|
| 350 |
|
|
#endif
|
| 351 |
|
|
|
| 352 |
|
|
// memory bank 7
|
| 353 |
|
|
#if SBBASE7_INIT != 0
|
| 354 |
|
|
mov SBBASE7_INIT,d0
|
| 355 |
|
|
mov d0,(SBBASE7)
|
| 356 |
|
|
mov SBCTRL70_INIT,d0
|
| 357 |
|
|
mov d0,(SBCTRL70)
|
| 358 |
|
|
mov SBCTRL71_INIT,d0
|
| 359 |
|
|
mov d0,(SBCTRL71)
|
| 360 |
|
|
mov SBCTRL72_INIT,d0
|
| 361 |
|
|
mov d0,(SBCTRL72)
|
| 362 |
|
|
#endif
|
| 363 |
|
|
|
| 364 |
|
|
#ifndef CYG_HAL_STARTUP_RAM
|
| 365 |
|
|
|
| 366 |
|
|
// Setup for 64MB initially and determine final mem config below.
|
| 367 |
|
|
mov SDRAMBUS,a0
|
| 368 |
|
|
mov (a0),d0
|
| 369 |
|
|
and 0xfffffffb,d0 // disable refresh
|
| 370 |
|
|
mov d0,(a0)
|
| 371 |
|
|
|
| 372 |
|
|
mov SDBASE0,a0
|
| 373 |
|
|
mov SDBASE0_32M_INIT,d0
|
| 374 |
|
|
mov d0,(a0)
|
| 375 |
|
|
mov SDBASE1,a0
|
| 376 |
|
|
mov SDBASE1_32M_INIT,d0
|
| 377 |
|
|
mov d0,(a0)
|
| 378 |
|
|
mov SDRAMBUS,a0
|
| 379 |
|
|
mov SDRAMBUS_32M_INIT,d0
|
| 380 |
|
|
mov d0,(a0)
|
| 381 |
|
|
|
| 382 |
|
|
mov 0x1000,d0
|
| 383 |
|
|
0:
|
| 384 |
|
|
sub 1,d0
|
| 385 |
|
|
bne 0b
|
| 386 |
|
|
|
| 387 |
|
|
// Check for 16MB and 32MB shadowing to determine actual amount of
|
| 388 |
|
|
// memory installed. This assumes 8M, 16M, or 32M configs.
|
| 389 |
|
|
mov 0,d0
|
| 390 |
|
|
mov d0,(0x90800000)
|
| 391 |
|
|
mov d0,(0x91000000)
|
| 392 |
|
|
mov 0xaaaaaaaa,d0
|
| 393 |
|
|
mov d0,(0x90000000)
|
| 394 |
|
|
mov (0x90800000),d1
|
| 395 |
|
|
cmp d0,d1
|
| 396 |
|
|
bne 1f
|
| 397 |
|
|
|
| 398 |
|
|
// 16MB installed
|
| 399 |
|
|
mov SDRAMBUS,a0
|
| 400 |
|
|
mov (a0),d0
|
| 401 |
|
|
and 0xfffffffb,d0 // disable refresh
|
| 402 |
|
|
mov d0,(a0)
|
| 403 |
|
|
mov SDBASE0,a1
|
| 404 |
|
|
mov SDBASE0_8M_INIT,d1
|
| 405 |
|
|
mov d1,(a1)
|
| 406 |
|
|
mov SDBASE1,a1
|
| 407 |
|
|
mov SDBASE1_8M_INIT,d1
|
| 408 |
|
|
mov d1,(a1)
|
| 409 |
|
|
mov SDRAMBUS_8M_INIT,d0
|
| 410 |
|
|
mov d0,(a0)
|
| 411 |
|
|
jmp 2f
|
| 412 |
|
|
1:
|
| 413 |
|
|
mov (0x91000000),d1
|
| 414 |
|
|
cmp d0,d1
|
| 415 |
|
|
bne 2f
|
| 416 |
|
|
|
| 417 |
|
|
// 32MB installed
|
| 418 |
|
|
mov SDRAMBUS,a0
|
| 419 |
|
|
mov (a0),d0
|
| 420 |
|
|
and 0xfffffffb,d0 // disable refresh
|
| 421 |
|
|
mov d0,(a0)
|
| 422 |
|
|
mov SDBASE0,a1
|
| 423 |
|
|
mov SDBASE0_16M_INIT,d1
|
| 424 |
|
|
mov d1,(a1)
|
| 425 |
|
|
mov SDBASE1,a1
|
| 426 |
|
|
mov SDBASE1_16M_INIT,d1
|
| 427 |
|
|
mov d1,(a1)
|
| 428 |
|
|
mov SDRAMBUS_16M_INIT,d0
|
| 429 |
|
|
mov d0,(a0)
|
| 430 |
|
|
2:
|
| 431 |
|
|
#endif // ! CYG_HAL_STARTUP_RAM
|
| 432 |
|
|
|
| 433 |
|
|
// now the ROMs need putting into the right place
|
| 434 |
|
|
// - this is tricky because when we're booting from the system flash,
|
| 435 |
|
|
// it has had its base address pre-swapped by the CPU
|
| 436 |
|
|
// - we need to copy a small piece of code to the SRAM and execute it
|
| 437 |
|
|
// there
|
| 438 |
|
|
|
| 439 |
|
|
// display on the LEDs
|
| 440 |
|
|
mov 0x7e7e7e7e,d0 # '-.-.-.-.'
|
| 441 |
|
|
mov d0,(HAL_LED_ADDRESS)
|
| 442 |
|
|
|
| 443 |
|
|
// copy the ROM address adjustor to the SRAM
|
| 444 |
|
|
add -4,sp
|
| 445 |
|
|
call __hal_plf_base_ref,[],0 // note we can't address ourselves directly yet
|
| 446 |
|
|
__hal_plf_base_ref:
|
| 447 |
|
|
movm (sp),[a3]
|
| 448 |
|
|
mov a3,a0
|
| 449 |
|
|
add __hal_plf_rom_swap_start-__hal_plf_base_ref,a0
|
| 450 |
|
|
add __hal_plf_rom_swap_end-__hal_plf_base_ref,a3
|
| 451 |
|
|
mov 0x8C000000,a1
|
| 452 |
|
|
0: movbu (a0),d0
|
| 453 |
|
|
movbu d0,(a1)
|
| 454 |
|
|
inc a0
|
| 455 |
|
|
inc a1
|
| 456 |
|
|
cmp a0,a3
|
| 457 |
|
|
bcc 0b
|
| 458 |
|
|
mov 0x8C000000,a1
|
| 459 |
|
|
jmp (a1)
|
| 460 |
|
|
|
| 461 |
|
|
////////////////////////////////////////////////////////////////
|
| 462 |
|
|
__hal_plf_rom_swap_start:
|
| 463 |
|
|
// put boot PROM at 0x80000000, and system flash at 0x84000000
|
| 464 |
|
|
mov SBBASE0_INIT_BPROM,d0
|
| 465 |
|
|
mov d0,(SBBASE0)
|
| 466 |
|
|
|
| 467 |
|
|
mov SBBASE1_INIT_BPROM,d0
|
| 468 |
|
|
mov d0,(SBBASE1)
|
| 469 |
|
|
|
| 470 |
|
|
// memory bank 0
|
| 471 |
|
|
mov SBCTRL00_INIT,d0
|
| 472 |
|
|
mov d0,(SBCTRL00)
|
| 473 |
|
|
mov SBCTRL01_INIT,d0
|
| 474 |
|
|
mov d0,(SBCTRL01)
|
| 475 |
|
|
mov SBCTRL02_INIT,d0
|
| 476 |
|
|
mov d0,(SBCTRL02)
|
| 477 |
|
|
|
| 478 |
|
|
// memory bank 1
|
| 479 |
|
|
mov SBCTRL10_INIT,d0
|
| 480 |
|
|
mov d0,(SBCTRL10)
|
| 481 |
|
|
mov SBCTRL11_INIT,d0
|
| 482 |
|
|
mov d0,(SBCTRL11)
|
| 483 |
|
|
mov SBCTRL12_INIT,d0
|
| 484 |
|
|
mov d0,(SBCTRL12)
|
| 485 |
|
|
|
| 486 |
|
|
// jump forward so we start running from the 80000000/84000000 base address
|
| 487 |
|
|
mov __hal_plf_rom_swap_reentry,a0
|
| 488 |
|
|
jmp (a0)
|
| 489 |
|
|
__hal_plf_rom_swap_end:
|
| 490 |
|
|
////////////////////////////////////////////////////////////////
|
| 491 |
|
|
|
| 492 |
|
|
__hal_plf_rom_swap_reentry:
|
| 493 |
|
|
// clear the on-CPU 16Kb SRAM
|
| 494 |
|
|
clr d0
|
| 495 |
|
|
mov 16384/4-4,d1
|
| 496 |
|
|
mov 0x8C000000,a0
|
| 497 |
|
|
0:
|
| 498 |
|
|
mov d0,(a0,d1)
|
| 499 |
|
|
sub 4,d1
|
| 500 |
|
|
bnc 0b
|
| 501 |
|
|
|
| 502 |
|
|
.endm
|
| 503 |
|
|
|
| 504 |
|
|
#define CYGPKG_HAL_MN10300_MEMC_DEFINED
|
| 505 |
|
|
|
| 506 |
|
|
#endif
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
//-----------------------------------------------------------------------------
|
| 510 |
|
|
// Syscall support.
|
| 511 |
|
|
#if defined(CYGPKG_CYGMON) || defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
|
| 512 |
|
|
// Cygmon provides syscall handling for this board
|
| 513 |
|
|
// These must be kept in sync with the rest of the tree.
|
| 514 |
|
|
#define SIGSYS 12
|
| 515 |
|
|
#define SIGSYSCALL SIGSYS
|
| 516 |
|
|
#endif
|
| 517 |
|
|
|
| 518 |
|
|
#------------------------------------------------------------------------------
|
| 519 |
|
|
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
|
| 520 |
|
|
# end of platform.inc
|
