| 1 |
27 |
unneback |
#ifndef CYGONCE_PLF_IO_H
|
| 2 |
|
|
#define CYGONCE_PLF_IO_H
|
| 3 |
|
|
|
| 4 |
|
|
//=============================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// plf_io.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// Platform specific IO support
|
| 9 |
|
|
//
|
| 10 |
|
|
//=============================================================================
|
| 11 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 21 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 26 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 30 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 31 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 32 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 33 |
|
|
// License. However the source code for this file must still be made available
|
| 34 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 37 |
|
|
// this file might be covered by the GNU General Public License.
|
| 38 |
|
|
//
|
| 39 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 40 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 41 |
|
|
// -------------------------------------------
|
| 42 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 43 |
|
|
//=============================================================================
|
| 44 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 45 |
|
|
//
|
| 46 |
|
|
// Author(s): dhowells
|
| 47 |
|
|
// Contributors: dmoseley
|
| 48 |
|
|
// Date: 2001-05-17
|
| 49 |
|
|
// Purpose: ASB2305 platform IO support
|
| 50 |
|
|
// Description:
|
| 51 |
|
|
// Usage: #include <cyg/hal/plf_io.h>
|
| 52 |
|
|
//
|
| 53 |
|
|
//####DESCRIPTIONEND####
|
| 54 |
|
|
//
|
| 55 |
|
|
//=============================================================================
|
| 56 |
|
|
|
| 57 |
|
|
#include <pkgconf/hal.h>
|
| 58 |
|
|
#ifndef __ASSEMBLER__
|
| 59 |
|
|
#include <cyg/hal/hal_intr.h>
|
| 60 |
|
|
#endif
|
| 61 |
|
|
|
| 62 |
|
|
#ifdef __ASSEMBLER__
|
| 63 |
|
|
#define HAL_REG_8(x) x
|
| 64 |
|
|
#define HAL_REG_16(x) x
|
| 65 |
|
|
#define HAL_REG_32(x) x
|
| 66 |
|
|
#else
|
| 67 |
|
|
#define HAL_REG_8(x) (volatile cyg_uint8*)(x)
|
| 68 |
|
|
#define HAL_REG_16(x) (volatile cyg_uint16*)(x)
|
| 69 |
|
|
#define HAL_REG_32(x) (volatile cyg_uint32*)(x)
|
| 70 |
|
|
#endif
|
| 71 |
|
|
|
| 72 |
|
|
# define CYGARC_UNCACHED_ADDRESS(x) ((x)|0x20000000)
|
| 73 |
|
|
|
| 74 |
|
|
//-----------------------------------------------------------------------------
|
| 75 |
|
|
|
| 76 |
|
|
/* ASB GPIO Registers */
|
| 77 |
|
|
#define HAL_GPIO_BASE 0xDB000000
|
| 78 |
|
|
|
| 79 |
|
|
#define HAL_GPIO_0_MODE_OFFSET 0x0000
|
| 80 |
|
|
#define HAL_GPIO_0_IN_OFFSET 0x0004
|
| 81 |
|
|
#define HAL_GPIO_0_OUT_OFFSET 0x0008
|
| 82 |
|
|
#define HAL_GPIO_1_MODE_OFFSET 0x0100
|
| 83 |
|
|
#define HAL_GPIO_1_IN_OFFSET 0x0104
|
| 84 |
|
|
#define HAL_GPIO_1_OUT_OFFSET 0x0108
|
| 85 |
|
|
#define HAL_GPIO_2_MODE_OFFSET 0x0200
|
| 86 |
|
|
#define HAL_GPIO_2_IN_OFFSET 0x0204
|
| 87 |
|
|
#define HAL_GPIO_2_OUT_OFFSET 0x0208
|
| 88 |
|
|
#define HAL_GPIO_3_MODE_OFFSET 0x0300
|
| 89 |
|
|
#define HAL_GPIO_3_IN_OFFSET 0x0304
|
| 90 |
|
|
#define HAL_GPIO_3_OUT_OFFSET 0x0308
|
| 91 |
|
|
#define HAL_GPIO_4_MODE_OFFSET 0x0400
|
| 92 |
|
|
#define HAL_GPIO_4_IN_OFFSET 0x0404
|
| 93 |
|
|
#define HAL_GPIO_4_OUT_OFFSET 0x0408
|
| 94 |
|
|
#define HAL_GPIO_5_MODE_OFFSET 0x0500
|
| 95 |
|
|
#define HAL_GPIO_5_IN_OFFSET 0x0504
|
| 96 |
|
|
#define HAL_GPIO_5_OUT_OFFSET 0x0508
|
| 97 |
|
|
|
| 98 |
|
|
#define HAL_GPIO_0_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_0_MODE_OFFSET)
|
| 99 |
|
|
#define HAL_GPIO_0_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_IN_OFFSET)
|
| 100 |
|
|
#define HAL_GPIO_0_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_OUT_OFFSET)
|
| 101 |
|
|
#define HAL_GPIO_1_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_1_MODE_OFFSET)
|
| 102 |
|
|
#define HAL_GPIO_1_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_IN_OFFSET)
|
| 103 |
|
|
#define HAL_GPIO_1_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_OUT_OFFSET)
|
| 104 |
|
|
#define HAL_GPIO_2_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_2_MODE_OFFSET)
|
| 105 |
|
|
#define HAL_GPIO_2_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_IN_OFFSET)
|
| 106 |
|
|
#define HAL_GPIO_2_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_OUT_OFFSET)
|
| 107 |
|
|
#define HAL_GPIO_3_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_3_MODE_OFFSET)
|
| 108 |
|
|
#define HAL_GPIO_3_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_IN_OFFSET)
|
| 109 |
|
|
#define HAL_GPIO_3_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_OUT_OFFSET)
|
| 110 |
|
|
#define HAL_GPIO_4_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_4_MODE_OFFSET)
|
| 111 |
|
|
#define HAL_GPIO_4_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_IN_OFFSET)
|
| 112 |
|
|
#define HAL_GPIO_4_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_OUT_OFFSET)
|
| 113 |
|
|
#define HAL_GPIO_5_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_5_MODE_OFFSET)
|
| 114 |
|
|
#define HAL_GPIO_5_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_IN_OFFSET)
|
| 115 |
|
|
#define HAL_GPIO_5_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_OUT_OFFSET)
|
| 116 |
|
|
|
| 117 |
|
|
//-----------------------------------------------------------------------------
|
| 118 |
|
|
#define HAL_LED_ADDRESS 0xA6F90000
|
| 119 |
|
|
#define HAL_GPIO_MODE_ALL_OUTPUT 0x5555
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
#ifdef __ASSEMBLER__
|
| 123 |
|
|
|
| 124 |
|
|
# include <cyg/hal/platform.inc>
|
| 125 |
|
|
# define DEBUG_DISPLAY(hexdig) hal_diag_led hexdig
|
| 126 |
|
|
# define DEBUG_DELAY() \
|
| 127 |
|
|
mov 0x20000, d0; \
|
| 128 |
|
|
0: sub 1, d0; \
|
| 129 |
|
|
bne 0b; \
|
| 130 |
|
|
nop
|
| 131 |
|
|
|
| 132 |
|
|
#else
|
| 133 |
|
|
|
| 134 |
|
|
extern cyg_uint8 cyg_hal_plf_led_val(CYG_WORD hexdig);
|
| 135 |
|
|
# define DEBUG_DISPLAY(hexdig) HAL_WRITE_UINT8(HAL_LED_ADDRESS, cyg_hal_plf_led_val(hexdig))
|
| 136 |
|
|
# define DEBUG_DELAY() \
|
| 137 |
|
|
{ \
|
| 138 |
|
|
volatile int i = 0x80000; \
|
| 139 |
|
|
while (--i) ; \
|
| 140 |
|
|
}
|
| 141 |
|
|
|
| 142 |
|
|
#endif
|
| 143 |
|
|
|
| 144 |
|
|
//-----------------------------------------------------------------------------
|
| 145 |
|
|
// PCI access stuff
|
| 146 |
|
|
|
| 147 |
|
|
// Compute address necessary to access PCI config space for the given
|
| 148 |
|
|
// bus and device.
|
| 149 |
|
|
#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
|
| 150 |
|
|
(0x80000000 | ((__bus) << 16) | ((__devfn) << 8) | ((__offset) & ~3))
|
| 151 |
|
|
|
| 152 |
|
|
// Read a value from the PCI configuration space of the appropriate
|
| 153 |
|
|
// size at an address composed from the bus, devfn and offset.
|
| 154 |
|
|
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
|
| 155 |
|
|
do { \
|
| 156 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 157 |
|
|
HAL_READ_UINT8(0xBE040000+(__offset),(__val)); \
|
| 158 |
|
|
} \
|
| 159 |
|
|
else { \
|
| 160 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 161 |
|
|
HAL_READ_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
|
| 162 |
|
|
} \
|
| 163 |
|
|
} while(0)
|
| 164 |
|
|
|
| 165 |
|
|
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
|
| 166 |
|
|
do { \
|
| 167 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 168 |
|
|
HAL_READ_UINT16(0xBE040000+(__offset),(__val)); \
|
| 169 |
|
|
} \
|
| 170 |
|
|
else { \
|
| 171 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 172 |
|
|
HAL_READ_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
|
| 173 |
|
|
} \
|
| 174 |
|
|
} while(0)
|
| 175 |
|
|
|
| 176 |
|
|
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
|
| 177 |
|
|
do { \
|
| 178 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 179 |
|
|
HAL_READ_UINT32(0xBE040000+(__offset),(__val)); \
|
| 180 |
|
|
} \
|
| 181 |
|
|
else { \
|
| 182 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 183 |
|
|
HAL_READ_UINT32(0xBFFFFFFC,(__val)); \
|
| 184 |
|
|
} \
|
| 185 |
|
|
} while(0)
|
| 186 |
|
|
|
| 187 |
|
|
// Write a value to the PCI configuration space of the appropriate
|
| 188 |
|
|
// size at an address composed from the bus, devfn and offset.
|
| 189 |
|
|
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
|
| 190 |
|
|
do { \
|
| 191 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 192 |
|
|
HAL_WRITE_UINT8(0xBE040000+(__offset),(__val)); \
|
| 193 |
|
|
} \
|
| 194 |
|
|
else { \
|
| 195 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 196 |
|
|
HAL_WRITE_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
|
| 197 |
|
|
} \
|
| 198 |
|
|
} while(0)
|
| 199 |
|
|
|
| 200 |
|
|
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
|
| 201 |
|
|
do { \
|
| 202 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 203 |
|
|
HAL_WRITE_UINT16(0xBE040000+(__offset),(__val)); \
|
| 204 |
|
|
} \
|
| 205 |
|
|
else { \
|
| 206 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 207 |
|
|
HAL_WRITE_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
|
| 208 |
|
|
} \
|
| 209 |
|
|
} while(0)
|
| 210 |
|
|
|
| 211 |
|
|
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
|
| 212 |
|
|
do { \
|
| 213 |
|
|
if ((__bus)==0 && (__devfn)==0) { \
|
| 214 |
|
|
HAL_WRITE_UINT32(0xBE040000+(__offset),(__val)); \
|
| 215 |
|
|
} \
|
| 216 |
|
|
else { \
|
| 217 |
|
|
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
|
| 218 |
|
|
HAL_WRITE_UINT32(0xBFFFFFFC,(__val)); \
|
| 219 |
|
|
} \
|
| 220 |
|
|
} while(0)
|
| 221 |
|
|
|
| 222 |
|
|
// Initialize the PCI bus.
|
| 223 |
|
|
#define HAL_PCI_INIT() \
|
| 224 |
|
|
do { \
|
| 225 |
|
|
cyg_uint32 devfn; \
|
| 226 |
|
|
cyg_uint16 word; \
|
| 227 |
|
|
\
|
| 228 |
|
|
/* we need to set up the bridge _now_ or we won't be able to access the */ \
|
| 229 |
|
|
/* PCI config registers */ \
|
| 230 |
|
|
HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
|
| 231 |
|
|
word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
|
| 232 |
|
|
word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
|
| 233 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
|
| 234 |
|
|
\
|
| 235 |
|
|
HAL_PCI_CFG_WRITE_UINT16(0,0,CYG_PCI_CFG_STATUS, 0xF800); \
|
| 236 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_LATENCY_TIMER, 0x10); \
|
| 237 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_BAR_0, 0x80000000); \
|
| 238 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_INT_LINE, 1); \
|
| 239 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,0x48, 0x98000000); \
|
| 240 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x41, 0x00); \
|
| 241 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x42, 0x01); \
|
| 242 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x44, 0x01); \
|
| 243 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,0x50, 0x00000001); \
|
| 244 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,0x58, 0x00000002); \
|
| 245 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,0x5C, 0x00000001); \
|
| 246 |
|
|
\
|
| 247 |
|
|
/* we also need to set up the PCI-PCI bridge (no BIOS, you see) */ \
|
| 248 |
|
|
devfn = 3<<3 | 0; \
|
| 249 |
|
|
\
|
| 250 |
|
|
/* IO: 0x00010000-0x0001ffff */ \
|
| 251 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_BASE, 0x01); \
|
| 252 |
|
|
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_BASE_UPPER16, 0x0001); \
|
| 253 |
|
|
HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_LIMIT, 0xF1); \
|
| 254 |
|
|
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_LIMIT_UPPER16, 0x0001); \
|
| 255 |
|
|
\
|
| 256 |
|
|
HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
|
| 257 |
|
|
word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
|
| 258 |
|
|
word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
|
| 259 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
|
| 260 |
|
|
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_BASE, 0x1000); \
|
| 261 |
|
|
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_LIMIT, 0x1000); \
|
| 262 |
|
|
} while(0)
|
| 263 |
|
|
|
| 264 |
|
|
|
| 265 |
|
|
//-----------------------------------------------------------------------------
|
| 266 |
|
|
// Resources
|
| 267 |
|
|
|
| 268 |
|
|
// Map PCI device resources starting from these addresses in PCI space.
|
| 269 |
|
|
#define HAL_PCI_ALLOC_BASE_MEMORY 0x10000000
|
| 270 |
|
|
#define HAL_PCI_ALLOC_BASE_IO 0x1000
|
| 271 |
|
|
|
| 272 |
|
|
// This is where the PCI spaces are mapped in the CPU's address space.
|
| 273 |
|
|
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
|
| 274 |
|
|
#define HAL_PCI_PHYSICAL_IO_BASE 0xBE000000
|
| 275 |
|
|
|
| 276 |
|
|
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
|
| 277 |
|
|
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
|
| 278 |
|
|
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
|
| 279 |
|
|
CYG_MACRO_START \
|
| 280 |
|
|
cyg_uint8 __req; \
|
| 281 |
|
|
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
|
| 282 |
|
|
if (0 != __req) { \
|
| 283 |
|
|
/* Interrupt assignment as 21285 sees them. (From */ \
|
| 284 |
|
|
/* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
|
| 285 |
|
|
CYG_ADDRWORD __translation[4] = { \
|
| 286 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_170, /* INTC# */ \
|
| 287 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_169, /* INTB# */ \
|
| 288 |
|
|
CYGNUM_HAL_INTERRUPT_EXTERNAL_1, /* INTA# */ \
|
| 289 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_171}; /* INTD# */ \
|
| 290 |
|
|
\
|
| 291 |
|
|
/* The PCI lines from the different slots are wired like this */ \
|
| 292 |
|
|
/* on the PCI backplane: */ \
|
| 293 |
|
|
/* pin6A pin7B pin7A pin8B */ \
|
| 294 |
|
|
/* System Slot INTA# INTB# INTC# INTD# */ \
|
| 295 |
|
|
/* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
|
| 296 |
|
|
/* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
|
| 297 |
|
|
/* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
|
| 298 |
|
|
/* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
|
| 299 |
|
|
/* */ \
|
| 300 |
|
|
/* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
|
| 301 |
|
|
/* */ \
|
| 302 |
|
|
/* Devsel signals are wired to, resulting in device IDs: */ \
|
| 303 |
|
|
/* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
|
| 304 |
|
|
/* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
|
| 305 |
|
|
/* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
|
| 306 |
|
|
/* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
|
| 307 |
|
|
/* */ \
|
| 308 |
|
|
/* (From PCI Development Backplane, 3.2.1 General) */ \
|
| 309 |
|
|
/* */ \
|
| 310 |
|
|
/* The observant reader will notice that the array does not */ \
|
| 311 |
|
|
/* match the table of how interrupts are wired. The array */ \
|
| 312 |
|
|
/* does however match observed behavior of the hardware: */ \
|
| 313 |
|
|
/* */ \
|
| 314 |
|
|
/* Observed interrupts with an Intel ethernet card */ \
|
| 315 |
|
|
/* put in the slots in turn and set to generate interrupts: */ \
|
| 316 |
|
|
/* slot 1/intA# (dev 8): caused host INTB# */ \
|
| 317 |
|
|
/* slot 2/intA# (dev 7): caused host INTC# */ \
|
| 318 |
|
|
/* slot 3/intA# (dev 6): caused host INTD# */ \
|
| 319 |
|
|
/* slot 4/intA# (dev 5): caused host INTA# */ \
|
| 320 |
|
|
\
|
| 321 |
|
|
__vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
|
| 322 |
|
|
__valid = true; \
|
| 323 |
|
|
} else { \
|
| 324 |
|
|
/* Device will not generate interrupt requests. */ \
|
| 325 |
|
|
__valid = false; \
|
| 326 |
|
|
} \
|
| 327 |
|
|
CYG_MACRO_END
|
| 328 |
|
|
|
| 329 |
|
|
|
| 330 |
|
|
//-----------------------------------------------------------------------------
|
| 331 |
|
|
// Bus address translation macros
|
| 332 |
|
|
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
|
| 333 |
|
|
CYG_MACRO_START \
|
| 334 |
|
|
(__bus_addr) = (CYG_ADDRESS)((cyg_uint32)(__cpu_addr)&~0x20000000); \
|
| 335 |
|
|
CYG_MACRO_END
|
| 336 |
|
|
|
| 337 |
|
|
#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
|
| 338 |
|
|
CYG_MACRO_START \
|
| 339 |
|
|
(__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
|
| 340 |
|
|
CYG_MACRO_END
|
| 341 |
|
|
|
| 342 |
|
|
//-----------------------------------------------------------------------------
|
| 343 |
|
|
// end of plf_io.h
|
| 344 |
|
|
#endif // CYGONCE_PLF_IO_H
|
