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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [stb/] [v2_0/] [src/] [hal_diag.c] - Blame information for rev 174

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/*=============================================================================
2
//
3
//      hal_diag.c
4
//
5
//      HAL diagnostic output code
6
//
7
//=============================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//=============================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):   nickg
44
// Contributors:        nickg
45
// Date:        1998-03-02
46
// Purpose:     HAL diagnostic output
47
// Description: Implementations of HAL diagnostic output support.
48
//
49
//####DESCRIPTIONEND####
50
//
51
//===========================================================================*/
52
 
53
#include <pkgconf/hal.h>
54
 
55
#include <cyg/infra/cyg_type.h>          // base types
56
#include <cyg/infra/cyg_trac.h>         // tracing macros
57
#include <cyg/infra/cyg_ass.h>          // assertion macros
58
 
59
#include <cyg/hal/hal_diag.h>
60
#include <cyg/hal/hal_intr.h>
61
#include <cyg/hal/hal_misc.h>
62
 
63
/*---------------------------------------------------------------------------*/
64
/* Select default diag channel to use                                        */
65
 
66
//#define CYG_KERNEL_DIAG_ROMART
67
//#define CYG_KERNEL_DIAG_SERIAL0
68
//#define CYG_KERNEL_DIAG_SERIAL1
69
//#define CYG_KERNEL_DIAG_SERIAL2
70
//#define CYG_KERNEL_DIAG_BUFFER
71
//#define CYG_KERNEL_DIAG_GDB
72
 
73
#if !defined(CYG_KERNEL_DIAG_SERIAL0) && \
74
    !defined(CYG_KERNEL_DIAG_SERIAL1) && \
75
    !defined(CYG_KERNEL_DIAG_SERIAL2) && \
76
    !defined(CYG_KERNEL_DIAG_ROMART)
77
 
78
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
79
 
80
#define CYG_KERNEL_DIAG_SERIAL0
81
#define CYG_KERNEL_DIAG_GDB
82
 
83
#else
84
 
85
#define CYG_KERNEL_DIAG_SERIAL0
86
 
87
#endif
88
 
89
#endif
90
 
91
//#define CYG_HAL_MN10300_STB_SERIAL2
92
 
93
/*---------------------------------------------------------------------------*/
94
// MN10300 Serial line
95
 
96
#if defined(CYG_HAL_MN10300_STB_SERIAL0) || defined(CYG_KERNEL_DIAG_SERIAL0)
97
 
98
// We use serial0 on AM33
99
#define SERIAL0_CR       ((volatile cyg_uint16 *)0xd4002000)
100
#define SERIAL0_ICR      ((volatile cyg_uint8 *) 0xd4002004)
101
#define SERIAL0_TXR      ((volatile cyg_uint8 *) 0xd4002008)
102
#define SERIAL0_RXR      ((volatile cyg_uint8 *) 0xd4002009)
103
#define SERIAL0_SR       ((volatile cyg_uint16 *)0xd400200c)
104
 
105
// Timer 2 provides baud rate divisor
106
#define TIMER0_MD       ((volatile cyg_uint8 *)0xd4003002)
107
#define TIMER0_BR       ((volatile cyg_uint8 *)0xd4003012)
108
#define TIMER0_CR       ((volatile cyg_uint8 *)0xd4003022)
109
 
110
// Timer 0 provides a prescaler for lower baud rates
111
#define HW_TIMER0_MD       ((volatile cyg_uint8 *)0xd4003000)
112
#define HW_TIMER0_BR       ((volatile cyg_uint8 *)0xd4003010)
113
#define HW_TIMER0_CR       ((volatile cyg_uint8 *)0xd4003020)
114
 
115
#define SIO_LSTAT_TRDY  0x20
116
#define SIO_LSTAT_RRDY  0x10
117
 
118
#define SERIAL_CR_TXE   0x8000
119
 
120
void hal_diag_init_serial0(void)
121
{
122
#if 1    
123
    // 99 translates to 38400 baud.
124
    *TIMER0_BR = 99;
125
    // Timer0 sourced from IOCLK
126
    *TIMER0_MD = 0x80;
127
#else
128
    // 1 and 198 translate into 9800 baud
129
    *TIMER0_BR = 1;
130
    *TIMER0_MD = 0x84;          // source = timer 0 overflow
131
    *HW_TIMER0_BR = 198;        // timer 0 base register
132
    *HW_TIMER0_CR = 0x80;       // source from ioclk
133
#endif
134
 
135
    // No interrupts for now.
136
    *SERIAL0_ICR = 0x00;
137
 
138
    // Source from timer 1, 8bit chars, enable tx and rx
139
    *SERIAL0_CR = 0xc085;
140
}
141
 
142
void hal_diag_write_char_serial0(char c)
143
{
144
    register volatile cyg_uint16 *volatile tty_status = SERIAL0_SR;
145
    register volatile cyg_uint8 *volatile tty_tx = SERIAL0_TXR;
146
 
147
    while( (*tty_status & SIO_LSTAT_TRDY) != 0 ) continue;
148
 
149
    *tty_tx = c;
150
}
151
 
152
void hal_diag_drain_serial0(void)
153
{
154
    register volatile cyg_uint16 *volatile tty_status = SERIAL0_SR;
155
 
156
    while( (*tty_status & SIO_LSTAT_TRDY) != 0 ) continue;
157
}
158
 
159
void hal_diag_read_char_serial0(char *c)
160
{
161
    register volatile cyg_uint16 *volatile tty_status = SERIAL0_SR;
162
    register volatile cyg_uint8 *volatile tty_rx = SERIAL0_RXR;
163
 
164
    while( (*tty_status & SIO_LSTAT_RRDY) == 0 ) continue;
165
 
166
    *c = *tty_rx;
167
 
168
    // We must ack the interrupt caused by that read to avoid
169
    // confusing the GDB stub ROM.
170
    HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX );
171
}
172
 
173
#if defined(CYG_KERNEL_DIAG_SERIAL0)
174
 
175
#define hal_diag_init_serial hal_diag_init_serial0
176
#define hal_diag_write_char_serial hal_diag_write_char_serial0
177
#define hal_diag_drain_serial hal_diag_drain_serial0
178
#define hal_diag_read_char_serial hal_diag_read_char_serial0
179
 
180
#endif
181
 
182
#endif
183
 
184
/*---------------------------------------------------------------------------*/
185
// MN10300 Serial line
186
 
187
#if defined(CYG_HAL_MN10300_STB_SERIAL1) || defined(CYG_KERNEL_DIAG_SERIAL1)
188
 
189
// We use serial1 on MN103002
190
#define SERIAL1_CR       ((volatile cyg_uint16 *)0xd4002010)
191
#define SERIAL1_ICR      ((volatile cyg_uint8 *) 0xd4002014)
192
#define SERIAL1_TXR      ((volatile cyg_uint8 *) 0xd4002018)
193
#define SERIAL1_RXR      ((volatile cyg_uint8 *) 0xd4002019)
194
#define SERIAL1_SR       ((volatile cyg_uint16 *)0xd400201c)
195
 
196
// Timer 1 provided baud rate divisor
197
#define TIMER1_MD       ((volatile cyg_uint8 *)0xd4003001)
198
#define TIMER1_BR       ((volatile cyg_uint8 *)0xd4003011)
199
#define TIMER1_CR       ((volatile cyg_uint8 *)0xd4003021)
200
 
201
// Timer 0 provides a prescaler for lower baud rates
202
#define HW_TIMER0_MD       ((volatile cyg_uint8 *)0xd4003000)
203
#define HW_TIMER0_BR       ((volatile cyg_uint8 *)0xd4003010)
204
#define HW_TIMER0_CR       ((volatile cyg_uint8 *)0xd4003020)
205
 
206
#define SIO1_LSTAT_TRDY  0x20
207
#define SIO1_LSTAT_RRDY  0x10
208
 
209
#define SERIAL_CR_TXE   0x8000
210
 
211
void hal_diag_init_serial1(void)
212
{
213
#if 1    
214
    // 99 translates to 38400 baud.
215
    *TIMER1_BR = 99;
216
 
217
    // Timer1 sourced from IOCLK
218
    *TIMER1_MD = 0x80;
219
 
220
#else
221
 
222
    // 1 and 198 translate into 9800 baud
223
    *TIMER1_BR = 1;
224
    *TIMER1_MD = 0x84;          // source = timer 0 overflow
225
    *HW_TIMER0_BR = 198;        // timer 0 base register
226
    *HW_TIMER0_CR = 0x80;       // source from ioclk
227
#endif
228
 
229
    // No interrupts for now.
230
    *SERIAL1_ICR = 0x00;
231
 
232
    // Source from timer 1, 8bit chars, enable tx and rx
233
    *SERIAL1_CR = 0xc084;
234
}
235
 
236
void hal_diag_write_char_serial1(char c)
237
{
238
    register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR;
239
    register volatile cyg_uint8 *volatile tty_tx = SERIAL1_TXR;
240
 
241
    while( (*tty_status & SIO1_LSTAT_TRDY) != 0 ) continue;
242
 
243
    *tty_tx = c;
244
}
245
 
246
void hal_diag_drain_serial1(void)
247
{
248
    register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR;
249
 
250
    while( (*tty_status & SIO1_LSTAT_TRDY) != 0 ) continue;
251
}
252
 
253
void hal_diag_read_char_serial1(char *c)
254
{
255
    register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR;
256
    register volatile cyg_uint8 *volatile tty_rx = SERIAL1_RXR;
257
 
258
    while( (*tty_status & SIO1_LSTAT_RRDY) == 0 ) continue;
259
 
260
    *c = *tty_rx;
261
 
262
    // We must ack the interrupt caused by that read to avoid
263
    // confusing the GDB stub ROM.
264
    HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_1_RX );
265
}
266
 
267
#if defined(CYG_KERNEL_DIAG_SERIAL1)
268
 
269
#define hal_diag_init_serial hal_diag_init_serial1
270
#define hal_diag_write_char_serial hal_diag_write_char_serial1
271
#define hal_diag_drain_serial hal_diag_drain_serial1
272
#define hal_diag_read_char_serial hal_diag_read_char_serial1
273
 
274
#endif
275
 
276
#endif
277
 
278
/*---------------------------------------------------------------------------*/
279
 
280
#if defined(CYG_HAL_MN10300_STB_SERIAL2) || defined(CYG_KERNEL_DIAG_SERIAL2)
281
 
282
// We use serial2 on MN103002
283
#define SERIAL2_CR       ((volatile cyg_uint16 *)0xd4002020)
284
#define SERIAL2_ICR      ((volatile cyg_uint8 *) 0xd4002024)
285
#define SERIAL2_TXR      ((volatile cyg_uint8 *) 0xd4002028)
286
#define SERIAL2_RXR      ((volatile cyg_uint8 *) 0xd4002029)
287
#define SERIAL2_SR       ((volatile cyg_uint8 *) 0xd400202c)
288
#define SERIAL2_TR       ((volatile cyg_uint8 *) 0xd400202d)
289
 
290
// Timer 3 provides baud rate divisor
291
#define TIMER2_MD       ((volatile cyg_uint8 *)0xd4003003)
292
#define TIMER2_BR       ((volatile cyg_uint8 *)0xd4003013)
293
#define TIMER2_CR       ((volatile cyg_uint8 *)0xd4003023)
294
 
295
#define SIO2_LSTAT_TRDY  0x20
296
#define SIO2_LSTAT_RRDY  0x10
297
 
298
void hal_diag_init_serial2(void)
299
{
300
#if 0
301
    {
302
        int i,j;
303
        for( j = 1; j < 255; j++ )
304
        {
305
            for(i = 1; i < 127; i++)
306
            {
307
                *TIMER2_BR = j;
308
                *SERIAL2_TR = i;
309
 
310
                // Timer2 sourced from IOCLK
311
                *TIMER2_MD = 0x80;
312
 
313
                // No interrupts for now.
314
                *SERIAL2_ICR = 0x00;
315
 
316
                // Source from timer 2, 8bit chars, enable tx and rx
317
                *SERIAL2_CR = 0xc081;
318
 
319
                diag_printf("\r\n<%03d,%03d>1234567890abcdefgh<%03d,%03d>\r\n",j,i,j,i);
320
            }
321
        }
322
    }
323
#endif
324
 
325
    // 7 and 102 translate to 38400 baud.
326
    // The AM33 documentation says that these values should be 7 and 113.
327
    // I have no explanation as to why there is such a discrepancy between the
328
    // documentation and the hardware.
329
 
330
    *TIMER2_BR = 7;
331
    *SERIAL2_TR = 102;
332
 
333
    // Timer2 sourced from IOCLK
334
    *TIMER2_MD = 0x80;
335
 
336
    // No interrupts for now.
337
    *SERIAL2_ICR = 0x00;
338
 
339
    // Source from timer 3, 8bit chars, enable tx and rx
340
    *SERIAL2_CR = 0xc083;
341
 
342
}
343
 
344
void hal_diag_write_char_serial2(char c)
345
{
346
    register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR;
347
    register volatile cyg_uint8 *volatile tty_tx = SERIAL2_TXR;
348
 
349
    while( (*tty_status & SIO2_LSTAT_TRDY) != 0 ) continue;
350
 
351
    *tty_tx = c;
352
}
353
 
354
void hal_diag_drain_serial2(void)
355
{
356
    register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR;
357
 
358
    while( (*tty_status & SIO2_LSTAT_TRDY) != 0 ) continue;
359
}
360
 
361
void hal_diag_read_char_serial2(char *c)
362
{
363
    register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR;
364
    register volatile cyg_uint8 *volatile tty_rx = SERIAL2_RXR;
365
 
366
    while( (*tty_status & SIO2_LSTAT_RRDY) == 0 ) continue;
367
 
368
    *c = *tty_rx;
369
 
370
    // We must ack the interrupt caused by that read to avoid
371
    // confusing the GDB stub ROM.
372
    HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_2_RX );
373
 
374
 
375
}
376
 
377
#if defined(CYG_KERNEL_DIAG_SERIAL2)
378
 
379
#define hal_diag_init_serial hal_diag_init_serial2
380
#define hal_diag_write_char_serial hal_diag_write_char_serial2
381
#define hal_diag_drain_serial hal_diag_drain_serial2
382
#define hal_diag_read_char_serial hal_diag_read_char_serial2
383
 
384
#endif
385
 
386
#endif
387
 
388
/*---------------------------------------------------------------------------*/
389
 
390
 
391
#if defined(CYG_KERNEL_DIAG_BUFFER)
392
 
393
char hal_diag_buffer[10000];
394
int hal_diag_buffer_pos;
395
 
396
void hal_diag_init_buffer(void)
397
{
398
    hal_diag_buffer_pos = 0;
399
}
400
 
401
void hal_diag_write_char_buffer(char c)
402
{
403
    hal_diag_buffer[hal_diag_buffer_pos++] = c;
404
    if (hal_diag_buffer_pos >= sizeof(hal_diag_buffer) )
405
        hal_diag_buffer_pos = 0;
406
}
407
 
408
void hal_diag_drain_buffer(void)
409
{
410
}
411
 
412
void hal_diag_read_char_buffer(char *c)
413
{
414
    *c = '\n';
415
}
416
 
417
#define hal_diag_init_serial hal_diag_init_buffer
418
#define hal_diag_write_char_serial hal_diag_write_char_buffer
419
#define hal_diag_drain_serial hal_diag_drain_buffer
420
#define hal_diag_read_char_serial hal_diag_read_char_buffer
421
 
422
#endif
423
 
424
 
425
/*---------------------------------------------------------------------------*/
426
 
427
void hal_diag_init(void)
428
{
429
    hal_diag_init_serial();
430
}
431
 
432
void hal_diag_write_char(char c)
433
{
434
#ifdef CYG_KERNEL_DIAG_GDB
435
 
436
    static char line[100];
437
    static int pos = 0;
438
 
439
    // No need to send CRs
440
    if( c == '\r' ) return;
441
 
442
    line[pos++] = c;
443
 
444
    if( c == '\n' || pos == sizeof(line) )
445
    {
446
        // Disable interrupts. This prevents GDB trying to interrupt us
447
        // while we are in the middle of sending a packet. The serial
448
        // receive interrupt will be seen when we re-enable interrupts
449
        // later.
450
 
451
        CYG_INTERRUPT_STATE oldstate;
452
        CYG_BYTE wdcr;
453
        HAL_DISABLE_INTERRUPTS(oldstate);
454
 
455
        // Beacuse of problems with NT on the testfarm, we also have
456
        // to disable the watchdog here. This only matters in the
457
        // watchdog tests. And yes, this sends my irony meter off the
458
        // scale too.
459
 
460
        HAL_READ_UINT8( 0xC0001002, wdcr );
461
        HAL_WRITE_UINT8( 0xC0001002, wdcr&0x3F );
462
 
463
        while(1)
464
        {
465
            static char hex[] = "0123456789ABCDEF";
466
            cyg_uint8 csum = 0;
467
            int i;
468
 
469
            hal_diag_write_char_serial('$');
470
            hal_diag_write_char_serial('O');
471
            csum += 'O';
472
            for( i = 0; i < pos; i++ )
473
            {
474
                char ch = line[i];
475
                char h = hex[(ch>>4)&0xF];
476
                char l = hex[ch&0xF];
477
                hal_diag_write_char_serial(h);
478
                hal_diag_write_char_serial(l);
479
                csum += h;
480
                csum += l;
481
            }
482
            hal_diag_write_char_serial('#');
483
            hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
484
            hal_diag_write_char_serial(hex[csum&0xF]);
485
 
486
 
487
            {
488
                char c1;
489
 
490
                hal_diag_read_char_serial( &c1 );
491
 
492
                if( c1 == '+' ) break;
493
 
494
 
495
                if( cyg_hal_is_break( &c1, 1 ) )
496
                    cyg_hal_user_break( NULL );
497
 
498
            }
499
        }
500
 
501
        pos = 0;
502
 
503
        // Wait for tx buffer to drain
504
        hal_diag_drain_serial();
505
 
506
        // And re-enable interrupts
507
        HAL_RESTORE_INTERRUPTS(oldstate);
508
        HAL_WRITE_UINT8( 0xC0001002, wdcr );
509
    }
510
 
511
#else
512
    hal_diag_write_char_serial(c);
513
#endif    
514
}
515
 
516
 
517
 
518
 
519
void hal_diag_read_char(char *c)
520
{
521
    hal_diag_read_char_serial(c);
522
}
523
 
524
 
525
/*---------------------------------------------------------------------------*/
526
/* End of hal_diag.c */

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