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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): sfurman
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// Contributors:
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// Date: 2003-01-24
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// both external interrupts and clock interrupts.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#ifndef CYGONCE_HAL_HAL_INTR_H
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#define CYGONCE_HAL_HAL_INTR_H
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#include <cyg/hal/hal_arch.h>
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//--------------------------------------------------------------------------
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// OpenRISC vectors.
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// These are the exception/interrupt causes defined by the hardware.
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// These values are the ones to use for HAL_VSR_GET/SET
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// Reset
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#define CYGNUM_HAL_VECTOR_RESET 0x01
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// Bus Error - probably invalid physical address
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#define CYGNUM_HAL_VECTOR_BUS_ERROR 0x02
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// Either no matching page-table entry or protection fault
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// while executing load/store operation
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#define CYGNUM_HAL_VECTOR_DATA_PAGE_FAULT 0x03
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// Either no matching page-table entry or protection fault
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// while fetching instruction
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#define CYGNUM_HAL_VECTOR_INSTR_PAGE_FAULT 0x04
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// Tick Timer interrupt
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#define CYGNUM_HAL_VECTOR_TICK_TIMER 0x05
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// Unaligned access
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#define CYGNUM_HAL_VECTOR_UNALIGNED_ACCESS 0x06
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// Illegal instruction
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#define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 0x07
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// External Interrupt from PIC
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#define CYGNUM_HAL_VECTOR_INTERRUPT 0x08
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// D-TLB Miss
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#define CYGNUM_HAL_VECTOR_DTLB_MISS 0x09
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// I-TLB Miss
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#define CYGNUM_HAL_VECTOR_ITLB_MISS 0x0A
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// Numeric overflow, etc.
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#define CYGNUM_HAL_VECTOR_RANGE 0x0B
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// System Call
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#define CYGNUM_HAL_VECTOR_SYSTEM_CALL 0x0C
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// TRAP instruction executed
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#define CYGNUM_HAL_VECTOR_TRAP 0x0E
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#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESET
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#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_TRAP
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#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN+1)
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// Exception vectors. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
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CYGNUM_HAL_VECTOR_DTLB_MISS
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#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
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CYGNUM_HAL_VECTOR_DTLB_MISS
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#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
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CYGNUM_HAL_VECTOR_UNALIGNED_ACCESS
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#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_RANGE
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#define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_INTERRUPT
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// Min/Max exception numbers and how many there are
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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#define CYGNUM_HAL_EXCEPTION_COUNT \
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( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// Interrupts 0-31 are connected to the PIC
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#define CYGNUM_HAL_INTERRUPT_0 0
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#define CYGNUM_HAL_INTERRUPT_1 1
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#define CYGNUM_HAL_INTERRUPT_2 2
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#define CYGNUM_HAL_INTERRUPT_3 3
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#define CYGNUM_HAL_INTERRUPT_4 4
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#define CYGNUM_HAL_INTERRUPT_5 5
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#define CYGNUM_HAL_INTERRUPT_6 6
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#define CYGNUM_HAL_INTERRUPT_7 7
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#define CYGNUM_HAL_INTERRUPT_8 8
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#define CYGNUM_HAL_INTERRUPT_9 9
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#define CYGNUM_HAL_INTERRUPT_10 10
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#define CYGNUM_HAL_INTERRUPT_11 11
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#define CYGNUM_HAL_INTERRUPT_12 12
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#define CYGNUM_HAL_INTERRUPT_13 13
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#define CYGNUM_HAL_INTERRUPT_14 14
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#define CYGNUM_HAL_INTERRUPT_15 15
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#define CYGNUM_HAL_INTERRUPT_16 16
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#define CYGNUM_HAL_INTERRUPT_17 17
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#define CYGNUM_HAL_INTERRUPT_18 18
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#define CYGNUM_HAL_INTERRUPT_19 19
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#define CYGNUM_HAL_INTERRUPT_20 20
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#define CYGNUM_HAL_INTERRUPT_21 21
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#define CYGNUM_HAL_INTERRUPT_22 22
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#define CYGNUM_HAL_INTERRUPT_23 23
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#define CYGNUM_HAL_INTERRUPT_24 24
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#define CYGNUM_HAL_INTERRUPT_25 25
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#define CYGNUM_HAL_INTERRUPT_26 26
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#define CYGNUM_HAL_INTERRUPT_27 27
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#define CYGNUM_HAL_INTERRUPT_28 28
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#define CYGNUM_HAL_INTERRUPT_29 29
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#define CYGNUM_HAL_INTERRUPT_30 30
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#define CYGNUM_HAL_INTERRUPT_31 31
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// By SW convention, interrupt #32 is the tick timer
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#define CYGNUM_HAL_INTERRUPT_32 32
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// The interrupt vector used by the RTC, aka tick timer
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_32
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 32
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#define CYGNUM_HAL_ISR_COUNT 33
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#endif
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#ifndef __ASSEMBLER__
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// Static data used by HAL
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// ISR tables
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externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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// VSR table
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externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];
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//--------------------------------------------------------------------------
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// Default ISR
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// The #define is used to test whether this routine exists, and to allow
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// us to call it.
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externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_DEFAULT_ISR hal_default_isr
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//--------------------------------------------------------------------------
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// Interrupt state storage
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typedef cyg_uint32 CYG_INTERRUPT_STATE;
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//--------------------------------------------------------------------------
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// Interrupt control macros
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#ifndef CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
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// Clear both tick timer and external interrupts in the Supervisor Register
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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_old_ = MFSPR(SPR_SR); \
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MTSPR(SPR_SR, _old_ & ~(SPR_SR_IEE|SPR_SR_TEE)); \
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CYG_MACRO_END
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// Enable both tick timer and external interrupts in the Supervisor Register
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#define HAL_ENABLE_INTERRUPTS() \
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MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_IEE|SPR_SR_TEE))
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// Copy interrupt flags from argument into Supervisor Register
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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cyg_uint32 t1,t2; \
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t1 = MFSPR(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE); \
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t2 = (_old_) & (SPR_SR_IEE|SPR_SR_TEE); \
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MTSPR(SPR_SR, t1 | t2); \
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CYG_MACRO_END
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#define HAL_QUERY_INTERRUPTS( _state_ ) \
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CYG_MACRO_START \
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_state = MFSPR(SPR_SR); \
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CYG_MACRO_END
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#endif // CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
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//--------------------------------------------------------------------------
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// Routine to execute DSRs using separate interrupt stack
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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externC void hal_interrupt_stack_call_pending_DSRs(void);
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#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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hal_interrupt_stack_call_pending_DSRs()
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// these are offered solely for stack usage testing
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// if they are not defined, then there is no interrupt stack.
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#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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// use them to declare these extern however you want:
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// extern char HAL_INTERRUPT_STACK_BASE[];
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// extern char HAL_INTERRUPT_STACK_TOP[];
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// is recommended
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#endif
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//--------------------------------------------------------------------------
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| 270 |
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// Vector translation.
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// For chained interrupts we only have a single vector though which all
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// are passed. For unchained interrupts we have a vector per interrupt.
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#ifndef HAL_TRANSLATE_VECTOR
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#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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#else
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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#endif
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#endif
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//--------------------------------------------------------------------------
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| 289 |
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// Interrupt and VSR attachment macros
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| 291 |
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#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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CYG_MACRO_START \
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cyg_uint32 _index_; \
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HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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\
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if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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(_state_) = 0; \
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else \
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(_state_) = 1; \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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{ \
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cyg_uint32 _index_; \
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HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
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\
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if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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{ \
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hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
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hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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} \
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}
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#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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{ \
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| 317 |
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cyg_uint32 _index_; \
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HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
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\
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if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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{ \
|
| 322 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
|
| 323 |
|
|
hal_interrupt_data[_index_] = 0; \
|
| 324 |
|
|
hal_interrupt_objects[_index_] = 0; \
|
| 325 |
|
|
} \
|
| 326 |
|
|
}
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| 327 |
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|
| 328 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 329 |
|
|
*(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
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| 330 |
|
|
|
| 331 |
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|
|
| 332 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
|
| 333 |
|
|
if( (void*)_poldvsr_ != NULL) \
|
| 334 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
|
| 335 |
|
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hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 336 |
|
|
CYG_MACRO_END
|
| 337 |
|
|
|
| 338 |
|
|
// This is an ugly name, but what it means is: grab the VSR back to eCos
|
| 339 |
|
|
// internal handling, or if you like, the default handler. But if
|
| 340 |
|
|
// cooperating with GDB and CygMon, the default behaviour is to pass most
|
| 341 |
|
|
// exceptions to CygMon. This macro undoes that so that eCos handles the
|
| 342 |
|
|
// exception. So use it with care.
|
| 343 |
|
|
|
| 344 |
|
|
externC void cyg_hal_default_exception_vsr(void);
|
| 345 |
|
|
externC void cyg_hal_default_interrupt_vsr(void);
|
| 346 |
|
|
|
| 347 |
|
|
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
|
| 348 |
|
|
HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
|
| 349 |
|
|
? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
|
| 350 |
|
|
: (CYG_ADDRESS)cyg_hal_default_exception_vsr, \
|
| 351 |
|
|
_poldvsr_ ); \
|
| 352 |
|
|
CYG_MACRO_END
|
| 353 |
|
|
|
| 354 |
|
|
//--------------------------------------------------------------------------
|
| 355 |
|
|
// Interrupt controller access
|
| 356 |
|
|
|
| 357 |
|
|
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 358 |
|
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 359 |
|
|
|
| 360 |
|
|
// Mask (disable) interrupts from specified source
|
| 361 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 362 |
|
|
CYG_MACRO_START \
|
| 363 |
|
|
int mask; \
|
| 364 |
|
|
if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
|
| 365 |
|
|
/* The tick timer interrupt isn't */ \
|
| 366 |
|
|
/* controlled by the PIC; It has its own*/\
|
| 367 |
|
|
/* enable bit in the SR. */ \
|
| 368 |
|
|
MTSPR(SPR_SR, MFSPR(SPR_SR)& ~SPR_SR_TEE);\
|
| 369 |
|
|
} else { \
|
| 370 |
|
|
mask = ~(1 << (_vector_)); \
|
| 371 |
|
|
MTSPR(SPR_PICMR, MFSPR(SPR_PICMR)& mask); \
|
| 372 |
|
|
} \
|
| 373 |
|
|
CYG_MACRO_END
|
| 374 |
|
|
|
| 375 |
|
|
// Allow interrupts from specified source
|
| 376 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 377 |
|
|
CYG_MACRO_START \
|
| 378 |
|
|
int bit; \
|
| 379 |
|
|
if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
|
| 380 |
|
|
/* The tick timer interrupt isn't */ \
|
| 381 |
|
|
/* controlled by the PIC; It has its own*/\
|
| 382 |
|
|
/* enable bit in the SR. */ \
|
| 383 |
|
|
MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_TEE);\
|
| 384 |
|
|
} else { \
|
| 385 |
|
|
bit = (1 << (_vector_)); \
|
| 386 |
|
|
MTSPR(SPR_PICMR, MFSPR(SPR_PICMR) | bit); \
|
| 387 |
|
|
} \
|
| 388 |
|
|
CYG_MACRO_END
|
| 389 |
|
|
|
| 390 |
|
|
// Reset interrupt request in the PIC for specified device
|
| 391 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 392 |
|
|
CYG_MACRO_START \
|
| 393 |
|
|
int mask; \
|
| 394 |
|
|
if ((_vector_) != CYGNUM_HAL_INTERRUPT_RTC) { \
|
| 395 |
|
|
mask = ~(1 << (_vector_)); \
|
| 396 |
|
|
MTSPR(SPR_PICSR, MFSPR(SPR_PICSR) & mask);\
|
| 397 |
|
|
} \
|
| 398 |
|
|
CYG_MACRO_END
|
| 399 |
|
|
|
| 400 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) CYG_EMPTY_STATEMENT
|
| 401 |
|
|
|
| 402 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) CYG_EMPTY_STATEMENT
|
| 403 |
|
|
|
| 404 |
|
|
#endif
|
| 405 |
|
|
|
| 406 |
|
|
//--------------------------------------------------------------------------
|
| 407 |
|
|
// Clock control.
|
| 408 |
|
|
|
| 409 |
|
|
externC CYG_WORD32 cyg_hal_clock_period;
|
| 410 |
|
|
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
|
| 411 |
|
|
|
| 412 |
|
|
// Start tick timer interrupts
|
| 413 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 414 |
|
|
CYG_MACRO_START \
|
| 415 |
|
|
{ \
|
| 416 |
|
|
int ttmr_new = _period_ | 0x60000000; \
|
| 417 |
|
|
MTSPR(SPR_TTMR, 0); \
|
| 418 |
|
|
MTSPR(SPR_TTCR, 0); \
|
| 419 |
|
|
MTSPR(SPR_TTMR, ttmr_new); \
|
| 420 |
|
|
cyg_hal_clock_period = _period_; \
|
| 421 |
|
|
} \
|
| 422 |
|
|
CYG_MACRO_END
|
| 423 |
|
|
|
| 424 |
|
|
// Acknowledge clock timer interrupt
|
| 425 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
| 426 |
|
|
CYG_MACRO_START \
|
| 427 |
|
|
int ttmr_new = _period_ | 0x60000000; \
|
| 428 |
|
|
MTSPR(SPR_TTMR, ttmr_new); \
|
| 429 |
|
|
CYG_MACRO_END
|
| 430 |
|
|
|
| 431 |
|
|
// Read the current value of the tick timer
|
| 432 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 433 |
|
|
CYG_MACRO_START \
|
| 434 |
|
|
*(_pvalue_) = MFSPR(SPR_TTCR); \
|
| 435 |
|
|
CYG_MACRO_END
|
| 436 |
|
|
|
| 437 |
|
|
#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
|
| 438 |
|
|
!defined(HAL_CLOCK_LATENCY)
|
| 439 |
|
|
#define HAL_CLOCK_LATENCY( _pvalue_ ) \
|
| 440 |
|
|
CYG_MACRO_START \
|
| 441 |
|
|
register CYG_WORD32 _cval_; \
|
| 442 |
|
|
HAL_CLOCK_READ(&_cval_); \
|
| 443 |
|
|
*(_pvalue_) = _cval_ - cyg_hal_clock_period; \
|
| 444 |
|
|
CYG_MACRO_END
|
| 445 |
|
|
#endif
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
//--------------------------------------------------------------------------
|
| 449 |
|
|
// Microsecond delay function provided in hal_misc.c
|
| 450 |
|
|
externC void hal_delay_us(int us);
|
| 451 |
|
|
|
| 452 |
|
|
#define HAL_DELAY_US(n) hal_delay_us(n)
|
| 453 |
|
|
|
| 454 |
|
|
#endif /* #ifndef __ASSEMBLER__ */
|
| 455 |
|
|
|
| 456 |
|
|
//--------------------------------------------------------------------------
|
| 457 |
|
|
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
|
| 458 |
|
|
// End of hal_intr.h
|
