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#ifndef CYGONCE_HAL_HAL_IO_H

#define CYGONCE_HAL_HAL_IO_H

//=============================================================================

//

//      hal_io.h

//

//      HAL device IO register support.

//

//=============================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

//

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// for more details.

//

// You should have received a copy of the GNU General Public License along

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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

//

// As a special exception, if other files instantiate templates or use macros

// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

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//

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// -------------------------------------------

//####ECOSGPLCOPYRIGHTEND####

//=============================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):   nickg

// Contributors:        nickg

// Date:        2003-02-28

// Purpose:     Define IO register support

// Description: The macros defined here provide the HAL APIs for handling

//              device IO control registers.

//              

// Usage:

//              #include <cyg/hal/hal_io.h>

//              ...

//              

//

//####DESCRIPTIONEND####

//

//=============================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>

//#include <cyg/hal/plf_io.h>

//-----------------------------------------------------------------------------

// IO Register address.

// This type is for recording the address of an IO register.

typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;

//-----------------------------------------------------------------------------

// HAL IO macros.

#ifndef HAL_IO_MACROS_DEFINED

//-----------------------------------------------------------------------------

// BYTE Register access.

// Individual and vectorized access to 8 bit registers.

#define HAL_READ_UINT8( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_BYTE *)(_register_)))

#define HAL_WRITE_UINT8( _register_, _value_ ) \

        (*((volatile CYG_BYTE *)(_register_)) = (_value_))

#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \

}

#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \

}

//-----------------------------------------------------------------------------

// 16 bit access.

// Individual and vectorized access to 16 bit registers.

#define HAL_READ_UINT16( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))

#define HAL_WRITE_UINT16( _register_, _value_ ) \

        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))

#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \

}

#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \

}

//-----------------------------------------------------------------------------

// 32 bit access.

// Individual and vectorized access to 32 bit registers.

#define HAL_READ_UINT32( _register_, _value_ ) \

        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))

#define HAL_WRITE_UINT32( _register_, _value_ ) \

        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))

#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \

}

#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \

{                                                                       \

    cyg_count32 _i_,_j_;                                                \

    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \

        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \

}

#define HAL_IO_MACROS_DEFINED

#endif

//-----------------------------------------------------------------------------

#endif // ifndef CYGONCE_HAL_HAL_IO_H

// End of hal_io.h