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##=============================================================================
2
##
3
##      adder.S
4
##
5
##      ADDER board hardware setup
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
## Copyright (C) 2002 Gary Thomas
13
##
14
## eCos is free software; you can redistribute it and/or modify it under
15
## the terms of the GNU General Public License as published by the Free
16
## Software Foundation; either version 2 or (at your option) any later version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License along
24
## with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26
##
27
## As a special exception, if other files instantiate templates or use macros
28
## or inline functions from this file, or you compile this file and link it
29
## with other works to produce a work based on this file, this file does not
30
## by itself cause the resulting work to be covered by the GNU General Public
31
## License. However the source code for this file must still be made available
32
## in accordance with section (3) of the GNU General Public License.
33
##
34
## This exception does not invalidate any other reasons why a work based on
35
## this file might be covered by the GNU General Public License.
36
##
37
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38
## at http://sources.redhat.com/ecos/ecos-license/
39
## -------------------------------------------
40
#####ECOSGPLCOPYRIGHTEND####
41
##=============================================================================
42
#######DESCRIPTIONBEGIN####
43
##
44
## Author(s):   hmt
45
## Contributors:hmt, gthomas
46
## Date:        1999-06-08
47
## Purpose:     ADDER board hardware setup
48
## Description: This file contains any code needed to initialize the
49
##              hardware on a ADDER PPC860 board.
50
##
51
######DESCRIPTIONEND####
52
##
53
##=============================================================================
54
 
55
#include 
56
 
57
#include                /* register symbols et al */
58
#include                /* on-chip resource layout, special */
59
                                        /* registers, IMM layout...         */
60
#include        /* more of the same */
61
 
62
#------------------------------------------------------------------------------
63
# this is controlled with one define for tidiness:
64
# (and it is undefined by default)
65
 
66
//#define CYGPRI_RAM_START_PROGRAMS_UPMS
67
 
68
#if defined(CYG_HAL_STARTUP_ROM) \
69
 || defined(CYG_HAL_STARTUP_ROMRAM) \
70
 || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
71
# define CYGPRI_DO_PROGRAM_UPMS
72
#endif
73
 
74
/* The intention is that we only set up the UPMs in ROM start, be it actual
75
 * ROM application start or Stub ROMs that we built from the same sources.
76
 *
77
 * The alternative approach - in which we have reliability doubts - is to
78
 * program the UPMs with *old* timing data in StubROM start, then
79
 * *reprogram* them with *new* timing data in RAM start - and of course
80
 * program with *new* timing data in plain ROM application start.
81
 * (Re-programming from new to new timing data fails - hence the suspicion
82
 * of reprogramming _at_all_, hence this private configuration)
83
 *
84
 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
85
 * - programming the UPMs exactly once - is obtained.  Define it to get the
86
 * latter, untrusted behaviour.
87
 */
88
 
89
#------------------------------------------------------------------------------
90
 
91
FUNC_START( hal_hardware_init )
92
 
93
        # Throughout this routine, r4 is the base address of the control
94
        # registers.  r3 and r5 are scratch in general.
95
 
96
        lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
97
        mtspr   CYGARC_REG_IMMR,r4
98
 
99
#define CACHE_UNLOCKALL         0x0a00
100
#define CACHE_DISABLE           0x0400
101
#define CACHE_INVALIDATEALL     0x0c00
102
#define CACHE_ENABLE            0x0200
103
#define CACHE_ENABLEBIT         0x8000
104
 
105
#define CACHE_FORCEWRITETHROUGH 0x0100
106
#define CACHE_NOWRITETHROUGH    0x0300
107
#define CACHE_CLEAR_LE_SWAP     0x0700
108
 
109
        # DATA CACHE
110
        mfspr   r3,CYGARC_REG_DC_CST            /* clear error bits */
111
        lis     r3,CACHE_UNLOCKALL
112
        sync
113
        mtspr   CYGARC_REG_DC_CST,r3            /* unlock all lines */
114
 
115
        lis     r3,CACHE_INVALIDATEALL
116
        sync
117
        mtspr   CYGARC_REG_DC_CST,r3            /* invalidate all lines */
118
 
119
        lis     r3,CACHE_DISABLE
120
        sync
121
        mtspr   CYGARC_REG_DC_CST,r3            /* disable */
122
 
123
        lis     r3,CACHE_FORCEWRITETHROUGH
124
        sync
125
        mtspr   CYGARC_REG_DC_CST,r3            /* set force-writethrough mode */
126
 
127
        lis     r3,CACHE_CLEAR_LE_SWAP
128
        sync
129
        mtspr   CYGARC_REG_DC_CST,r3            /* clear little-endian swap mode */
130
        /* (dunno what this is, but it sounds like a bad thing) */
131
 
132
        # INSTRUCTION CACHE (no writeback modes)
133
        mfspr   r3,CYGARC_REG_IC_CST            /* clear error bits */
134
        lis     r3,CACHE_UNLOCKALL
135
        mtspr   CYGARC_REG_IC_CST,r3            /* unlock all lines */
136
        isync
137
        lis     r3,CACHE_INVALIDATEALL
138
        mtspr   CYGARC_REG_IC_CST,r3            /* invalidate all lines */
139
        isync
140
        lis     r3,CACHE_DISABLE
141
        mtspr   CYGARC_REG_IC_CST,r3            /* disable */
142
        isync
143
 
144
        sync
145
 
146
        /*
147
         * SIU Initialization.
148
         */
149
        lwi     r3,0x00610400
150
        stw     r3,SIUMCR(r4)
151
 
152
#ifdef CYG_HAL_STARTUP_ROMRAM
153
// Need to set the PC into the FLASH (ROM) before the address map changes
154
        lwi     r3,10f
155
        lwi     r5,0xFE000000
156
        or      r3,r3,r5
157
        mtctr   r3
158
        bctr
159
10:
160
#endif
161
 
162
        /*
163
         * Enable bus monitor. Disable Watchdog timer.
164
         */
165
        lwi     r3,0xffffff88
166
        stw     r3,SYPCR(r4)
167
 
168
        /*
169
         * Clear REFA & REFB. Enable but freeze timebase.
170
         */
171
        lwi     r3,0x0000            // FIXME:   should this be 0x0000 or 0x00C2
172
        sth     r3,TBSCR(r4)
173
 
174
        /*
175
         * Unlock some RTC registers (see section 5.11.2)
176
         */
177
        lwi     r3,0x55ccaa33
178
        stw     r3,RTCSCK(r4)
179
        stw     r3,RTCK(r4)
180
        stw     r3,RTSECK(r4)
181
        stw     r3,RTCALK(r4)
182
 
183
        /*
184
         * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
185
         */
186
        li      r3,0x0000            // FIXME:   should this be 0x0000 or 0x00C3
187
        sth     r3,RTCSC(r4)
188
 
189
        /*
190
         * Clear periodic timer interrupt status.
191
         * Enable periodic timer and stop it on freeze.
192
         */
193
        li      r3,0x0001            // FIXME:   should this be 0x0001 or 0x0083
194
        sth     r3,PISCR(r4)
195
 
196
#ifdef CYGPRI_DO_PROGRAM_UPMS
197
        /*
198
         * Perform UPM programming by writing to its 64 RAM locations.
199
         * Note that UPM initialization must be done before the Bank Register
200
         * initialization. Otherwise, system may hang when writing to Bank
201
         * Registers in certain cases.
202
         */
203
        lis     r5,__upmtbl_start@h
204
        ori     r5,r5,__upmtbl_start@l
205
        lis     r6,__upmtbl_end@h
206
        ori     r6,r6,__upmtbl_end@l
207
        sub     r7,r6,r5      /* size of table */
208
        srawi   r7,r7,2       /* in words */
209
 
210
        li      r6,0x00000000     /* Command - OP=Write, UPMA, MAD=0 */
211
    1:
212
        lwz     r3,0(r5)      /* get data from table */
213
        stw     r3,MDR(r4)    /* store the data to MD register */
214
        stw     r6,MCR(r4)    /* issue command to MCR register */
215
        addi    r5,r5,4       /* next entry in the table */
216
        addi    r6,r6,1       /* next MAD address */
217
        cmpw    r6,r7         /* done yet ? */
218
        blt     1b
219
#endif // CYGPRI_DO_PROGRAM_UPMS
220
 
221
        /*
222
         * Set refresh timer prescaler to divide by 8.
223
         */
224
        li      r3,PTP_DIV32
225
        sth     r3,MPTPR(r4)
226
 
227
        /*
228
         * See Table 15-16 MPC860 User's Manual.
229
         *
230
// Set the value of Machine A Mode Register (MAMR) to $5E802114.
231
//      Field PTA (bits 0-7) = 94
232
//      Field PTAE (bit 8) = 1
233
//      Field AMA (bits 9-11) = 0
234
//      Field Reserved (bit 12) = 0
235
//      Field DSA (bits 13-14) = 0
236
//      Field Reserved (bit 15) = 0
237
//      Field G0CLA (bits 16-18) = 1
238
//      Field GPL_A4DIS (bit 19) = 0
239
//      Field RLFA (bits 20-23) = 1
240
//      Field WLFA (bits 24-27) = 1
241
//      Field TLFA (bits 28-31) = 4
242
         */
243
 
244
//
245
// PTA field is (System Clock in MHz * Refresh rate in us) / Prescale
246
// e.g.  ((14*3.6864)*62.5)/32 => 100.8 => 101
247
//
248
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47)
249
#define PLPRCR_PTX 0x00C // (47MHz/3.6864MHz)-1
250
#define MAMR_PTA 94
251
#endif
252
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 51)
253
#define PLPRCR_PTX 0x00D // (51.6MHz/3.6864MHz)-1
254
#define MAMR_PTA 101
255
#endif
256
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 55)
257
#define PLPRCR_PTX 0x00E // (55.3MHz/3.6864MHz)-1
258
#define MAMR_PTA 108
259
#endif
260
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 59)
261
#define PLPRCR_PTX 0x00F // (58.9MHz/3.6864MHz)-1
262
#define MAMR_PTA 116
263
#endif
264
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 63)
265
#define PLPRCR_PTX 0x010 // (62.7MHz/3.6864MHz)-1
266
#define MAMR_PTA 123
267
#endif
268
//#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF)
269
        lwi     r3,0x00802114|(MAMR_PTA<<24)
270
        stw     r3,MAMR(r4)
271
        stw     r3,MBMR(r4)
272
 
273
        /*
274
         * Base Register initialization.
275
         */
276
 
277
        /* BOOT ROM */
278
        lwi     r3,0xFE000801   # 16-bit, GPCM
279
        lwi     r5,0xFF800774   # 7 wait states, up to 8MB
280
        stw     r3,BR0(r4)
281
        stw     r5,OR0(r4)
282
 
283
        /* Misc I/O, 16 bit port */
284
        lwi     r3,0xFA100801
285
        lwi     r5,0xFFFF8730
286
        stw     r3,BR2(r4)
287
        stw     r5,OR2(r4)
288
 
289
        /* ONBOARD DRAM */
290
        lwi     r3,0x00000081   # 32-bit, UPMA
291
        lwi     r5,0xFF800E00
292
        stw     r3,BR1(r4)
293
        stw     r5,OR1(r4)
294
 
295
        /* DRAM DIMM BANK1 */
296
        lwi     r3,0x00000080   # 32-bit, UPMA, INVALID
297
        lwi     r5,0xFFFF87FC
298
        stw     r3,BR3(r4)
299
        stw     r5,OR3(r4)
300
 
301
#if 0
302
        /* NVRAM */
303
        lwi     r3,0xfa000401   # 8-bit, GPCM
304
        lwi     r5,0xffe00930
305
        stw     r3,BR4(r4)
306
        stw     r5,OR4(r4)
307
 
308
        /* PCI BRIDGE MEM/IO */
309
        lwi     r3,0x80000001   # 32-bit, GPCM
310
        lwi     r5,0xa0000108
311
        stw     r3,BR5(r4)
312
        stw     r5,OR5(r4)
313
 
314
        /* PCI BRIDGE REGISTERS */
315
        lwi     r3,0xfa210001   # 32-bit, GPCM
316
        lwi     r5,0xffff0108
317
        stw     r3,BR6(r4)
318
        stw     r5,OR6(r4)
319
 
320
        /* FLASH */
321
        lwi     r3,0xfc000001   # 32-bit, GPCM
322
        lwi     r5,0xff800940
323
        stw     r3,BR7(r4)
324
        stw     r5,OR7(r4)
325
#endif
326
 
327
        /*
328
         *  SYSTEM CLOCK CONTROL REGISTER
329
// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
330
//      Field Reserved (bit 0) = 0
331
//      Field COM (bits 1-2) = 0
332
//      Field Reserved (bits 3-5) = 0
333
//      Field TBS (bit 6) = 0
334
//      Field RTDIV (bit 7) = 0
335
//      Field RTSEL (bit 8) = 0
336
//      Field CRQEN (bit 9) = 1
337
//      Field PRQEN (bit 10) = 0
338
//      Field Reserved (bits 11-12) = 0
339
//      Field EBDF (bits 13-14) = 0
340
//      Field Reserved (bits 15-16) = 0
341
//      Field DFSYNC (bits 17-18) = 0
342
//      Field DFBRG (bits 19-20) = 0
343
//      Field DFNL (bits 21-23) = 0
344
//      Field DFNH (bits 24-26) = 0
345
//      Field Reserved (bits 27-31) = 0
346
         */
347
        lwi     r3,0x00400000
348
        stw     r3,SCCR(r4)
349
 
350
        /*
351
         *  PLL, LOW POWER, AND RESET CONTROL REGISTER
352
// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
353
//      Field MF (bits 0-11) = 12
354
//      Field Reserved (bits 12-15) = 0
355
//      Field SPLSS (bit 16) = 0
356
//      Field TEXPS (bit 17) = 1
357
//      Field Reserved (bit 18) = 0
358
//      Field TMIST (bit 19) = 0
359
//      Field Reserved (bit 20) = 0
360
//      Field CSRC (bit 21) = 0
361
//      Field LPM (bits 22-23) = 0
362
//      Field CSR (bit 24) = 0
363
//      Field LOLRE (bit 25) = 0
364
//      Field FIOPD (bit 26) = 0
365
//      Field Reserved (bits 27-31) = 0
366
         */
367
        lwi     r3,0x04000|(PLPRCR_PTX<<20)
368
        stw     r3,PLPRCR(r4)
369
 
370
        lwi     r3,0x40000
371
        mtctr   r3
372
10:     nop
373
        bdnz    10b
374
 
375
        /* SDRAM Initialization Sequence, UPMA, CS1 */
376
        li      r3,0
377
        stw     r3,MAR(r4)
378
 
379
        lwi     r3,0x80002115;  /* run precharge from loc 21 (0x15) */
380
        stw     r3,MCR(r4)
381
 
382
        lwi     r3,0x80002830;  /* run refresh 8 times */
383
        stw     r3,MCR(r4)
384
 
385
        lwi     r3,0x88;        /* MR 88 for high range */
386
        stw     r3,MAR(r4)
387
 
388
        lwi     r3,0x80002116;  /* run MRS pattern from loc 22 (0x16) */
389
        stw     r3,MCR(r4)
390
 
391
        # mask interrupt sources in the SIU
392
        lis     r2,0
393
        lwi     r3,CYGARC_REG_IMM_SIMASK
394
        stw     r2,0(r3)
395
 
396
        # set the decrementer to maxint
397
        lwi     r2,0
398
        not     r2,r2
399
        mtdec   r2
400
 
401
        # and enable the timebase and decrementer to make sure
402
        li      r2,1                            # TBEnable and not TBFreeze
403
        lwi     r3,CYGARC_REG_IMM_TBSCR
404
        sth     r2,0(r3)
405
 
406
#ifdef CYG_HAL_STARTUP_ROM
407
        # move return address to where the ROM is
408
        mflr    r3
409
        lwi     r4,0x00FFFFFF        // CAUTION!! Assumes only low 16M for ROM
410
        and     r3,r3,r4
411
        oris    r3,r3,CYGMEM_REGION_rom>>16
412
        mtlr    r3
413
#endif
414
 
415
#ifdef CYG_HAL_STARTUP_ROMRAM
416
        // Copy image from ROM to RAM
417
        mflr    r3
418
        lwi     r4,0xFE000000
419
        lwi     r5,0x01FFFFFF   // ROM/FLASH base
420
        and     r3,r3,r5        // segment relative
421
        lwi     r6,_hal_hardware_init_done
422
        mtlr    r6
423
        sub     r6,r3,r6        // Absolute address
424
        add     r6,r6,r4        // FLASH address
425
        lwi     r7,0            // where to copy to
426
        lwi     r8,__ram_data_end
427
10:     lwz     r5,0(r6)
428
        stw     r5,0(r7)
429
        addi    r6,r6,4
430
        addi    r7,r7,4
431
        cmplw   r7,r8
432
        bne     10b
433
#endif
434
 
435
        blr
436
FUNC_END( hal_hardware_init )
437
 
438
 
439
#ifdef CYGPRI_DO_PROGRAM_UPMS
440
# -------------------------------------------------------------------------
441
# this table initializes the User Programmable Machine (UPM) nastiness
442
# in the QUICC to control DRAM timing.
443
 
444
__upmtbl_start:
445
// single read   (offset 0x00 in upm ram)
446
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00
447
       .long   0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04
448
// burst read    (offset 0x08 in upm ram)
449
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00
450
       .long   0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44
451
       .long   0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35
452
       .long   0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35
453
// single write  (offset 0x18 in upm ram)
454
       .long   0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47
455
       .long   0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
456
// burst write   (offset 0x20 in upm ram)
457
       .long   0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
458
       .long   0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04
459
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
460
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
461
// refresh       (offset 0x30 in upm ram)
462
       .long   0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04
463
       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
464
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
465
// exception     (offset 0x3C in upm ram)
466
       .long   0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
467
__upmtbl_end:
468
#endif // CYGPRI_DO_PROGRAM_UPMS
469
 
470
#------------------------------------------------------------------------------
471
# end of adder.S

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