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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [cme555/] [v2_0/] [src/] [hal_diag.c] - Blame information for rev 174

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//=============================================================================
2
//
3
//      hal_diag.c
4
//
5
//      HAL diagnostic output code
6
//
7
//=============================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//=============================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):    Bob Koninckx
44
// Contributors: Bob Koninckx
45
// Date:         2001-12-11
46
// Purpose:      HAL diagnostic output
47
// Description:  Implementations of HAL diagnostic output support.
48
//
49
//####DESCRIPTIONEND####
50
//
51
//=============================================================================
52
 
53
#include <pkgconf/hal.h>
54
 
55
#include <cyg/hal/hal_diag.h>           // our header.
56
 
57
#include <cyg/infra/cyg_type.h>         // base types, externC
58
#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
59
#include <cyg/hal/hal_misc.h>           // Helper functions
60
#include <cyg/hal/hal_io.h>             // IO macros
61
#include <cyg/hal/hal_intr.h>           // Interrupt macros
62
 
63
#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP
64
#include <cyg/hal/hal_if.h>             // Calling-if API
65
 
66
 
67
static void cyg_hal_plf_serial_init(void);
68
 
69
void
70
cyg_hal_plf_comms_init(void)
71
{
72
    static int initialized = 0;
73
 
74
    if (initialized)
75
        return;
76
 
77
    initialized = 1;
78
 
79
    cyg_hal_plf_serial_init();
80
}
81
 
82
//=============================================================================
83
// Serial driver
84
//=============================================================================
85
 
86
//-----------------------------------------------------------------------------
87
// There are two serial ports.
88
#define CYG_DEV_SERIAL_BASE_A    0x305008 // SCI0
89
#define CYG_DEV_SERIAL_BASE_B    0x305020 // SCI1
90
 
91
//-----------------------------------------------------------------------------
92
// Define CYG_DEVICE_SERIAL_RS232_SCIBR
93
// Default baudrate is 38400
94
// These values are calculated for a 40Mhz clock frequency
95
// This should be enough, we did not provide clock frequency as a configuration 
96
// option anyway
97
#define CYG_DEV_SERIAL_RS232_SCxBR_300    4167
98
#define CYG_DEV_SERIAL_RS232_SCxBR_600    2083
99
#define CYG_DEV_SERIAL_RS232_SCxBR_1200   1042
100
#define CYG_DEV_SERIAL_RS232_SCxBR_2400    521
101
#define CYG_DEV_SERIAL_RS232_SCxBR_4800    260
102
#define CYG_DEV_SERIAL_RS232_SCxBR_9600    130 
103
#define CYG_DEV_SERIAL_RS232_SCxBR_14400    87
104
#define CYG_DEV_SERIAL_RS232_SCxBR_19200    65
105
#define CYG_DEV_SERIAL_RS232_SCxBR_28800    43
106
#define CYG_DEV_SERIAL_RS232_SCxBR_38400    33
107
#define CYG_DEV_SERIAL_RS232_SCxBR_57600    22
108
#define CYG_DEV_SERIAL_RS232_SCxBR_115200   11
109
 
110
//-----------------------------------------------------------------------------
111
// Define the serial registers.
112
#define CYG_DEV_SERIAL_RS232_SCCR0 0x00
113
#define CYG_DEV_SERIAL_RS232_SCCR1 0x01
114
#define CYG_DEV_SERIAL_RS232_SCSR  0x02
115
#define CYG_DEV_SERIAL_RS232_SCDR  0x03
116
 
117
#define SCCR0_OTHR   0x8000 // Select baud rate other than system clock
118
#define SCCR0_LINKBD 0x4000 // Link baud
119
#define SCCR0_SCxBR  0x1fff // SCI baud rate
120
 
121
#define SCCR1_LOOPS  0x4000 // Loop mode
122
#define SCCR1_WOMS   0x2000 // Wired or for SCI pins
123
#define SCCR1_ILT    0x1000 // Idle line detect type
124
#define SCCR1_PT     0x0800 // Parity type (0 = Odd, 1 = Even)
125
#define SCCR1_PE     0x0400 // Parity enable
126
#define SCCR1_M      0x0200 // Mode select (0 = 10 bit frame, 1 = 11 bit frame)
127
#define SCCR1_WAKE   0x0100 // Wakeup by address mark
128
#define SCCR1_TIE    0x0080 // Transmit interrupt enable
129
#define SCCR1_TCIE   0x0040 // Transmit complete interrupt enable
130
#define SCCR1_RIE    0x0020 // Receiver interrupt enable
131
#define SCCR1_ILIE   0x0010 // Idle line interrupt enable
132
#define SCCR1_TE     0x0008 // Transmiter enable
133
#define SCCR1_RE     0x0004 // Receiver enable
134
#define SCCR1_RWU    0x0002 // Receiver wakeup
135
#define SCCR1_SBK    0x0001 // Send break
136
 
137
#define SCSR_TDRE    0x0100 // Transmit data register empty
138
#define SCSR_TC      0x0080 // Transmit complete
139
#define SCSR_RDRF    0x0040 // Receive data register full
140
#define SCSR_RAF     0x0020 // Receive active flag
141
#define SCSR_IDLE    0x0010 // Idle line detected
142
#define SCSR_OR      0x0008 // Overrun error
143
#define SCSR_NF      0x0004 // Noise error flag
144
#define SCSR_FE      0x0002 // Framing error
145
#define SCSR_PF      0x0001 // Parity error
146
 
147
//-----------------------------------------------------------------------------
148
typedef struct {
149
    cyg_uint16*  base;
150
    cyg_int32    msec_timeout;
151
    int          siu_vector;
152
    int          imb3_vector;
153
    unsigned int level;
154
    int          baud_rate;
155
} channel_data_t;
156
 
157
//-----------------------------------------------------------------------------
158
static void
159
init_serial_channel(const channel_data_t* __ch_data)
160
{
161
    cyg_uint16 * base = __ch_data->base;
162
    cyg_uint16 br;
163
 
164
    switch(__ch_data->baud_rate)
165
    {
166
      case 300:
167
        br = CYG_DEV_SERIAL_RS232_SCxBR_300;
168
        break;
169
      case 600:
170
        br = CYG_DEV_SERIAL_RS232_SCxBR_600;
171
        break;
172
      case 1200:
173
        br = CYG_DEV_SERIAL_RS232_SCxBR_1200;
174
        break;
175
      case 2400:
176
        br = CYG_DEV_SERIAL_RS232_SCxBR_2400;
177
        break;
178
      case 4800:
179
        br = CYG_DEV_SERIAL_RS232_SCxBR_4800;
180
        break;
181
      case 9600:
182
        br = CYG_DEV_SERIAL_RS232_SCxBR_9600;
183
        break;
184
      case 14400:
185
        br = CYG_DEV_SERIAL_RS232_SCxBR_14400;
186
        break;
187
      case 19200:
188
        br = CYG_DEV_SERIAL_RS232_SCxBR_19200;
189
        break;
190
      case 28800:
191
        br = CYG_DEV_SERIAL_RS232_SCxBR_28800;
192
        break;
193
      case 38400:
194
        br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
195
        break;
196
      case 57600:
197
        br = CYG_DEV_SERIAL_RS232_SCxBR_57600;
198
        break;
199
      case 115200:
200
        br = CYG_DEV_SERIAL_RS232_SCxBR_115200;
201
        break;
202
      default:
203
        // Use the default if something unknown is requested
204
        br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
205
        break;
206
    }
207
 
208
    // 8-1-No parity
209
    HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE));
210
 
211
    // Set baud rate
212
    HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR0, br);
213
}
214
 
215
static cyg_bool
216
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
217
{
218
    cyg_uint16 status;
219
    cyg_uint16 result;
220
    cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
221
 
222
    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
223
    if((status & SCSR_RDRF) == 0)
224
        return false;
225
 
226
    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, result);
227
    *ch = (cyg_uint8)(result & 0x00ff);
228
 
229
    return true;
230
}
231
 
232
 
233
cyg_uint8
234
cyg_hal_plf_serial_getc(void* __ch_data)
235
{
236
    cyg_uint8 ch;
237
    CYGARC_HAL_SAVE_GP();
238
 
239
    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
240
 
241
    CYGARC_HAL_RESTORE_GP();
242
    return ch;
243
}
244
 
245
void
246
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
247
{
248
    cyg_uint16 status;
249
    cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
250
 
251
    CYGARC_HAL_SAVE_GP();
252
 
253
    do {
254
       HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
255
    } while((status & SCSR_TDRE) == 0);
256
 
257
    HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, (short)c);
258
 
259
    // Hang around until the character is safely sent
260
    do {
261
       HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
262
    } while((status & SCSR_TDRE) == 0);
263
 
264
    CYGARC_HAL_RESTORE_GP();
265
}
266
 
267
// Channel data
268
// Do NOT make them const, will cause problems when trying
269
// to change the timeout parameter ... (Is this a bug in other)
270
// PowerPC platform hals ?? You only see it when you really start from
271
// flash ....
272
static channel_data_t channels[2] = {
273
    { (cyg_uint16*)CYG_DEV_SERIAL_BASE_A,
274
      1000,
275
      CYGNUM_HAL_INTERRUPT_SIU_LVL0,
276
      CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX,
277
      0,
278
      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
279
    { (cyg_uint16*)CYG_DEV_SERIAL_BASE_B,
280
      1000,
281
      CYGNUM_HAL_INTERRUPT_SIU_LVL0,
282
      CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX,
283
      0,
284
      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
285
};
286
 
287
static void
288
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
289
                         cyg_uint32 __len)
290
{
291
    CYGARC_HAL_SAVE_GP();
292
 
293
    while(__len-- > 0)
294
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
295
 
296
    CYGARC_HAL_RESTORE_GP();
297
}
298
 
299
static void
300
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
301
{
302
    CYGARC_HAL_SAVE_GP();
303
 
304
    while(__len-- > 0)
305
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
306
 
307
    CYGARC_HAL_RESTORE_GP();
308
}
309
 
310
cyg_bool
311
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
312
{
313
    int delay_count;
314
    channel_data_t* chan = (channel_data_t*)__ch_data;
315
    cyg_bool res;
316
    CYGARC_HAL_SAVE_GP();
317
 
318
    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
319
    for(;;) {
320
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
321
        if (res || 0 == delay_count--)
322
            break;
323
 
324
        CYGACC_CALL_IF_DELAY_US(100);
325
    }
326
 
327
    CYGARC_HAL_RESTORE_GP();
328
    return res;
329
}
330
 
331
static int
332
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
333
{
334
    static int irq_state = 0;
335
    channel_data_t* chan = (channel_data_t*)__ch_data;
336
 
337
    int ret = 0;
338
    CYGARC_HAL_SAVE_GP();
339
 
340
    switch (__func) {
341
    case __COMMCTL_GETBAUD:
342
        ret = chan->baud_rate;
343
        break;
344
    case __COMMCTL_SETBAUD:
345
        {
346
        va_list ap;
347
        va_start(ap, __func);
348
 
349
        ret = chan->baud_rate;
350
        chan->baud_rate = va_arg(ap, cyg_int32);
351
        init_serial_channel(chan);
352
 
353
        va_end(ap);
354
        }
355
        break;
356
    case __COMMCTL_IRQ_ENABLE:
357
        HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level);
358
        HAL_INTERRUPT_UNMASK(chan->imb3_vector);
359
        HAL_INTERRUPT_UNMASK(chan->siu_vector);
360
        irq_state = 1;
361
        break;
362
    case __COMMCTL_IRQ_DISABLE:
363
        ret = irq_state;
364
        irq_state = 0;
365
        HAL_INTERRUPT_MASK(chan->imb3_vector);
366
        HAL_INTERRUPT_MASK(chan->siu_vector);
367
        break;
368
    case __COMMCTL_DBG_ISR_VECTOR:
369
        ret = chan->siu_vector;
370
        break;
371
    case __COMMCTL_SET_TIMEOUT:
372
        {
373
        va_list ap;
374
        va_start(ap, __func);
375
 
376
        ret = chan->msec_timeout;
377
        chan->msec_timeout = va_arg(ap, cyg_uint32);
378
 
379
        va_end(ap);
380
        }
381
        break;
382
    default:
383
        break;
384
    }
385
    CYGARC_HAL_RESTORE_GP();
386
    return ret;
387
}
388
 
389
static int
390
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
391
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
392
{
393
    int res = 0;
394
 
395
    cyg_uint16 status;
396
    cyg_uint16 control;
397
 
398
    cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
399
 
400
    CYGARC_HAL_SAVE_GP();
401
 
402
    *__ctrlc = 0;
403
 
404
    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
405
    HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, control);
406
 
407
    if((status & SCSR_RDRF) && (control & SCCR1_RIE))
408
    {   // Only if the interrupt was caused by the channel
409
        cyg_uint8 c;
410
        c = cyg_hal_plf_serial_getc(__ch_data);
411
 
412
        if(cyg_hal_is_break(&c, 1))
413
            *__ctrlc = 1;
414
 
415
        HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
416
        res = CYG_ISR_HANDLED;
417
    }
418
 
419
    CYGARC_HAL_RESTORE_GP();
420
    return res;
421
}
422
 
423
static void
424
cyg_hal_plf_serial_init(void)
425
{
426
    hal_virtual_comm_table_t* comm;
427
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
428
 
429
    // Disable interrupts.
430
    HAL_INTERRUPT_MASK(channels[0].imb3_vector);
431
    HAL_INTERRUPT_MASK(channels[1].imb3_vector);
432
 
433
    // Init channels
434
    init_serial_channel(&channels[0]);
435
    init_serial_channel(&channels[1]);
436
 
437
    // Setup procs in the vector table
438
 
439
    // Set channel 0
440
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
441
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
442
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
443
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
444
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
445
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
446
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
447
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
448
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
449
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
450
 
451
    // Set channel 1
452
    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
453
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
454
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
455
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
456
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
457
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
458
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
459
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
460
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
461
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
462
 
463
    // Restore original console
464
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
465
}
466
 
467
//=============================================================================
468
// Compatibility with older stubs
469
//=============================================================================
470
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
471
 
472
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
473
#include <cyg/hal/hal_stub.h>           // CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION
474
#endif
475
 
476
//-----------------------------------------------------------------------------
477
// Assumption: all diagnostic output must be GDB packetized unless
478
// this is a configuration for a stand-alone ROM system.
479
#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGSEM_HAL_ROM_MONITOR)
480
# define HAL_DIAG_USES_HARDWARE
481
#endif
482
 
483
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
484
# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_A)
485
#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
486
# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_B)
487
#else
488
# error "LCD driver not (yet) implemented for cme555"
489
#endif
490
 
491
static channel_data_t channel = { __BASE, 0, 0 };
492
 
493
#ifdef HAL_DIAG_USES_HARDWARE
494
 
495
void hal_diag_init(void)
496
{
497
    init_serial_channel(&channel);
498
}
499
 
500
void hal_diag_write_char(char __c)
501
{
502
    cyg_hal_plf_serial_putc(&channel, __c);
503
}
504
 
505
void hal_diag_read_char(char *c)
506
{
507
    *c = cyg_hal_plf_serial_getc(&channel);
508
}
509
 
510
#else  // ifdef HAL_DIAG_USES_HARDWARE
511
 
512
// Initialize diag port
513
void
514
hal_diag_init(void)
515
{
516
    // Init devices
517
    init_serial_channel(&channel);
518
}
519
 
520
void
521
hal_diag_write_char_serial( char c )
522
{
523
    unsigned long __state;
524
    HAL_DISABLE_INTERRUPTS(__state);
525
    cyg_hal_plf_serial_putc(&channel, c);
526
    HAL_RESTORE_INTERRUPTS(__state);
527
}
528
 
529
void
530
hal_diag_read_char(char *c)
531
{
532
    *c = cyg_hal_plf_serial_getc(&channel);
533
}
534
 
535
void
536
hal_diag_write_char(char c)
537
{
538
    static char line[100];
539
    static int pos = 0;
540
 
541
    // No need to send CRs
542
    if( c == '\r' ) return;
543
 
544
    line[pos++] = c;
545
 
546
    if( c == '\n' || pos == sizeof(line) )
547
    {
548
        CYG_INTERRUPT_STATE old;
549
 
550
        // Disable interrupts. This prevents GDB trying to interrupt us
551
        // while we are in the middle of sending a packet. The serial
552
        // receive interrupt will be seen when we re-enable interrupts
553
        // later.
554
 
555
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
556
        CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
557
#else
558
        HAL_DISABLE_INTERRUPTS(old);
559
#endif
560
 
561
        while(1)
562
        {
563
            char c1;
564
            static char hex[] = "0123456789ABCDEF";
565
            cyg_uint8 csum = 0;
566
            int i;
567
 
568
            hal_diag_write_char_serial('$');
569
            hal_diag_write_char_serial('O');
570
            csum += 'O';
571
            for( i = 0; i < pos; i++ )
572
            {
573
                char ch = line[i];
574
                char h = hex[(ch>>4)&0xF];
575
                char l = hex[ch&0xF];
576
                hal_diag_write_char_serial(h);
577
                hal_diag_write_char_serial(l);
578
                csum += h;
579
                csum += l;
580
            }
581
            hal_diag_write_char_serial('#');
582
            hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
583
            hal_diag_write_char_serial(hex[csum&0xF]);
584
 
585
            // Wait for the ACK character '+' from GDB here and handle
586
            // receiving a ^C instead.
587
            hal_diag_read_char(&c1);
588
 
589
            if( c1 == '+' )
590
                break;              // a good acknowledge
591
 
592
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
593
            if( 3 == c1 ) {
594
                // Ctrl-C: breakpoint.
595
                cyg_hal_gdb_interrupt(
596
                    (target_register_t)__builtin_return_address(0));
597
                break;
598
            }
599
#endif
600
            // otherwise, loop round again
601
        }
602
 
603
        pos = 0;
604
 
605
        // And re-enable interrupts
606
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
607
        CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
608
#else
609
        HAL_RESTORE_INTERRUPTS(old);
610
#endif
611
 
612
    }
613
}
614
 
615
#endif  // ifdef HAL_DIAG_USES_HARDWARE
616
 
617
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
618
 
619
//-----------------------------------------------------------------------------
620
// End of hal_diag.c

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