OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [csb281/] [v2_0/] [include/] [pkgconf/] [mlt_powerpc_csb281_rom.h] - Blame information for rev 565

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Thu May 30 10:21:41 2002
2
 
3
// This is a generated file - do not edit
4
 
5
#ifndef __ASSEMBLER__
6
#include <cyg/infra/cyg_type.h>
7
#include <stddef.h>
8
 
9
#endif
10
#define CYGMEM_REGION_ram (0)
11
#define CYGMEM_REGION_ram_SIZE (0x1F00000)
12
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
13
#define CYGMEM_REGION_rom (0xfff00000)
14
#define CYGMEM_REGION_rom_SIZE (0x100000)
15
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
16
#ifndef __ASSEMBLER__
17
extern char CYG_LABEL_NAME (__reserved_vectors) [];
18
#endif
19
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
20
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
21
#ifndef __ASSEMBLER__
22
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
23
#endif
24
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
25
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
26
#ifndef __ASSEMBLER__
27
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
28
#endif
29
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
30
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
31
#ifndef __ASSEMBLER__
32
extern char CYG_LABEL_NAME (__heap1) [];
33
#endif
34
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
35
#define CYGMEM_SECTION_heap1_SIZE (0x1f00000 - (size_t) CYG_LABEL_NAME (__heap1))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.