OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [csb281/] [v2_0/] [src/] [csb281.S] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
##=============================================================================
2
##
3
##      csb281.S
4
##
5
##      CSB281 board hardware setup
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
## Copyright (C) 2002, 2003 Gary Thomas
13
##
14
## eCos is free software; you can redistribute it and/or modify it under
15
## the terms of the GNU General Public License as published by the Free
16
## Software Foundation; either version 2 or (at your option) any later version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License along
24
## with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26
##
27
## As a special exception, if other files instantiate templates or use macros
28
## or inline functions from this file, or you compile this file and link it
29
## with other works to produce a work based on this file, this file does not
30
## by itself cause the resulting work to be covered by the GNU General Public
31
## License. However the source code for this file must still be made available
32
## in accordance with section (3) of the GNU General Public License.
33
##
34
## This exception does not invalidate any other reasons why a work based on
35
## this file might be covered by the GNU General Public License.
36
##
37
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38
## at http://sources.redhat.com/ecos/ecos-license/
39
## -------------------------------------------
40
#####ECOSGPLCOPYRIGHTEND####
41
##=============================================================================
42
#######DESCRIPTIONBEGIN####
43
##
44
## Author(s):   gthomas
45
## Contributors:hmt
46
## Date:        2002-07-22
47
## Purpose:     CSB281 board hardware setup
48
## Description: This file contains any code needed to initialize the
49
##              hardware on a Cogent CSB281 (PowerPC 8245) board.
50
##
51
######DESCRIPTIONEND####
52
##
53
##=============================================================================
54
 
55
#include 
56
#include 
57
#include 
58
#include 
59
 
60
#include                /* register symbols et al */
61
#include                /* on-chip resource layout, special */
62
 
63
#------------------------------------------------------------------------------
64
 
65
// LED macro uses r23, r25: r4 left alone
66
#if 0
67
#define LED( x ) \
68
        lwi     r25,0xFA100018;         \
69
        lwi     r23,(x);                \
70
        stb     r23,0(r25)
71
#else
72
#define LED(x)
73
#endif
74
 
75
FUNC_START(_led)
76
        lwi     r25,0xFF000000
77
        lwz     r26,0(r25)
78
        ori     r26,r26,0x18
79
        stw     r26,0(r25)
80
        blr
81
FUNC_END(_led)
82
 
83
#------------------------------------------------------------------------------
84
 
85
FUNC_START( hal_hardware_init )
86
 
87
        // Basic hardware initialization
88
        mflr    r31
89
        bl      10f     // Gets position independent address of table
90
HW_init:
91
#ifndef CYG_HAL_STARTUP_RAM
92
        .long   0x80000080, 0x00000000  // MSAR1 - SDRAM Bank 0 start
93
        .long   0x80000090, 0x0000003F  // MEAR1 - SDRAM Bank 0 end
94
        .long   0x800000A0, 0x00000001  // MBEN1 - SDRAM Bank 1 enable
95
        .long   0x800000F0, 0x88000000  // MCCR1 - SDRAM control (no GO)
96
        .long   0x800000F4, 0x1E00023C  // MCCR2 - Timing
97
        .long   0x800000F8, 0xB6000000  // MCCR3
98
        .long   0x800000FC, 0x35B03334  // MCCR4
99
        .long   0x800000F0, 0x88080000  // MCCR1 - SDRAM control (GO)
100
        .long   0x800000D0, 0xB4000000  // ERCR1
101
        .long   0x800000D4, 0xBCF7B1E3  // ERCR2
102
        .long   0x800000D8, 0x7000000D  // RCS2  - 0x70000000..0x71FFFFFF
103
        .long   0x800000DC, 0x7800000D  // RCS3  - 0x78000000..0x79FFFFFF
104
#endif
105
        .long   0x80000078, _CSB281_EUMBBAR  // EUMBBAR - machine registers
106
        .long   0x800000A8, 0xFF141110  // PICR1 - RCS0 local, Big Endian, DEC/TB
107
        .long   0x800000AC, 0x08000000  // PICR2
108
        .long   0
109
10:     nop
110
        mflr    r3              // Pointer to initialization table
111
        subi    r3,r3,4
112
        lwi     r4,_CSB281_PCI_CONFIG_ADDR
113
        lwi     r5,_CSB281_PCI_CONFIG_DATA
114
20:     lwzu    r6,4(r3)        // Register address
115
        lwzu    r7,4(r3)        // Data
116
        cmpi    0,r6,0
117
        beq     30f             // end of table?
118
        stwbrx  r6,0,r4         // Set address
119
        stwbrx  r7,0,r5         // value
120
        b       20b
121
30:     mtlr    r31
122
 
123
        # set the decrementer to maxint
124
        lwi     r2,0
125
        not     r2,r2
126
        mtdec   r2
127
 
128
#ifdef CYG_HAL_STARTUP_ROMRAM
129
        // Copy image from ROM to RAM
130
        mflr    r3
131
        lwi     r4,0xFF000000
132
        lwi     r5,0x00FFFFFF   // ROM/FLASH base
133
        and     r3,r3,r5        // segment relative
134
        lwi     r6,_hal_hardware_init_done
135
        mtlr    r6
136
        sub     r6,r3,r6        // Absolute address
137
        add     r6,r6,r4        // FLASH address
138
        lwi     r7,0            // where to copy to
139
        lwi     r8,__ram_data_end
140
10:     lwz     r5,0(r6)
141
        stw     r5,0(r7)
142
        addi    r6,r6,4
143
        addi    r7,r7,4
144
        cmplw   r7,r8
145
        bne     10b
146
#endif
147
 
148
        blr
149
FUNC_END( hal_hardware_init )
150
 
151
#------------------------------------------------------------------------------
152
# end of csb281.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.