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//=============================================================================
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//
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// hal_diag.c
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//
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// HAL diagnostic output code
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Bob Koninckx
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// Contributors: Bob Koninckx
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// Date: 2001-12-11
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// Purpose: HAL diagnostic output
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// Description: Implementations of HAL diagnostic output support.
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/hal/hal_diag.h> // our header.
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#include <cyg/infra/cyg_type.h> // base types, externC
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#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
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#include <cyg/hal/hal_misc.h> // Helper functions
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_intr.h> // Interrupt macros
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#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP
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#include <cyg/hal/hal_if.h> // Calling-if API
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static void cyg_hal_plf_serial_init(void);
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void
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cyg_hal_plf_comms_init(void)
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{
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static int initialized = 0;
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if (initialized)
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return;
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initialized = 1;
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cyg_hal_plf_serial_init();
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}
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//=============================================================================
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// Serial driver
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//=============================================================================
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//-----------------------------------------------------------------------------
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// There are two serial ports.
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#define CYG_DEV_SERIAL_BASE_A 0x305008 // SCI0
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#define CYG_DEV_SERIAL_BASE_B 0x305020 // SCI1
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//-----------------------------------------------------------------------------
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// Define CYG_DEVICE_SERIAL_RS232_SCIBR
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// Default baudrate is 38400
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// These values are calculated for a 40Mhz clock frequency
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// This should be enough, we did not provide clock frequency as a configuration
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// option anyway
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#define CYG_DEV_SERIAL_RS232_SCxBR_300 4167
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#define CYG_DEV_SERIAL_RS232_SCxBR_600 2083
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#define CYG_DEV_SERIAL_RS232_SCxBR_1200 1042
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#define CYG_DEV_SERIAL_RS232_SCxBR_2400 521
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#define CYG_DEV_SERIAL_RS232_SCxBR_4800 260
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#define CYG_DEV_SERIAL_RS232_SCxBR_9600 130
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#define CYG_DEV_SERIAL_RS232_SCxBR_14400 87
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#define CYG_DEV_SERIAL_RS232_SCxBR_19200 65
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#define CYG_DEV_SERIAL_RS232_SCxBR_28800 43
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#define CYG_DEV_SERIAL_RS232_SCxBR_38400 33
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#define CYG_DEV_SERIAL_RS232_SCxBR_57600 22
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#define CYG_DEV_SERIAL_RS232_SCxBR_115200 11
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//-----------------------------------------------------------------------------
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// Define the serial registers.
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#define CYG_DEV_SERIAL_RS232_SCCR0 0x00
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#define CYG_DEV_SERIAL_RS232_SCCR1 0x01
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#define CYG_DEV_SERIAL_RS232_SCSR 0x02
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#define CYG_DEV_SERIAL_RS232_SCDR 0x03
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#define SCCR0_OTHR 0x8000 // Select baud rate other than system clock
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#define SCCR0_LINKBD 0x4000 // Link baud
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#define SCCR0_SCxBR 0x1fff // SCI baud rate
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#define SCCR1_LOOPS 0x4000 // Loop mode
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#define SCCR1_WOMS 0x2000 // Wired or for SCI pins
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#define SCCR1_ILT 0x1000 // Idle line detect type
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#define SCCR1_PT 0x0800 // Parity type (0 = Odd, 1 = Even)
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#define SCCR1_PE 0x0400 // Parity enable
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#define SCCR1_M 0x0200 // Mode select (0 = 10 bit frame, 1 = 11 bit frame)
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#define SCCR1_WAKE 0x0100 // Wakeup by address mark
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#define SCCR1_TIE 0x0080 // Transmit interrupt enable
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#define SCCR1_TCIE 0x0040 // Transmit complete interrupt enable
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#define SCCR1_RIE 0x0020 // Receiver interrupt enable
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#define SCCR1_ILIE 0x0010 // Idle line interrupt enable
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#define SCCR1_TE 0x0008 // Transmiter enable
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#define SCCR1_RE 0x0004 // Receiver enable
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#define SCCR1_RWU 0x0002 // Receiver wakeup
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#define SCCR1_SBK 0x0001 // Send break
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#define SCSR_TDRE 0x0100 // Transmit data register empty
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#define SCSR_TC 0x0080 // Transmit complete
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#define SCSR_RDRF 0x0040 // Receive data register full
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#define SCSR_RAF 0x0020 // Receive active flag
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#define SCSR_IDLE 0x0010 // Idle line detected
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#define SCSR_OR 0x0008 // Overrun error
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#define SCSR_NF 0x0004 // Noise error flag
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#define SCSR_FE 0x0002 // Framing error
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#define SCSR_PF 0x0001 // Parity error
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//-----------------------------------------------------------------------------
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typedef struct {
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cyg_uint16* base;
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cyg_int32 msec_timeout;
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int siu_vector;
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int imb3_vector;
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unsigned int level;
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int baud_rate;
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} channel_data_t;
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//-----------------------------------------------------------------------------
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static void
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init_serial_channel(const channel_data_t* __ch_data)
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{
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cyg_uint16 * base = __ch_data->base;
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cyg_uint16 br;
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switch(__ch_data->baud_rate)
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{
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case 300:
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br = CYG_DEV_SERIAL_RS232_SCxBR_300;
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break;
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case 600:
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br = CYG_DEV_SERIAL_RS232_SCxBR_600;
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break;
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case 1200:
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br = CYG_DEV_SERIAL_RS232_SCxBR_1200;
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break;
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case 2400:
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br = CYG_DEV_SERIAL_RS232_SCxBR_2400;
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break;
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case 4800:
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br = CYG_DEV_SERIAL_RS232_SCxBR_4800;
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break;
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case 9600:
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br = CYG_DEV_SERIAL_RS232_SCxBR_9600;
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break;
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case 14400:
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br = CYG_DEV_SERIAL_RS232_SCxBR_14400;
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break;
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case 19200:
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br = CYG_DEV_SERIAL_RS232_SCxBR_19200;
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break;
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case 28800:
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br = CYG_DEV_SERIAL_RS232_SCxBR_28800;
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break;
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case 38400:
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br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
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break;
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case 57600:
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br = CYG_DEV_SERIAL_RS232_SCxBR_57600;
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break;
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case 115200:
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br = CYG_DEV_SERIAL_RS232_SCxBR_115200;
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break;
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default:
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// Use the default if something unknown is requested
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br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
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break;
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}
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// 8-1-No parity
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HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE));
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// Set baud rate
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HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR0, br);
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}
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static cyg_bool
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cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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{
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cyg_uint16 status;
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cyg_uint16 result;
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cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
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HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
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if((status & SCSR_RDRF) == 0)
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return false;
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HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, result);
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*ch = (cyg_uint8)(result & 0x00ff);
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return true;
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}
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cyg_uint8
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cyg_hal_plf_serial_getc(void* __ch_data)
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{
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cyg_uint8 ch;
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CYGARC_HAL_SAVE_GP();
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while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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241 |
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CYGARC_HAL_RESTORE_GP();
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return ch;
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}
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void
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cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
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{
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248 |
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cyg_uint16 status;
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249 |
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cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
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250 |
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251 |
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CYGARC_HAL_SAVE_GP();
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do {
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254 |
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HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
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} while((status & SCSR_TDRE) == 0);
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256 |
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257 |
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HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, (short)c);
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258 |
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259 |
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// Hang around until the character is safely sent
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260 |
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do {
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261 |
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HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
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262 |
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} while((status & SCSR_TDRE) == 0);
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263 |
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264 |
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CYGARC_HAL_RESTORE_GP();
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265 |
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}
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266 |
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267 |
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// Channel data
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268 |
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// Do NOT make them const, will cause problems when trying
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269 |
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// to change the timeout parameter ... (Is this a bug in other)
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270 |
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// PowerPC platform hals ?? You only see it when you really start from
|
271 |
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// flash ....
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272 |
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static channel_data_t channels[2] = {
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273 |
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{ (cyg_uint16*)CYG_DEV_SERIAL_BASE_A,
|
274 |
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1000,
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275 |
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CYGNUM_HAL_INTERRUPT_SIU_LVL0,
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276 |
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CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX,
|
277 |
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0,
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278 |
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CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
|
279 |
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{ (cyg_uint16*)CYG_DEV_SERIAL_BASE_B,
|
280 |
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1000,
|
281 |
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CYGNUM_HAL_INTERRUPT_SIU_LVL0,
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282 |
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CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX,
|
283 |
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0,
|
284 |
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CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
|
285 |
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};
|
286 |
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|
287 |
|
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static void
|
288 |
|
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cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
|
289 |
|
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cyg_uint32 __len)
|
290 |
|
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{
|
291 |
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CYGARC_HAL_SAVE_GP();
|
292 |
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|
293 |
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while(__len-- > 0)
|
294 |
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cyg_hal_plf_serial_putc(__ch_data, *__buf++);
|
295 |
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|
296 |
|
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CYGARC_HAL_RESTORE_GP();
|
297 |
|
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}
|
298 |
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|
299 |
|
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static void
|
300 |
|
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cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
|
301 |
|
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{
|
302 |
|
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CYGARC_HAL_SAVE_GP();
|
303 |
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|
304 |
|
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while(__len-- > 0)
|
305 |
|
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*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
|
306 |
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|
307 |
|
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CYGARC_HAL_RESTORE_GP();
|
308 |
|
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}
|
309 |
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|
310 |
|
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cyg_bool
|
311 |
|
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cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
|
312 |
|
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{
|
313 |
|
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int delay_count;
|
314 |
|
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channel_data_t* chan = (channel_data_t*)__ch_data;
|
315 |
|
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cyg_bool res;
|
316 |
|
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CYGARC_HAL_SAVE_GP();
|
317 |
|
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|
318 |
|
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delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
|
319 |
|
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for(;;) {
|
320 |
|
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res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
|
321 |
|
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if (res || 0 == delay_count--)
|
322 |
|
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break;
|
323 |
|
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|
324 |
|
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CYGACC_CALL_IF_DELAY_US(100);
|
325 |
|
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}
|
326 |
|
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|
327 |
|
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CYGARC_HAL_RESTORE_GP();
|
328 |
|
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return res;
|
329 |
|
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}
|
330 |
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|
331 |
|
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static int
|
332 |
|
|
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
|
333 |
|
|
{
|
334 |
|
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static int irq_state = 0;
|
335 |
|
|
channel_data_t* chan = (channel_data_t*)__ch_data;
|
336 |
|
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|
337 |
|
|
int ret = 0;
|
338 |
|
|
CYGARC_HAL_SAVE_GP();
|
339 |
|
|
|
340 |
|
|
switch (__func) {
|
341 |
|
|
case __COMMCTL_GETBAUD:
|
342 |
|
|
ret = chan->baud_rate;
|
343 |
|
|
break;
|
344 |
|
|
case __COMMCTL_SETBAUD:
|
345 |
|
|
{
|
346 |
|
|
va_list ap;
|
347 |
|
|
va_start(ap, __func);
|
348 |
|
|
|
349 |
|
|
ret = chan->baud_rate;
|
350 |
|
|
chan->baud_rate = va_arg(ap, cyg_int32);
|
351 |
|
|
init_serial_channel(chan);
|
352 |
|
|
|
353 |
|
|
va_end(ap);
|
354 |
|
|
}
|
355 |
|
|
break;
|
356 |
|
|
case __COMMCTL_IRQ_ENABLE:
|
357 |
|
|
HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level);
|
358 |
|
|
HAL_INTERRUPT_UNMASK(chan->imb3_vector);
|
359 |
|
|
HAL_INTERRUPT_UNMASK(chan->siu_vector);
|
360 |
|
|
irq_state = 1;
|
361 |
|
|
break;
|
362 |
|
|
case __COMMCTL_IRQ_DISABLE:
|
363 |
|
|
ret = irq_state;
|
364 |
|
|
irq_state = 0;
|
365 |
|
|
HAL_INTERRUPT_MASK(chan->imb3_vector);
|
366 |
|
|
HAL_INTERRUPT_MASK(chan->siu_vector);
|
367 |
|
|
break;
|
368 |
|
|
case __COMMCTL_DBG_ISR_VECTOR:
|
369 |
|
|
ret = chan->siu_vector;
|
370 |
|
|
break;
|
371 |
|
|
case __COMMCTL_SET_TIMEOUT:
|
372 |
|
|
{
|
373 |
|
|
va_list ap;
|
374 |
|
|
va_start(ap, __func);
|
375 |
|
|
|
376 |
|
|
ret = chan->msec_timeout;
|
377 |
|
|
chan->msec_timeout = va_arg(ap, cyg_uint32);
|
378 |
|
|
|
379 |
|
|
va_end(ap);
|
380 |
|
|
}
|
381 |
|
|
break;
|
382 |
|
|
default:
|
383 |
|
|
break;
|
384 |
|
|
}
|
385 |
|
|
CYGARC_HAL_RESTORE_GP();
|
386 |
|
|
return ret;
|
387 |
|
|
}
|
388 |
|
|
|
389 |
|
|
static int
|
390 |
|
|
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
|
391 |
|
|
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
|
392 |
|
|
{
|
393 |
|
|
int res = 0;
|
394 |
|
|
|
395 |
|
|
cyg_uint16 status;
|
396 |
|
|
cyg_uint16 control;
|
397 |
|
|
|
398 |
|
|
cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
|
399 |
|
|
|
400 |
|
|
CYGARC_HAL_SAVE_GP();
|
401 |
|
|
|
402 |
|
|
*__ctrlc = 0;
|
403 |
|
|
|
404 |
|
|
HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
|
405 |
|
|
HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, control);
|
406 |
|
|
|
407 |
|
|
if((status & SCSR_RDRF) && (control & SCCR1_RIE))
|
408 |
|
|
{ // Only if the interrupt was caused by the channel
|
409 |
|
|
cyg_uint8 c;
|
410 |
|
|
c = cyg_hal_plf_serial_getc(__ch_data);
|
411 |
|
|
|
412 |
|
|
if(cyg_hal_is_break(&c, 1))
|
413 |
|
|
*__ctrlc = 1;
|
414 |
|
|
|
415 |
|
|
HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
|
416 |
|
|
res = CYG_ISR_HANDLED;
|
417 |
|
|
}
|
418 |
|
|
|
419 |
|
|
CYGARC_HAL_RESTORE_GP();
|
420 |
|
|
return res;
|
421 |
|
|
}
|
422 |
|
|
|
423 |
|
|
static void
|
424 |
|
|
cyg_hal_plf_serial_init(void)
|
425 |
|
|
{
|
426 |
|
|
hal_virtual_comm_table_t* comm;
|
427 |
|
|
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
|
428 |
|
|
|
429 |
|
|
// Disable interrupts.
|
430 |
|
|
HAL_INTERRUPT_MASK(channels[0].imb3_vector);
|
431 |
|
|
HAL_INTERRUPT_MASK(channels[1].imb3_vector);
|
432 |
|
|
|
433 |
|
|
// Init channels
|
434 |
|
|
init_serial_channel(&channels[0]);
|
435 |
|
|
init_serial_channel(&channels[1]);
|
436 |
|
|
|
437 |
|
|
// Setup procs in the vector table
|
438 |
|
|
|
439 |
|
|
// Set channel 0
|
440 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
|
441 |
|
|
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
|
442 |
|
|
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
|
443 |
|
|
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
|
444 |
|
|
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
|
445 |
|
|
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
|
446 |
|
|
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
|
447 |
|
|
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
|
448 |
|
|
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
|
449 |
|
|
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
|
450 |
|
|
|
451 |
|
|
// Set channel 1
|
452 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
|
453 |
|
|
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
|
454 |
|
|
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
|
455 |
|
|
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
|
456 |
|
|
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
|
457 |
|
|
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
|
458 |
|
|
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
|
459 |
|
|
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
|
460 |
|
|
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
|
461 |
|
|
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
|
462 |
|
|
|
463 |
|
|
// Restore original console
|
464 |
|
|
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
|
465 |
|
|
}
|
466 |
|
|
|
467 |
|
|
//=============================================================================
|
468 |
|
|
// Compatibility with older stubs
|
469 |
|
|
//=============================================================================
|
470 |
|
|
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
|
471 |
|
|
|
472 |
|
|
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
|
473 |
|
|
#include <cyg/hal/hal_stub.h> // CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION
|
474 |
|
|
#endif
|
475 |
|
|
|
476 |
|
|
//-----------------------------------------------------------------------------
|
477 |
|
|
// Assumption: all diagnostic output must be GDB packetized unless
|
478 |
|
|
// this is a configuration for a stand-alone ROM system.
|
479 |
|
|
#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGSEM_HAL_ROM_MONITOR)
|
480 |
|
|
# define HAL_DIAG_USES_HARDWARE
|
481 |
|
|
#endif
|
482 |
|
|
|
483 |
|
|
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
|
484 |
|
|
# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_A)
|
485 |
|
|
#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
|
486 |
|
|
# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_B)
|
487 |
|
|
#else
|
488 |
|
|
# error "Invalid console channel selection"
|
489 |
|
|
#endif
|
490 |
|
|
|
491 |
|
|
static channel_data_t channel = { __BASE, 0, 0 };
|
492 |
|
|
|
493 |
|
|
#ifdef HAL_DIAG_USES_HARDWARE
|
494 |
|
|
|
495 |
|
|
void hal_diag_init(void)
|
496 |
|
|
{
|
497 |
|
|
init_serial_channel(&channel);
|
498 |
|
|
}
|
499 |
|
|
|
500 |
|
|
void hal_diag_write_char(char __c)
|
501 |
|
|
{
|
502 |
|
|
cyg_hal_plf_serial_putc(&channel, __c);
|
503 |
|
|
}
|
504 |
|
|
|
505 |
|
|
void hal_diag_read_char(char *c)
|
506 |
|
|
{
|
507 |
|
|
*c = cyg_hal_plf_serial_getc(&channel);
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
#else // ifdef HAL_DIAG_USES_HARDWARE
|
511 |
|
|
|
512 |
|
|
// Initialize diag port
|
513 |
|
|
void
|
514 |
|
|
hal_diag_init(void)
|
515 |
|
|
{
|
516 |
|
|
// Init devices
|
517 |
|
|
init_serial_channel(&channel);
|
518 |
|
|
}
|
519 |
|
|
|
520 |
|
|
void
|
521 |
|
|
hal_diag_write_char_serial( char c )
|
522 |
|
|
{
|
523 |
|
|
unsigned long __state;
|
524 |
|
|
HAL_DISABLE_INTERRUPTS(__state);
|
525 |
|
|
cyg_hal_plf_serial_putc(&channel, c);
|
526 |
|
|
HAL_RESTORE_INTERRUPTS(__state);
|
527 |
|
|
}
|
528 |
|
|
|
529 |
|
|
void
|
530 |
|
|
hal_diag_read_char(char *c)
|
531 |
|
|
{
|
532 |
|
|
*c = cyg_hal_plf_serial_getc(&channel);
|
533 |
|
|
}
|
534 |
|
|
|
535 |
|
|
void
|
536 |
|
|
hal_diag_write_char(char c)
|
537 |
|
|
{
|
538 |
|
|
static char line[100];
|
539 |
|
|
static int pos = 0;
|
540 |
|
|
|
541 |
|
|
// No need to send CRs
|
542 |
|
|
if( c == '\r' ) return;
|
543 |
|
|
|
544 |
|
|
line[pos++] = c;
|
545 |
|
|
|
546 |
|
|
if( c == '\n' || pos == sizeof(line) )
|
547 |
|
|
{
|
548 |
|
|
CYG_INTERRUPT_STATE old;
|
549 |
|
|
|
550 |
|
|
// Disable interrupts. This prevents GDB trying to interrupt us
|
551 |
|
|
// while we are in the middle of sending a packet. The serial
|
552 |
|
|
// receive interrupt will be seen when we re-enable interrupts
|
553 |
|
|
// later.
|
554 |
|
|
|
555 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
556 |
|
|
CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
|
557 |
|
|
#else
|
558 |
|
|
HAL_DISABLE_INTERRUPTS(old);
|
559 |
|
|
#endif
|
560 |
|
|
|
561 |
|
|
while(1)
|
562 |
|
|
{
|
563 |
|
|
char c1;
|
564 |
|
|
static char hex[] = "0123456789ABCDEF";
|
565 |
|
|
cyg_uint8 csum = 0;
|
566 |
|
|
int i;
|
567 |
|
|
|
568 |
|
|
hal_diag_write_char_serial('$');
|
569 |
|
|
hal_diag_write_char_serial('O');
|
570 |
|
|
csum += 'O';
|
571 |
|
|
for( i = 0; i < pos; i++ )
|
572 |
|
|
{
|
573 |
|
|
char ch = line[i];
|
574 |
|
|
char h = hex[(ch>>4)&0xF];
|
575 |
|
|
char l = hex[ch&0xF];
|
576 |
|
|
hal_diag_write_char_serial(h);
|
577 |
|
|
hal_diag_write_char_serial(l);
|
578 |
|
|
csum += h;
|
579 |
|
|
csum += l;
|
580 |
|
|
}
|
581 |
|
|
hal_diag_write_char_serial('#');
|
582 |
|
|
hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
|
583 |
|
|
hal_diag_write_char_serial(hex[csum&0xF]);
|
584 |
|
|
|
585 |
|
|
// Wait for the ACK character '+' from GDB here and handle
|
586 |
|
|
// receiving a ^C instead.
|
587 |
|
|
hal_diag_read_char(&c1);
|
588 |
|
|
|
589 |
|
|
if( c1 == '+' )
|
590 |
|
|
break; // a good acknowledge
|
591 |
|
|
|
592 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
|
593 |
|
|
if( 3 == c1 ) {
|
594 |
|
|
// Ctrl-C: breakpoint.
|
595 |
|
|
cyg_hal_gdb_interrupt(
|
596 |
|
|
(target_register_t)__builtin_return_address(0));
|
597 |
|
|
break;
|
598 |
|
|
}
|
599 |
|
|
#endif
|
600 |
|
|
// otherwise, loop round again
|
601 |
|
|
}
|
602 |
|
|
|
603 |
|
|
pos = 0;
|
604 |
|
|
|
605 |
|
|
// And re-enable interrupts
|
606 |
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
607 |
|
|
CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
|
608 |
|
|
#else
|
609 |
|
|
HAL_RESTORE_INTERRUPTS(old);
|
610 |
|
|
#endif
|
611 |
|
|
|
612 |
|
|
}
|
613 |
|
|
}
|
614 |
|
|
|
615 |
|
|
#endif // ifdef HAL_DIAG_USES_HARDWARE
|
616 |
|
|
|
617 |
|
|
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
|
618 |
|
|
|
619 |
|
|
//-----------------------------------------------------------------------------
|
620 |
|
|
// End of hal_diag.c
|