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#ifndef CYGONCE_HAL_PPC_FADS_PPC_860_H
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#define CYGONCE_HAL_PPC_FADS_PPC_860_H
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//=============================================================================
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//####UNSUPPORTEDBEGIN####
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//
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// -------------------------------------------
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// This source file has been contributed to eCos/Red Hat. It may have been
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// changed slightly to provide an interface consistent with those of other
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// files.
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//
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// The functionality and contents of this file is supplied "AS IS"
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// without any form of support and will not necessarily be kept up
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// to date by Red Hat.
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//
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// The style of programming used in this file may not comply with the
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// eCos programming guidelines. Please do not use as a base for other
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// files.
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//
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// All inquiries about this file, or the functionality provided by it,
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// should be directed to the 'ecos-discuss' mailing list (see
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// http://sourceware.cygnus.com/ecos/intouch.html for details).
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//
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// Contributed by: Kevin Hester <khester@opticworks.com>
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// Maintained by: <Unmaintained>
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// See also:
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// Motorola's "Example Software Initializing the SMC as a UART" package
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// (smc2.zip) at:
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// http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table
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// -------------------------------------------
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//
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//####UNSUPPORTEDEND####
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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/******************************************************************************
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*
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* Definitions of Parameter RAM entries for each peripheral and mode
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*
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******************************************************************************/
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/*---------------------------------------------------------------------------*/
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/* HDLC parameter RAM (SCC) */
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/*---------------------------------------------------------------------------*/
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struct hdlc_pram
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{
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/*-------------------*/
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/* SCC parameter RAM */
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/*-------------------*/
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cyg_uint16 rbase; /* RX BD base address */
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cyg_uint16 tbase; /* TX BD base address */
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cyg_uint8 rfcr; /* Rx function code */
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cyg_uint8 tfcr; /* Tx function code */
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cyg_uint16 mrblr; /* Rx buffer length */
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cyg_uint32 rstate; /* Rx internal state */
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cyg_uint32 rptr; /* Rx internal data pointer */
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cyg_uint16 rbptr; /* rb BD Pointer */
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cyg_uint16 rcount; /* Rx internal byte count */
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cyg_uint32 rtemp; /* Rx temp */
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cyg_uint32 tstate; /* Tx internal state */
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cyg_uint32 tptr; /* Tx internal data pointer */
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cyg_uint16 tbptr; /* Tx BD pointer */
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cyg_uint16 tcount; /* Tx byte count */
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cyg_uint32 ttemp; /* Tx temp */
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cyg_uint32 rcrc; /* temp receive CRC */
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cyg_uint32 tcrc; /* temp transmit CRC */
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/*-----------------------------*/
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/* HDLC specific parameter RAM */
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/*-----------------------------*/
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cyg_uint8 RESERVED1[4]; /* Reserved area */
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cyg_uint32 c_mask; /* CRC constant */
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cyg_uint32 c_pres; /* CRC preset */
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cyg_uint16 disfc; /* discarded frame counter */
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cyg_uint16 crcec; /* CRC error counter */
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cyg_uint16 abtsc; /* abort sequence counter */
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cyg_uint16 nmarc; /* nonmatching address rx cnt */
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cyg_uint16 retrc; /* frame retransmission cnt */
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cyg_uint16 mflr; /* maximum frame length reg */
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cyg_uint16 max_cnt; /* maximum length counter */
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cyg_uint16 rfthr; /* received frames threshold */
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cyg_uint16 rfcnt; /* received frames count */
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cyg_uint16 hmask; /* user defined frm addr mask */
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cyg_uint16 haddr1; /* user defined frm address 1 */
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cyg_uint16 haddr2; /* user defined frm address 2 */
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cyg_uint16 haddr3; /* user defined frm address 3 */
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cyg_uint16 haddr4; /* user defined frm address 4 */
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cyg_uint16 tmp; /* temp */
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cyg_uint16 tmp_mb; /* temp */
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};
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/*-------------------------------------------------------------------------*/
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/* ASYNC HDLC parameter RAM (SCC) */
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/*-------------------------------------------------------------------------*/
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struct async_hdlc_pram
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{
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/*-------------------*/
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/* SCC parameter RAM */
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/*-------------------*/
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cyg_uint16 rbase; /* RX BD base address */
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cyg_uint16 tbase; /* TX BD base address */
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cyg_uint8 rfcr; /* Rx function code */
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cyg_uint8 tfcr; /* Tx function code */
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cyg_uint16 mrblr; /* Rx buffer length */
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cyg_uint32 rstate; /* Rx internal state */
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cyg_uint32 rptr; /* Rx internal data pointer */
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cyg_uint16 rbptr; /* rb BD Pointer */
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cyg_uint16 rcount; /* Rx internal byte count */
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cyg_uint32 rtemp; /* Rx temp */
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cyg_uint32 tstate; /* Tx internal state */
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cyg_uint32 tptr; /* Tx internal data pointer */
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cyg_uint16 tbptr; /* Tx BD pointer */
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cyg_uint16 tcount; /* Tx byte count */
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cyg_uint32 ttemp; /* Tx temp */
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cyg_uint32 rcrc; /* temp receive CRC */
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cyg_uint32 tcrc; /* temp transmit CRC */
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/*-----------------------------------*/
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/* ASYNC HDLC specific parameter RAM */
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/*-----------------------------------*/
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cyg_uint8 RESERVED2[4]; /* Reserved area */
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cyg_uint32 c_mask; /* CRC constant */
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cyg_uint32 c_pres; /* CRC preset */
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cyg_uint16 bof; /* begining of flag character */
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cyg_uint16 eof; /* end of flag character */
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cyg_uint16 esc; /* control escape character */
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cyg_uint8 RESERVED3[4]; /* Reserved area */
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cyg_uint16 zero; /* zero */
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cyg_uint8 RESERVED4[2]; /* Reserved area */
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cyg_uint16 rfthr; /* received frames threshold */
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cyg_uint8 RESERVED5[4]; /* Reserved area */
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cyg_uint32 txctl_tbl; /* Tx ctl char mapping table */
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cyg_uint32 rxctl_tbl; /* Rx ctl char mapping table */
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cyg_uint16 nof; /* Number of opening flags */
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};
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/*--------------------------------------------------------------------------*/
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/* UART parameter RAM (SCC) */
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/*--------------------------------------------------------------------------*/
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/*----------------------------------------*/
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/* bits in uart control characters table */
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/*----------------------------------------*/
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#define CC_INVALID 0x8000 /* control character is valid */
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#define CC_REJ 0x4000 /* don't store char in buffer */
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#define CC_CHAR 0x00ff /* control character */
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/*------*/
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/* UART */
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/*------*/
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struct uart_pram
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{
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/*-------------------*/
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/* SCC parameter RAM */
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/*-------------------*/
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cyg_uint16 rbase; /* RX BD base address */
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cyg_uint16 tbase; /* TX BD base address */
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cyg_uint8 rfcr; /* Rx function code */
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cyg_uint8 tfcr; /* Tx function code */
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cyg_uint16 mrblr; /* Rx buffer length */
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cyg_uint32 rstate; /* Rx internal state */
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cyg_uint32 rptr; /* Rx internal data pointer */
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cyg_uint16 rbptr; /* rb BD Pointer */
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cyg_uint16 rcount; /* Rx internal byte count */
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cyg_uint32 rx_temp; /* Rx temp */
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cyg_uint32 tstate; /* Tx internal state */
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cyg_uint32 tptr; /* Tx internal data pointer */
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cyg_uint16 tbptr; /* Tx BD pointer */
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cyg_uint16 tcount; /* Tx byte count */
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cyg_uint32 ttemp; /* Tx temp */
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cyg_uint32 rcrc; /* temp receive CRC */
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cyg_uint32 tcrc; /* temp transmit CRC */
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/*------------------------------*/
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/* UART specific parameter RAM */
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/*------------------------------*/
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cyg_uint8 RESERVED6[8]; /* Reserved area */
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cyg_uint16 max_idl; /* maximum idle characters */
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cyg_uint16 idlc; /* rx idle counter (internal) */
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cyg_uint16 brkcr; /* break count register */
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cyg_uint16 parec; /* Rx parity error counter */
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cyg_uint16 frmec; /* Rx framing error counter */
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cyg_uint16 nosec; /* Rx noise counter */
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cyg_uint16 brkec; /* Rx break character counter */
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cyg_uint16 brkln; /* Reaceive break length */
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cyg_uint16 uaddr1; /* address character 1 */
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cyg_uint16 uaddr2; /* address character 2 */
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cyg_uint16 rtemp; /* temp storage */
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cyg_uint16 toseq; /* Tx out of sequence char */
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cyg_uint16 cc[8]; /* Rx control characters */
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cyg_uint16 rccm; /* Rx control char mask */
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cyg_uint16 rccr; /* Rx control char register */
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cyg_uint16 rlbc; /* Receive last break char */
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};
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/*---------------------------------------------------------------------------
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* BISYNC parameter RAM (SCC)
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*--------------------------------------------------------------------------*/
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struct bisync_pram
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{
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/*-------------------*/
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/* SCC parameter RAM */
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/*-------------------*/
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cyg_uint16 rbase; /* RX BD base address */
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cyg_uint16 tbase; /* TX BD base address */
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cyg_uint8 rfcr; /* Rx function code */
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cyg_uint8 tfcr; /* Tx function code */
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cyg_uint16 mrblr; /* Rx buffer length */
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cyg_uint32 rstate; /* Rx internal state */
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cyg_uint32 rptr; /* Rx internal data pointer */
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cyg_uint16 rbptr; /* rb BD Pointer */
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cyg_uint16 rcount; /* Rx internal byte count */
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cyg_uint32 rtemp; /* Rx temp */
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cyg_uint32 tstate; /* Tx internal state */
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cyg_uint32 tptr; /* Tx internal data pointer */
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cyg_uint16 tbptr; /* Tx BD pointer */
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cyg_uint16 tcount; /* Tx byte count */
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cyg_uint32 ttemp; /* Tx temp */
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cyg_uint32 rcrc; /* temp receive CRC */
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cyg_uint32 tcrc; /* temp transmit CRC */
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/*--------------------------------*/
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/* BISYNC specific parameter RAM */
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/*--------------------------------*/
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cyg_uint8 RESERVED7[4]; /* Reserved area */
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cyg_uint32 crcc; /* CRC Constant Temp Value */
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cyg_uint16 prcrc; /* Preset Receiver CRC-16/LRC */
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cyg_uint16 ptcrc; /* Preset Transmitter CRC-16/LRC */
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cyg_uint16 parec; /* Receive Parity Error Counter */
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cyg_uint16 bsync; /* BISYNC SYNC Character */
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| 256 |
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cyg_uint16 bdle; /* BISYNC DLE Character */
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cyg_uint16 cc[8]; /* Rx control characters */
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cyg_uint16 rccm; /* Receive Control Character Mask */
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};
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/*-------------------------------------------------------------------------*/
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/* Transparent mode parameter RAM (SCC) */
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| 264 |
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/*-------------------------------------------------------------------------*/
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| 265 |
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struct transparent_pram
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| 267 |
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| 268 |
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{
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| 269 |
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/*--------------------*/
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| 270 |
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/* SCC parameter RAM */
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| 271 |
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/*--------------------*/
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| 272 |
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| 273 |
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cyg_uint16 rbase; /* RX BD base address */
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| 274 |
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cyg_uint16 tbase; /* TX BD base address */
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| 275 |
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cyg_uint8 rfcr; /* Rx function code */
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| 276 |
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cyg_uint8 tfcr; /* Tx function code */
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| 277 |
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cyg_uint16 mrblr; /* Rx buffer length */
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| 278 |
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cyg_uint32 rstate; /* Rx internal state */
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| 279 |
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cyg_uint32 rptr; /* Rx internal data pointer */
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| 280 |
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cyg_uint16 rbptr; /* rb BD Pointer */
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| 281 |
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cyg_uint16 rcount; /* Rx internal byte count */
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| 282 |
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cyg_uint32 rtemp; /* Rx temp */
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| 283 |
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cyg_uint32 tstate; /* Tx internal state */
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| 284 |
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cyg_uint32 tptr; /* Tx internal data pointer */
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| 285 |
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cyg_uint16 tbptr; /* Tx BD pointer */
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| 286 |
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cyg_uint16 tcount; /* Tx byte count */
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| 287 |
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cyg_uint32 ttemp; /* Tx temp */
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| 288 |
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cyg_uint32 rcrc; /* temp receive CRC */
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| 289 |
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cyg_uint32 tcrc; /* temp transmit CRC */
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| 290 |
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| 291 |
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/*-------------------------------------*/
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| 292 |
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/* TRANSPARENT specific parameter RAM */
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| 293 |
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/*-------------------------------------*/
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| 294 |
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| 295 |
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cyg_uint32 crc_p; /* CRC Preset */
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| 296 |
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cyg_uint32 crc_c; /* CRC constant */
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| 297 |
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};
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| 298 |
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| 299 |
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| 300 |
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/*-------------------------------------------------------------------------*/
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| 301 |
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/* Ethernet parameter RAM (SCC) */
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| 302 |
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/*-------------------------------------------------------------------------*/
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| 303 |
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| 304 |
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struct ethernet_pram
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| 305 |
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| 306 |
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{
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| 307 |
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/*--------------------*/
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| 308 |
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/* SCC parameter RAM */
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| 309 |
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/*--------------------*/
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| 310 |
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| 311 |
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cyg_uint16 rbase; /* RX BD base address */
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| 312 |
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cyg_uint16 tbase; /* TX BD base address */
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| 313 |
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cyg_uint8 rfcr; /* Rx function code */
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| 314 |
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cyg_uint8 tfcr; /* Tx function code */
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| 315 |
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cyg_uint16 mrblr; /* Rx buffer length */
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| 316 |
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cyg_uint32 rstate; /* Rx internal state */
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| 317 |
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cyg_uint32 rptr; /* Rx internal data pointer */
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| 318 |
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cyg_uint16 rbptr; /* rb BD Pointer */
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| 319 |
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cyg_uint16 rcount; /* Rx internal byte count */
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| 320 |
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cyg_uint32 rtemp; /* Rx temp */
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| 321 |
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cyg_uint32 tstate; /* Tx internal state */
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| 322 |
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cyg_uint32 tptr; /* Tx internal data pointer */
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| 323 |
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cyg_uint16 tbptr; /* Tx BD pointer */
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| 324 |
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cyg_uint16 tcount; /* Tx byte count */
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| 325 |
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cyg_uint32 ttemp; /* Tx temp */
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| 326 |
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cyg_uint32 rcrc; /* temp receive CRC */
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| 327 |
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cyg_uint32 tcrc; /* temp transmit CRC */
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| 328 |
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|
|
| 329 |
|
|
/*---------------------------------*/
|
| 330 |
|
|
/* ETHERNET specific parameter RAM */
|
| 331 |
|
|
/*---------------------------------*/
|
| 332 |
|
|
|
| 333 |
|
|
cyg_uint32 c_pres; /* preset CRC */
|
| 334 |
|
|
cyg_uint32 c_mask; /* constant mask for CRC */
|
| 335 |
|
|
cyg_uint32 crcec; /* CRC error counter */
|
| 336 |
|
|
cyg_uint32 alec; /* alighnment error counter */
|
| 337 |
|
|
cyg_uint32 disfc; /* discard frame counter */
|
| 338 |
|
|
cyg_uint16 pads; /* short frame PAD characters */
|
| 339 |
|
|
cyg_uint16 ret_lim; /* retry limit threshold */
|
| 340 |
|
|
cyg_uint16 ret_cnt; /* retry limit counter */
|
| 341 |
|
|
cyg_uint16 mflr; /* maximum frame length reg */
|
| 342 |
|
|
cyg_uint16 minflr; /* minimum frame length reg */
|
| 343 |
|
|
cyg_uint16 maxd1; /* maximum DMA1 length reg */
|
| 344 |
|
|
cyg_uint16 maxd2; /* maximum DMA2 length reg */
|
| 345 |
|
|
cyg_uint16 maxd; /* rx max DMA */
|
| 346 |
|
|
cyg_uint16 dma_cnt; /* rx dma counter */
|
| 347 |
|
|
cyg_uint16 max_b; /* max bd byte count */
|
| 348 |
|
|
cyg_uint16 gaddr1; /* group address filter 1 */
|
| 349 |
|
|
cyg_uint16 gaddr2; /* group address filter 2 */
|
| 350 |
|
|
cyg_uint16 gaddr3; /* group address filter 3 */
|
| 351 |
|
|
cyg_uint16 gaddr4; /* group address filter 4 */
|
| 352 |
|
|
cyg_uint32 tbuf0_data0; /* save area 0 - current frm */
|
| 353 |
|
|
cyg_uint32 tbuf0_data1; /* save area 1 - current frm */
|
| 354 |
|
|
cyg_uint32 tbuf0_rba0;
|
| 355 |
|
|
cyg_uint32 tbuf0_crc;
|
| 356 |
|
|
cyg_uint16 tbuf0_bcnt;
|
| 357 |
|
|
cyg_uint16 paddr_h; /* physical address (MSB) */
|
| 358 |
|
|
cyg_uint16 paddr_m; /* physical address */
|
| 359 |
|
|
cyg_uint16 paddr_l; /* physical address (LSB) */
|
| 360 |
|
|
cyg_uint16 p_per; /* persistence */
|
| 361 |
|
|
cyg_uint16 rfbd_ptr; /* rx first bd pointer */
|
| 362 |
|
|
cyg_uint16 tfbd_ptr; /* tx first bd pointer */
|
| 363 |
|
|
cyg_uint16 tlbd_ptr; /* tx last bd pointer */
|
| 364 |
|
|
cyg_uint32 tbuf1_data0; /* save area 0 - next frame */
|
| 365 |
|
|
cyg_uint32 tbuf1_data1; /* save area 1 - next frame */
|
| 366 |
|
|
cyg_uint32 tbuf1_rba0;
|
| 367 |
|
|
cyg_uint32 tbuf1_crc;
|
| 368 |
|
|
cyg_uint16 tbuf1_bcnt;
|
| 369 |
|
|
cyg_uint16 tx_len; /* tx frame length counter */
|
| 370 |
|
|
cyg_uint16 iaddr1; /* individual address filter 1*/
|
| 371 |
|
|
cyg_uint16 iaddr2; /* individual address filter 2*/
|
| 372 |
|
|
cyg_uint16 iaddr3; /* individual address filter 3*/
|
| 373 |
|
|
cyg_uint16 iaddr4; /* individual address filter 4*/
|
| 374 |
|
|
cyg_uint16 boff_cnt; /* back-off counter */
|
| 375 |
|
|
cyg_uint16 taddr_h; /* temp address (MSB) */
|
| 376 |
|
|
cyg_uint16 taddr_m; /* temp address */
|
| 377 |
|
|
cyg_uint16 taddr_l; /* temp address (LSB) */
|
| 378 |
|
|
};
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
/*------------------------------------------------------------------*/
|
| 382 |
|
|
/* QMC definitions */
|
| 383 |
|
|
/*------------------------------------------------------------------*/
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
struct global_qmc_pram {
|
| 387 |
|
|
|
| 388 |
|
|
cyg_uint32 mcbase; /* Multichannel Base pointer */
|
| 389 |
|
|
cyg_uint16 qmcstate; /* Multichannel Controller state */
|
| 390 |
|
|
cyg_uint16 mrblr; /* Maximum Receive Buffer Length */
|
| 391 |
|
|
cyg_uint16 tx_s_ptr; /* TSATTx Pointer */
|
| 392 |
|
|
cyg_uint16 rxptr; /* Current Time slot entry in TSATRx */
|
| 393 |
|
|
cyg_uint16 grfthr; /* Global Receive frame threshold */
|
| 394 |
|
|
cyg_uint16 grfcnt; /* Global Receive Frame Count */
|
| 395 |
|
|
cyg_uint32 intbase; /* Multichannel Base address */
|
| 396 |
|
|
cyg_uint32 intptr; /* Pointer to interrupt queue */
|
| 397 |
|
|
cyg_uint16 rx_s_ptr; /* TSATRx Pointer */
|
| 398 |
|
|
cyg_uint16 txptr; /* Current Time slot entry in TSATTx */
|
| 399 |
|
|
cyg_uint32 c_mask32; /* CRC Constant (debb20e3) */
|
| 400 |
|
|
cyg_uint16 tsatrx[32]; /* Time Slot Assignment Table Rx */
|
| 401 |
|
|
cyg_uint16 tsattx[32]; /* Time Slot Assignment Table Tx */
|
| 402 |
|
|
cyg_uint16 c_mask16; /* CRC Constant (f0b8) */
|
| 403 |
|
|
|
| 404 |
|
|
};
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
/*------------------------------------------*/
|
| 408 |
|
|
/* QMC HDLC channel specific parameter RAM */
|
| 409 |
|
|
/*------------------------------------------*/
|
| 410 |
|
|
|
| 411 |
|
|
struct qmc_hdlc_pram {
|
| 412 |
|
|
|
| 413 |
|
|
cyg_uint16 tbase; /* Tx Buffer Descriptors Base Address */
|
| 414 |
|
|
cyg_uint16 chamr; /* Channel Mode Register */
|
| 415 |
|
|
cyg_uint32 tstate; /* Tx Internal State */
|
| 416 |
|
|
cyg_uint32 txintr; /* Tx Internal Data Pointer */
|
| 417 |
|
|
cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */
|
| 418 |
|
|
cyg_uint16 txcntr; /* Tx Internal Byte Count */
|
| 419 |
|
|
cyg_uint32 tupack; /* (Tx Temp) */
|
| 420 |
|
|
cyg_uint32 zistate; /* Zero Insertion machine state */
|
| 421 |
|
|
cyg_uint32 tcrc; /* Temp Transmit CRC */
|
| 422 |
|
|
cyg_uint16 intmsk; /* Channel's interrupt mask flags */
|
| 423 |
|
|
cyg_uint16 bdflags;
|
| 424 |
|
|
cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */
|
| 425 |
|
|
cyg_uint16 mflr; /* Max Frame Length Register */
|
| 426 |
|
|
cyg_uint32 rstate; /* Rx Internal State */
|
| 427 |
|
|
cyg_uint32 rxintr; /* Rx Internal Data Pointer */
|
| 428 |
|
|
cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */
|
| 429 |
|
|
cyg_uint16 rxbyc; /* Rx Internal Byte Count */
|
| 430 |
|
|
cyg_uint32 rpack; /* (Rx Temp) */
|
| 431 |
|
|
cyg_uint32 zdstate; /* Zero Deletion machine state */
|
| 432 |
|
|
cyg_uint32 rcrc; /* Temp Transmit CRC */
|
| 433 |
|
|
cyg_uint16 maxc; /* Max_length counter */
|
| 434 |
|
|
cyg_uint16 tmp_mb; /* Temp */
|
| 435 |
|
|
};
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
/*-------------------------------------------------*/
|
| 439 |
|
|
/* QMC Transparent channel specific parameter RAM */
|
| 440 |
|
|
/*-------------------------------------------------*/
|
| 441 |
|
|
|
| 442 |
|
|
struct qmc_tran_pram {
|
| 443 |
|
|
|
| 444 |
|
|
cyg_uint16 tbase; /* Tx Bufer Descriptors Base Address */
|
| 445 |
|
|
cyg_uint16 chamr; /* Channel Mode Register */
|
| 446 |
|
|
cyg_uint32 tstate; /* Tx Internal State */
|
| 447 |
|
|
cyg_uint32 txintr; /* Tx Internal Data Pointer */
|
| 448 |
|
|
cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */
|
| 449 |
|
|
cyg_uint16 txcntr; /* Tx Internal Byte Count */
|
| 450 |
|
|
cyg_uint32 tupack; /* (Tx Temp) */
|
| 451 |
|
|
cyg_uint32 zistate; /* Zero Insertion machine state */
|
| 452 |
|
|
cyg_uint32 RESERVED8;
|
| 453 |
|
|
cyg_uint16 intmsk; /* Channel's interrupt mask flags */
|
| 454 |
|
|
cyg_uint16 bdflags;
|
| 455 |
|
|
cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */
|
| 456 |
|
|
cyg_uint16 tmrblr; /* Max receive buffer length */
|
| 457 |
|
|
cyg_uint32 rstate; /* Rx Internal State */
|
| 458 |
|
|
cyg_uint32 rxintr; /* Rx Internal Data Pointer */
|
| 459 |
|
|
cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */
|
| 460 |
|
|
cyg_uint16 rxbyc; /* Rx Internal Byte Count */
|
| 461 |
|
|
cyg_uint32 rpack; /* (Rx Temp) */
|
| 462 |
|
|
cyg_uint32 zdstate; /* Zero Deletion machine state */
|
| 463 |
|
|
cyg_uint32 RESERVED9; /* Temp Transmit CRC */
|
| 464 |
|
|
cyg_uint16 trnsync; /* Max_length counter */
|
| 465 |
|
|
cyg_uint16 RESERVED10; /* Temp */
|
| 466 |
|
|
|
| 467 |
|
|
};
|
| 468 |
|
|
|
| 469 |
|
|
/*----------------------------------------------------------*/
|
| 470 |
|
|
/* allows multiprotocol array declaration in the memory map */
|
| 471 |
|
|
/*----------------------------------------------------------*/
|
| 472 |
|
|
|
| 473 |
|
|
struct qmc_chan_pram
|
| 474 |
|
|
{
|
| 475 |
|
|
union
|
| 476 |
|
|
{
|
| 477 |
|
|
struct qmc_hdlc_pram h;
|
| 478 |
|
|
struct qmc_tran_pram t;
|
| 479 |
|
|
}h_or_t;
|
| 480 |
|
|
};
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
/*--------------------------------------------------------------------*/
|
| 485 |
|
|
/* SMC UART parameter RAM */
|
| 486 |
|
|
/*--------------------------------------------------------------------*/
|
| 487 |
|
|
|
| 488 |
|
|
struct smc_uart_pram
|
| 489 |
|
|
|
| 490 |
|
|
{
|
| 491 |
|
|
cyg_uint16 rbase; /* Rx BD Base Address */
|
| 492 |
|
|
cyg_uint16 tbase; /* Tx BD Base Address */
|
| 493 |
|
|
cyg_uint8 rfcr; /* Rx function code */
|
| 494 |
|
|
cyg_uint8 tfcr; /* Tx function code */
|
| 495 |
|
|
cyg_uint16 mrblr; /* Rx buffer length */
|
| 496 |
|
|
cyg_uint32 rstate; /* Rx internal state */
|
| 497 |
|
|
cyg_uint32 rptr; /* Rx internal data pointer */
|
| 498 |
|
|
cyg_uint16 rbptr; /* rb BD Pointer */
|
| 499 |
|
|
cyg_uint16 rcount; /* Rx internal byte count */
|
| 500 |
|
|
cyg_uint32 rtemp; /* Rx temp */
|
| 501 |
|
|
cyg_uint32 tstate; /* Tx internal state */
|
| 502 |
|
|
cyg_uint32 tptr; /* Tx internal data pointer */
|
| 503 |
|
|
cyg_uint16 tbptr; /* Tx BD pointer */
|
| 504 |
|
|
cyg_uint16 tcount; /* Tx byte count */
|
| 505 |
|
|
cyg_uint32 ttemp; /* Tx temp */
|
| 506 |
|
|
cyg_uint16 max_idl; /* Maximum IDLE Characters */
|
| 507 |
|
|
cyg_uint16 idlc; /* Temporary IDLE Counter */
|
| 508 |
|
|
cyg_uint16 brkln; /* Last Rx Break Length */
|
| 509 |
|
|
cyg_uint16 brkec; /* Rx Break Condition Counter */
|
| 510 |
|
|
cyg_uint16 brkcr; /* Break Count Register (Tx) */
|
| 511 |
|
|
cyg_uint16 r_mask; /* Temporary bit mask */
|
| 512 |
|
|
};
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
/*--------------------------------------------------------------------------*/
|
| 516 |
|
|
/* SMC Transparent mode parameter RAM */
|
| 517 |
|
|
/*--------------------------------------------------------------------------*/
|
| 518 |
|
|
|
| 519 |
|
|
struct smc_trnsp_pram
|
| 520 |
|
|
|
| 521 |
|
|
{
|
| 522 |
|
|
cyg_uint16 rbase; /* Rx BD Base Address */
|
| 523 |
|
|
cyg_uint16 tbase; /* Tx BD Base Address */
|
| 524 |
|
|
cyg_uint8 rfcr; /* Rx function code */
|
| 525 |
|
|
cyg_uint8 tfcr; /* Tx function code */
|
| 526 |
|
|
cyg_uint16 mrblr; /* Rx buffer length */
|
| 527 |
|
|
cyg_uint32 rstate; /* Rx internal state */
|
| 528 |
|
|
cyg_uint32 rptr; /* Rx internal data pointer */
|
| 529 |
|
|
cyg_uint16 rbptr; /* rb BD Pointer */
|
| 530 |
|
|
cyg_uint16 rcount; /* Rx internal byte count */
|
| 531 |
|
|
cyg_uint32 rtemp; /* Rx temp */
|
| 532 |
|
|
cyg_uint32 tstate; /* Tx internal state */
|
| 533 |
|
|
cyg_uint32 tptr; /* Tx internal data pointer */
|
| 534 |
|
|
cyg_uint16 tbptr; /* Tx BD pointer */
|
| 535 |
|
|
cyg_uint16 tcount; /* Tx byte count */
|
| 536 |
|
|
cyg_uint32 ttemp; /* Tx temp */
|
| 537 |
|
|
cyg_uint16 RESERVED11[5]; /* Reserved */
|
| 538 |
|
|
};
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
/*--------------------------------------------------------------------------*/
|
| 542 |
|
|
/* SPI parameter RAM */
|
| 543 |
|
|
/*--------------------------------------------------------------------------*/
|
| 544 |
|
|
|
| 545 |
|
|
#define SPI_R 0x8000 /* Ready bit in BD */
|
| 546 |
|
|
|
| 547 |
|
|
struct spi_pram
|
| 548 |
|
|
|
| 549 |
|
|
{
|
| 550 |
|
|
cyg_uint16 rbase; /* Rx BD Base Address */
|
| 551 |
|
|
cyg_uint16 tbase; /* Tx BD Base Address */
|
| 552 |
|
|
cyg_uint8 rfcr; /* Rx function code */
|
| 553 |
|
|
cyg_uint8 tfcr; /* Tx function code */
|
| 554 |
|
|
cyg_uint16 mrblr; /* Rx buffer length */
|
| 555 |
|
|
cyg_uint32 rstate; /* Rx internal state */
|
| 556 |
|
|
cyg_uint32 rptr; /* Rx internal data pointer */
|
| 557 |
|
|
cyg_uint16 rbptr; /* rb BD Pointer */
|
| 558 |
|
|
cyg_uint16 rcount; /* Rx internal byte count */
|
| 559 |
|
|
cyg_uint32 rtemp; /* Rx temp */
|
| 560 |
|
|
cyg_uint32 tstate; /* Tx internal state */
|
| 561 |
|
|
cyg_uint32 tptr; /* Tx internal data pointer */
|
| 562 |
|
|
cyg_uint16 tbptr; /* Tx BD pointer */
|
| 563 |
|
|
cyg_uint16 tcount; /* Tx byte count */
|
| 564 |
|
|
cyg_uint32 ttemp; /* Tx temp */
|
| 565 |
|
|
|
| 566 |
|
|
cyg_uint8 RESERVED12[8]; /* Reserved */
|
| 567 |
|
|
};
|
| 568 |
|
|
|
| 569 |
|
|
|
| 570 |
|
|
/*--------------------------------------------------------------------------*/
|
| 571 |
|
|
/* I2C parameter RAM */
|
| 572 |
|
|
/*--------------------------------------------------------------------------*/
|
| 573 |
|
|
|
| 574 |
|
|
struct i2c_pram
|
| 575 |
|
|
|
| 576 |
|
|
{
|
| 577 |
|
|
/*--------------------*/
|
| 578 |
|
|
/* I2C parameter RAM */
|
| 579 |
|
|
/*--------------------*/
|
| 580 |
|
|
|
| 581 |
|
|
cyg_uint16 rbase; /* RX BD base address */
|
| 582 |
|
|
cyg_uint16 tbase; /* TX BD base address */
|
| 583 |
|
|
cyg_uint8 rfcr; /* Rx function code */
|
| 584 |
|
|
cyg_uint8 tfcr; /* Tx function code */
|
| 585 |
|
|
cyg_uint16 mrblr; /* Rx buffer length */
|
| 586 |
|
|
cyg_uint32 rstate; /* Rx internal state */
|
| 587 |
|
|
cyg_uint32 rptr; /* Rx internal data pointer */
|
| 588 |
|
|
cyg_uint16 rbptr; /* rb BD Pointer */
|
| 589 |
|
|
cyg_uint16 rcount; /* Rx internal byte count */
|
| 590 |
|
|
cyg_uint32 rtemp; /* Rx temp */
|
| 591 |
|
|
cyg_uint32 tstate; /* Tx internal state */
|
| 592 |
|
|
cyg_uint32 tptr; /* Tx internal data pointer */
|
| 593 |
|
|
cyg_uint16 tbptr; /* Tx BD pointer */
|
| 594 |
|
|
cyg_uint16 tcount; /* Tx byte count */
|
| 595 |
|
|
cyg_uint32 ttemp; /* Tx temp */
|
| 596 |
|
|
|
| 597 |
|
|
cyg_uint8 RESERVED13[8];
|
| 598 |
|
|
};
|
| 599 |
|
|
|
| 600 |
|
|
/*--------------------------------------------------------------------------*/
|
| 601 |
|
|
/* MISC parameter RAM */
|
| 602 |
|
|
/*--------------------------------------------------------------------------*/
|
| 603 |
|
|
|
| 604 |
|
|
struct misc_pram
|
| 605 |
|
|
{
|
| 606 |
|
|
cyg_uint8 RESERVED14[16];
|
| 607 |
|
|
};
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
|
| 611 |
|
|
/*--------------------------------------------------------------------------*/
|
| 612 |
|
|
/* PIP Centronics parameter RAM */
|
| 613 |
|
|
/*--------------------------------------------------------------------------*/
|
| 614 |
|
|
|
| 615 |
|
|
struct centronics_pram
|
| 616 |
|
|
|
| 617 |
|
|
{
|
| 618 |
|
|
cyg_uint16 rbase; /* Rx BD Base Address */
|
| 619 |
|
|
cyg_uint16 tbase; /* Tx BD Base Address */
|
| 620 |
|
|
cyg_uint8 fcr; /* function code */
|
| 621 |
|
|
cyg_uint8 smask; /* Status Mask */
|
| 622 |
|
|
cyg_uint16 mrblr; /* Rx buffer length */
|
| 623 |
|
|
cyg_uint32 rstate; /* Rx internal state */
|
| 624 |
|
|
cyg_uint32 rptr; /* Rx internal data pointer */
|
| 625 |
|
|
cyg_uint16 rbptr; /* rb BD Pointer */
|
| 626 |
|
|
cyg_uint16 rcount; /* Rx internal byte count */
|
| 627 |
|
|
cyg_uint32 rtemp; /* Rx temp */
|
| 628 |
|
|
cyg_uint32 tstate; /* Tx internal state */
|
| 629 |
|
|
cyg_uint32 tptr; /* Tx internal data pointer */
|
| 630 |
|
|
cyg_uint16 tbptr; /* Tx BD pointer */
|
| 631 |
|
|
cyg_uint16 tcount; /* Tx byte count */
|
| 632 |
|
|
cyg_uint32 ttemp; /* Tx temp */
|
| 633 |
|
|
cyg_uint16 max_sl; /* Maximum Silence period */
|
| 634 |
|
|
cyg_uint16 sl_cnt; /* Silence Counter */
|
| 635 |
|
|
cyg_uint16 char1; /* CONTROL char 1 */
|
| 636 |
|
|
cyg_uint16 char2; /* CONTROL char 2 */
|
| 637 |
|
|
cyg_uint16 char3; /* CONTROL char 3 */
|
| 638 |
|
|
cyg_uint16 char4; /* CONTROL char 4 */
|
| 639 |
|
|
cyg_uint16 char5; /* CONTROL char 5 */
|
| 640 |
|
|
cyg_uint16 char6; /* CONTROL char 6 */
|
| 641 |
|
|
cyg_uint16 char7; /* CONTROL char 7 */
|
| 642 |
|
|
cyg_uint16 char8; /* CONTROL char 8 */
|
| 643 |
|
|
cyg_uint16 rccm; /* Rx Control Char Mask */
|
| 644 |
|
|
cyg_uint16 rccr; /* Rx Char Control Register */
|
| 645 |
|
|
};
|
| 646 |
|
|
|
| 647 |
|
|
|
| 648 |
|
|
/*--------------------------------------------------------------------------*/
|
| 649 |
|
|
/* IDMA parameter RAM */
|
| 650 |
|
|
/*--------------------------------------------------------------------------*/
|
| 651 |
|
|
|
| 652 |
|
|
struct idma_pram
|
| 653 |
|
|
|
| 654 |
|
|
{
|
| 655 |
|
|
cyg_uint16 ibase; /* IDMA BD Base Address */
|
| 656 |
|
|
cyg_uint16 dcmr; /* DMA Channel Mode Register */
|
| 657 |
|
|
cyg_uint32 sapr; /* Source Internal Data Pointer */
|
| 658 |
|
|
cyg_uint32 dapr; /* Destination Internal Data Pointer */
|
| 659 |
|
|
cyg_uint16 ibptr; /* Buffer Descriptor Pointer */
|
| 660 |
|
|
cyg_uint16 write_sp; /* No description given in manual */
|
| 661 |
|
|
cyg_uint32 s_byte_c; /* Internal Source Byte Count */
|
| 662 |
|
|
cyg_uint32 d_byte_c; /* Internal Destination Byte Count */
|
| 663 |
|
|
cyg_uint32 s_state; /* Internal State */
|
| 664 |
|
|
cyg_uint32 itemp0; /* Temp Data Storage */
|
| 665 |
|
|
cyg_uint32 itemp1; /* Temp Data Storage */
|
| 666 |
|
|
cyg_uint32 itemp2; /* Temp Data Storage */
|
| 667 |
|
|
cyg_uint32 itemp3; /* Temp Data Storage */
|
| 668 |
|
|
cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */
|
| 669 |
|
|
cyg_uint16 read_sp; /* No description given in manual */
|
| 670 |
|
|
cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/
|
| 671 |
|
|
cyg_uint16 nodesc1; /* Temp Storage Address Pointer */
|
| 672 |
|
|
cyg_uint16 nodesc2; /* SR_MEM Byte Count */
|
| 673 |
|
|
cyg_uint32 d_state; /* Internal State */
|
| 674 |
|
|
};
|
| 675 |
|
|
|
| 676 |
|
|
|
| 677 |
|
|
|
| 678 |
|
|
/*--------------------------------------------------------------------------*/
|
| 679 |
|
|
/* RISC timer parameter RAM */
|
| 680 |
|
|
/*--------------------------------------------------------------------------*/
|
| 681 |
|
|
|
| 682 |
|
|
struct timer_pram
|
| 683 |
|
|
|
| 684 |
|
|
{
|
| 685 |
|
|
/*----------------------------*/
|
| 686 |
|
|
/* RISC timers parameter RAM */
|
| 687 |
|
|
/*----------------------------*/
|
| 688 |
|
|
|
| 689 |
|
|
cyg_uint16 tm_base; /* RISC timer table base adr */
|
| 690 |
|
|
cyg_uint16 tm_ptr; /* RISC timer table pointer */
|
| 691 |
|
|
cyg_uint16 r_tmr; /* RISC timer mode register */
|
| 692 |
|
|
cyg_uint16 r_tmv; /* RISC timer valid register */
|
| 693 |
|
|
cyg_uint32 tm_cmd; /* RISC timer cmd register */
|
| 694 |
|
|
cyg_uint32 tm_cnt; /* RISC timer internal cnt */
|
| 695 |
|
|
};
|
| 696 |
|
|
|
| 697 |
|
|
|
| 698 |
|
|
/*--------------------------------------------------------------------------*/
|
| 699 |
|
|
/* ROM Microcode parameter RAM */
|
| 700 |
|
|
/*--------------------------------------------------------------------------*/
|
| 701 |
|
|
|
| 702 |
|
|
struct ucode_pram
|
| 703 |
|
|
|
| 704 |
|
|
{
|
| 705 |
|
|
/*---------------------------*/
|
| 706 |
|
|
/* RISC ucode parameter RAM */
|
| 707 |
|
|
/*---------------------------*/
|
| 708 |
|
|
|
| 709 |
|
|
cyg_uint16 rev_num; /* Ucode Revision Number */
|
| 710 |
|
|
cyg_uint16 d_ptr; /* MISC Dump area pointer */
|
| 711 |
|
|
cyg_uint32 temp1; /* MISC Temp1 */
|
| 712 |
|
|
cyg_uint32 temp2; /* MISC Temp2 */
|
| 713 |
|
|
};
|
| 714 |
|
|
|
| 715 |
|
|
|
| 716 |
|
|
/*---------------------------------------------------------------------------*/
|
| 717 |
|
|
/* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */
|
| 718 |
|
|
/* Note that this area can also be used by microcodes and the QMC channel */
|
| 719 |
|
|
/* specific parameter ram. */
|
| 720 |
|
|
/*---------------------------------------------------------------------------*/
|
| 721 |
|
|
|
| 722 |
|
|
struct user_data
|
| 723 |
|
|
|
| 724 |
|
|
{
|
| 725 |
|
|
|
| 726 |
|
|
volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */
|
| 727 |
|
|
volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */
|
| 728 |
|
|
volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */
|
| 729 |
|
|
volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/
|
| 730 |
|
|
volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/
|
| 731 |
|
|
volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */
|
| 732 |
|
|
|
| 733 |
|
|
};
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
|
| 737 |
|
|
/***************************************************************************/
|
| 738 |
|
|
/* */
|
| 739 |
|
|
/* Definitions of Embedded PowerPC (EPPC) internal memory structures, */
|
| 740 |
|
|
/* including registers and dual-port RAM */
|
| 741 |
|
|
/* */
|
| 742 |
|
|
/***************************************************************************/
|
| 743 |
|
|
|
| 744 |
|
|
typedef struct eppc
|
| 745 |
|
|
|
| 746 |
|
|
{
|
| 747 |
|
|
/*-----------------------------------*/
|
| 748 |
|
|
/* BASE + 0x0000: INTERNAL REGISTERS */
|
| 749 |
|
|
/*-----------------------------------*/
|
| 750 |
|
|
|
| 751 |
|
|
/*-----*/
|
| 752 |
|
|
/* SIU */
|
| 753 |
|
|
/*-----*/
|
| 754 |
|
|
|
| 755 |
|
|
volatile cyg_uint32 siu_mcr; /* module configuration reg */
|
| 756 |
|
|
volatile cyg_uint32 siu_sypcr; /* System protection cnt */
|
| 757 |
|
|
cyg_uint8 RESERVED13[0x6];
|
| 758 |
|
|
volatile cyg_uint16 siu_swsr; /* sw service */
|
| 759 |
|
|
volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */
|
| 760 |
|
|
volatile cyg_uint32 siu_simask; /* Interrupt mask reg */
|
| 761 |
|
|
volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */
|
| 762 |
|
|
volatile cyg_uint32 siu_sivec; /* Interrupt vector */
|
| 763 |
|
|
volatile cyg_uint32 siu_tesr; /* Transfer error status */
|
| 764 |
|
|
volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */
|
| 765 |
|
|
volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */
|
| 766 |
|
|
cyg_uint8 RESERVED15[0x4c];
|
| 767 |
|
|
|
| 768 |
|
|
/*--------*/
|
| 769 |
|
|
/* PCMCIA */
|
| 770 |
|
|
/*--------*/
|
| 771 |
|
|
|
| 772 |
|
|
volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
|
| 773 |
|
|
volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
|
| 774 |
|
|
volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
|
| 775 |
|
|
volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
|
| 776 |
|
|
volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
|
| 777 |
|
|
volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
|
| 778 |
|
|
volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
|
| 779 |
|
|
volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
|
| 780 |
|
|
volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
|
| 781 |
|
|
volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
|
| 782 |
|
|
volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
|
| 783 |
|
|
volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
|
| 784 |
|
|
volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
|
| 785 |
|
|
volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
|
| 786 |
|
|
volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
|
| 787 |
|
|
volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
|
| 788 |
|
|
volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */
|
| 789 |
|
|
volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
|
| 790 |
|
|
volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
|
| 791 |
|
|
volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */
|
| 792 |
|
|
volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */
|
| 793 |
|
|
volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */
|
| 794 |
|
|
volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */
|
| 795 |
|
|
volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */
|
| 796 |
|
|
volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */
|
| 797 |
|
|
|
| 798 |
|
|
/*------*/
|
| 799 |
|
|
/* MEMC */
|
| 800 |
|
|
/*------*/
|
| 801 |
|
|
|
| 802 |
|
|
volatile cyg_uint32 memc_br0; /* base register 0 */
|
| 803 |
|
|
volatile cyg_uint32 memc_or0; /* option register 0 */
|
| 804 |
|
|
volatile cyg_uint32 memc_br1; /* base register 1 */
|
| 805 |
|
|
volatile cyg_uint32 memc_or1; /* option register 1 */
|
| 806 |
|
|
volatile cyg_uint32 memc_br2; /* base register 2 */
|
| 807 |
|
|
volatile cyg_uint32 memc_or2; /* option register 2 */
|
| 808 |
|
|
volatile cyg_uint32 memc_br3; /* base register 3 */
|
| 809 |
|
|
volatile cyg_uint32 memc_or3; /* option register 3 */
|
| 810 |
|
|
volatile cyg_uint32 memc_br4; /* base register 3 */
|
| 811 |
|
|
volatile cyg_uint32 memc_or4; /* option register 3 */
|
| 812 |
|
|
volatile cyg_uint32 memc_br5; /* base register 3 */
|
| 813 |
|
|
volatile cyg_uint32 memc_or5; /* option register 3 */
|
| 814 |
|
|
volatile cyg_uint32 memc_br6; /* base register 3 */
|
| 815 |
|
|
volatile cyg_uint32 memc_or6; /* option register 3 */
|
| 816 |
|
|
volatile cyg_uint32 memc_br7; /* base register 3 */
|
| 817 |
|
|
volatile cyg_uint32 memc_or7; /* option register 3 */
|
| 818 |
|
|
volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */
|
| 819 |
|
|
volatile cyg_uint32 memc_mar; /* Memory address */
|
| 820 |
|
|
volatile cyg_uint32 memc_mcr; /* Memory command */
|
| 821 |
|
|
volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */
|
| 822 |
|
|
volatile cyg_uint32 memc_mamr; /* Machine A mode */
|
| 823 |
|
|
volatile cyg_uint32 memc_mbmr; /* Machine B mode */
|
| 824 |
|
|
volatile cyg_uint16 memc_mstat; /* Memory status */
|
| 825 |
|
|
volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */
|
| 826 |
|
|
volatile cyg_uint32 memc_mdr; /* Memory data */
|
| 827 |
|
|
volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */
|
| 828 |
|
|
|
| 829 |
|
|
/*---------------------------*/
|
| 830 |
|
|
/* SYSTEM INTEGRATION TIMERS */
|
| 831 |
|
|
/*---------------------------*/
|
| 832 |
|
|
|
| 833 |
|
|
volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */
|
| 834 |
|
|
volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */
|
| 835 |
|
|
volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */
|
| 836 |
|
|
volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */
|
| 837 |
|
|
volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */
|
| 838 |
|
|
volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */
|
| 839 |
|
|
volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */
|
| 840 |
|
|
volatile cyg_uint32 simt_rtc; /* Realtime clock */
|
| 841 |
|
|
volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */
|
| 842 |
|
|
volatile cyg_uint32 simt_rtcal; /* Realtime alarm */
|
| 843 |
|
|
volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */
|
| 844 |
|
|
volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */
|
| 845 |
|
|
volatile cyg_uint32 simt_pitc; /* PIT counter */
|
| 846 |
|
|
volatile cyg_uint32 simt_pitr; /* PIT */
|
| 847 |
|
|
volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */
|
| 848 |
|
|
|
| 849 |
|
|
/*---------------*/
|
| 850 |
|
|
/* CLOCKS, RESET */
|
| 851 |
|
|
/*---------------*/
|
| 852 |
|
|
|
| 853 |
|
|
volatile cyg_uint32 clkr_sccr; /* System clk cntrl */
|
| 854 |
|
|
volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */
|
| 855 |
|
|
volatile cyg_uint32 clkr_rsr; /* reset status */
|
| 856 |
|
|
cyg_uint8 RESERVED28[0x74]; /* Reserved area */
|
| 857 |
|
|
|
| 858 |
|
|
/*--------------------------------*/
|
| 859 |
|
|
/* System Integration Timers Keys */
|
| 860 |
|
|
/*--------------------------------*/
|
| 861 |
|
|
|
| 862 |
|
|
volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */
|
| 863 |
|
|
volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */
|
| 864 |
|
|
volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */
|
| 865 |
|
|
volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */
|
| 866 |
|
|
cyg_uint8 RESERVED29[0x10]; /* Reserved area */
|
| 867 |
|
|
volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
|
| 868 |
|
|
|
| 869 |
|
|
volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */
|
| 870 |
|
|
volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */
|
| 871 |
|
|
volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */
|
| 872 |
|
|
cyg_uint8 RESERVED30[0x10]; /* Reserved area */
|
| 873 |
|
|
volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
|
| 874 |
|
|
volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */
|
| 875 |
|
|
cyg_uint8 RESERVED31[0x38]; /* Reserved area */
|
| 876 |
|
|
|
| 877 |
|
|
/*----------------------*/
|
| 878 |
|
|
/* Clock and Reset Keys */
|
| 879 |
|
|
/*----------------------*/
|
| 880 |
|
|
|
| 881 |
|
|
volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */
|
| 882 |
|
|
volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
|
| 883 |
|
|
volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */
|
| 884 |
|
|
cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */
|
| 885 |
|
|
|
| 886 |
|
|
/*-----*/
|
| 887 |
|
|
/* I2C */
|
| 888 |
|
|
/*-----*/
|
| 889 |
|
|
|
| 890 |
|
|
volatile cyg_uint8 i2c_i2mod; /* i2c mode */
|
| 891 |
|
|
cyg_uint8 RESERVED33[3];
|
| 892 |
|
|
volatile cyg_uint8 i2c_i2add; /* i2c address */
|
| 893 |
|
|
cyg_uint8 RESERVED34[3];
|
| 894 |
|
|
volatile cyg_uint8 i2c_i2brg; /* i2c brg */
|
| 895 |
|
|
cyg_uint8 RESERVED35[3];
|
| 896 |
|
|
volatile cyg_uint8 i2c_i2com; /* i2c command */
|
| 897 |
|
|
cyg_uint8 RESERVED36[3];
|
| 898 |
|
|
volatile cyg_uint8 i2c_i2cer; /* i2c event */
|
| 899 |
|
|
cyg_uint8 RESERVED37[3];
|
| 900 |
|
|
volatile cyg_uint8 i2c_i2cmr; /* i2c mask */
|
| 901 |
|
|
volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */
|
| 902 |
|
|
|
| 903 |
|
|
/*-----*/
|
| 904 |
|
|
/* DMA */
|
| 905 |
|
|
/*-----*/
|
| 906 |
|
|
|
| 907 |
|
|
volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */
|
| 908 |
|
|
volatile cyg_uint32 dma_sdar; /* SDMA address reg */
|
| 909 |
|
|
volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */
|
| 910 |
|
|
volatile cyg_uint8 dma_sdsr; /* SDMA status reg */
|
| 911 |
|
|
volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */
|
| 912 |
|
|
volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */
|
| 913 |
|
|
volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */
|
| 914 |
|
|
volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */
|
| 915 |
|
|
volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */
|
| 916 |
|
|
volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */
|
| 917 |
|
|
volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */
|
| 918 |
|
|
volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */
|
| 919 |
|
|
volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */
|
| 920 |
|
|
volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */
|
| 921 |
|
|
volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */
|
| 922 |
|
|
|
| 923 |
|
|
/*--------------------------*/
|
| 924 |
|
|
/* CPM Interrupt Controller */
|
| 925 |
|
|
/*--------------------------*/
|
| 926 |
|
|
|
| 927 |
|
|
volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */
|
| 928 |
|
|
volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */
|
| 929 |
|
|
volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */
|
| 930 |
|
|
volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */
|
| 931 |
|
|
volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */
|
| 932 |
|
|
volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */
|
| 933 |
|
|
|
| 934 |
|
|
/*----------*/
|
| 935 |
|
|
/* I/O port */
|
| 936 |
|
|
/*----------*/
|
| 937 |
|
|
|
| 938 |
|
|
volatile cyg_uint16 pio_padir; /* port A data direction reg */
|
| 939 |
|
|
volatile cyg_uint16 pio_papar; /* port A pin assignment reg */
|
| 940 |
|
|
volatile cyg_uint16 pio_paodr; /* port A open drain reg */
|
| 941 |
|
|
volatile cyg_uint16 pio_padat; /* port A data register */
|
| 942 |
|
|
volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */
|
| 943 |
|
|
volatile cyg_uint16 pio_pcdir; /* port C data direction reg */
|
| 944 |
|
|
volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */
|
| 945 |
|
|
volatile cyg_uint16 pio_pcso; /* port C special options */
|
| 946 |
|
|
volatile cyg_uint16 pio_pcdat; /* port C data register */
|
| 947 |
|
|
volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */
|
| 948 |
|
|
cyg_uint8 RESERVED49[6];
|
| 949 |
|
|
volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */
|
| 950 |
|
|
volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */
|
| 951 |
|
|
cyg_uint8 RESERVED50[2];
|
| 952 |
|
|
volatile cyg_uint16 pio_pddat; /* port D data reg */
|
| 953 |
|
|
volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */
|
| 954 |
|
|
|
| 955 |
|
|
/*-----------*/
|
| 956 |
|
|
/* CPM Timer */
|
| 957 |
|
|
/*-----------*/
|
| 958 |
|
|
|
| 959 |
|
|
volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */
|
| 960 |
|
|
volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */
|
| 961 |
|
|
volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */
|
| 962 |
|
|
volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */
|
| 963 |
|
|
volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */
|
| 964 |
|
|
volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */
|
| 965 |
|
|
volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */
|
| 966 |
|
|
volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */
|
| 967 |
|
|
volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */
|
| 968 |
|
|
volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */
|
| 969 |
|
|
volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */
|
| 970 |
|
|
volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */
|
| 971 |
|
|
volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */
|
| 972 |
|
|
volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */
|
| 973 |
|
|
volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */
|
| 974 |
|
|
volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */
|
| 975 |
|
|
volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */
|
| 976 |
|
|
volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */
|
| 977 |
|
|
volatile cyg_uint16 timer_ter1; /* timer 1 event reg */
|
| 978 |
|
|
volatile cyg_uint16 timer_ter2; /* timer 2 event reg */
|
| 979 |
|
|
volatile cyg_uint16 timer_ter3; /* timer 3 event reg */
|
| 980 |
|
|
volatile cyg_uint16 timer_ter4; /* timer 4 event reg */
|
| 981 |
|
|
volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */
|
| 982 |
|
|
|
| 983 |
|
|
/*----*/
|
| 984 |
|
|
/* CP */
|
| 985 |
|
|
/*----*/
|
| 986 |
|
|
|
| 987 |
|
|
volatile cyg_uint16 cp_cr; /* command register */
|
| 988 |
|
|
volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */
|
| 989 |
|
|
volatile cyg_uint16 cp_rccr; /* main configuration reg */
|
| 990 |
|
|
volatile cyg_uint8 RESERVED55; /* Reserved area */
|
| 991 |
|
|
volatile cyg_uint8 cp_resv1; /* Reserved reg */
|
| 992 |
|
|
volatile cyg_uint32 cp_resv2; /* Reserved reg */
|
| 993 |
|
|
volatile cyg_uint16 cp_rctr1; /* ram break register 1 */
|
| 994 |
|
|
volatile cyg_uint16 cp_rctr2; /* ram break register 2 */
|
| 995 |
|
|
volatile cyg_uint16 cp_rctr3; /* ram break register 3 */
|
| 996 |
|
|
volatile cyg_uint16 cp_rctr4; /* ram break register 4 */
|
| 997 |
|
|
volatile cyg_uint8 RESERVED56[0x2]; /* Reserved area */
|
| 998 |
|
|
volatile cyg_uint16 cp_rter; /* RISC timers event reg */
|
| 999 |
|
|
volatile cyg_uint8 RESERVED57[0x2]; /* Reserved area */
|
| 1000 |
|
|
volatile cyg_uint16 cp_rtmr; /* RISC timers mask reg */
|
| 1001 |
|
|
volatile cyg_uint8 RESERVED58[0x14]; /* Reserved area */
|
| 1002 |
|
|
|
| 1003 |
|
|
/*-----*/
|
| 1004 |
|
|
/* BRG */
|
| 1005 |
|
|
/*-----*/
|
| 1006 |
|
|
|
| 1007 |
|
|
volatile cyg_uint32 brgc1; /* BRG1 configuration reg */
|
| 1008 |
|
|
volatile cyg_uint32 brgc2; /* BRG2 configuration reg */
|
| 1009 |
|
|
volatile cyg_uint32 brgc3; /* BRG3 configuration reg */
|
| 1010 |
|
|
volatile cyg_uint32 brgc4; /* BRG4 configuration reg */
|
| 1011 |
|
|
|
| 1012 |
|
|
/*---------------*/
|
| 1013 |
|
|
/* SCC registers */
|
| 1014 |
|
|
/*---------------*/
|
| 1015 |
|
|
|
| 1016 |
|
|
struct scc_regs
|
| 1017 |
|
|
|
| 1018 |
|
|
{
|
| 1019 |
|
|
volatile cyg_uint32 scc_gsmr_l; /* SCC Gen mode (LOW) */
|
| 1020 |
|
|
volatile cyg_uint32 scc_gsmr_h; /* SCC Gen mode (HIGH) */
|
| 1021 |
|
|
volatile cyg_uint16 scc_psmr; /* protocol specific mode register */
|
| 1022 |
|
|
volatile cyg_uint8 RESERVED59[0x2]; /* Reserved area */
|
| 1023 |
|
|
volatile cyg_uint16 scc_todr; /* SCC transmit on demand */
|
| 1024 |
|
|
volatile cyg_uint16 scc_dsr; /* SCC data sync reg */
|
| 1025 |
|
|
volatile cyg_uint16 scc_scce; /* SCC event reg */
|
| 1026 |
|
|
volatile cyg_uint8 RESERVED60[0x2]; /* Reserved area */
|
| 1027 |
|
|
volatile cyg_uint16 scc_sccm; /* SCC mask reg */
|
| 1028 |
|
|
volatile cyg_uint8 RESERVED61[0x1]; /* Reserved area */
|
| 1029 |
|
|
volatile cyg_uint8 scc_sccs; /* SCC status reg */
|
| 1030 |
|
|
volatile cyg_uint8 RESERVED62[0x8]; /* Reserved area */
|
| 1031 |
|
|
|
| 1032 |
|
|
} scc_regs[4];
|
| 1033 |
|
|
|
| 1034 |
|
|
|
| 1035 |
|
|
/*-----*/
|
| 1036 |
|
|
/* SMC */
|
| 1037 |
|
|
/*-----*/
|
| 1038 |
|
|
|
| 1039 |
|
|
struct smc_regs
|
| 1040 |
|
|
|
| 1041 |
|
|
{
|
| 1042 |
|
|
volatile cyg_uint8 RESERVED63[0x2]; /* Reserved area */
|
| 1043 |
|
|
volatile cyg_uint16 smc_smcmr; /* SMC mode reg */
|
| 1044 |
|
|
volatile cyg_uint8 RESERVED64[0x2]; /* Reserved area */
|
| 1045 |
|
|
volatile cyg_uint8 smc_smce; /* SMC event reg */
|
| 1046 |
|
|
volatile cyg_uint8 RESERVED65[0x3]; /* Reserved area */
|
| 1047 |
|
|
volatile cyg_uint8 smc_smcm; /* SMC mask reg */
|
| 1048 |
|
|
volatile cyg_uint8 RESERVED66[0x5]; /* Reserved area */
|
| 1049 |
|
|
|
| 1050 |
|
|
} smc_regs[2];
|
| 1051 |
|
|
|
| 1052 |
|
|
|
| 1053 |
|
|
/*-----*/
|
| 1054 |
|
|
/* SPI */
|
| 1055 |
|
|
/*-----*/
|
| 1056 |
|
|
|
| 1057 |
|
|
volatile cyg_uint16 spi_spmode; /* SPI mode reg */
|
| 1058 |
|
|
volatile cyg_uint8 RESERVED67[0x4]; /* Reserved area */
|
| 1059 |
|
|
volatile cyg_uint8 spi_spie; /* SPI event reg */
|
| 1060 |
|
|
volatile cyg_uint8 RESERVED68[0x3]; /* Reserved area */
|
| 1061 |
|
|
volatile cyg_uint8 spi_spim; /* SPI mask reg */
|
| 1062 |
|
|
volatile cyg_uint8 RESERVED69[0x2]; /* Reserved area */
|
| 1063 |
|
|
volatile cyg_uint8 spi_spcom; /* SPI command reg */
|
| 1064 |
|
|
volatile cyg_uint8 RESERVED70[0x4]; /* Reserved area */
|
| 1065 |
|
|
|
| 1066 |
|
|
/*-----*/
|
| 1067 |
|
|
/* PIP */
|
| 1068 |
|
|
/*-----*/
|
| 1069 |
|
|
|
| 1070 |
|
|
volatile cyg_uint16 pip_pipc; /* pip configuration reg */
|
| 1071 |
|
|
volatile cyg_uint8 RESERVED71[0x2]; /* Reserved area */
|
| 1072 |
|
|
volatile cyg_uint16 pip_ptpr; /* pip timing parameters reg */
|
| 1073 |
|
|
volatile cyg_uint32 pip_pbdir; /* port b data direction reg */
|
| 1074 |
|
|
volatile cyg_uint32 pip_pbpar; /* port b pin assignment reg */
|
| 1075 |
|
|
volatile cyg_uint8 RESERVED72[0x2]; /* Reserved area */
|
| 1076 |
|
|
volatile cyg_uint16 pip_pbodr; /* port b open drain reg */
|
| 1077 |
|
|
volatile cyg_uint32 pip_pbdat; /* port b data reg */
|
| 1078 |
|
|
volatile cyg_uint8 RESERVED73[0x18]; /* Reserved area */
|
| 1079 |
|
|
|
| 1080 |
|
|
|
| 1081 |
|
|
/*------------------*/
|
| 1082 |
|
|
/* Serial Interface */
|
| 1083 |
|
|
/*------------------*/
|
| 1084 |
|
|
|
| 1085 |
|
|
volatile cyg_uint32 si_simode; /* SI mode register */
|
| 1086 |
|
|
volatile cyg_uint8 si_sigmr; /* SI global mode register */
|
| 1087 |
|
|
volatile cyg_uint8 RESERVED74; /* Reserved area */
|
| 1088 |
|
|
volatile cyg_uint8 si_sistr; /* SI status register */
|
| 1089 |
|
|
volatile cyg_uint8 si_sicmr; /* SI command register */
|
| 1090 |
|
|
volatile cyg_uint8 RESERVED75[0x4]; /* Reserved area */
|
| 1091 |
|
|
volatile cyg_uint32 si_sicr; /* SI clock routing */
|
| 1092 |
|
|
volatile cyg_uint32 si_sirp; /* SI ram pointers */
|
| 1093 |
|
|
volatile cyg_uint8 RESERVED76[0x10c]; /* Reserved area */
|
| 1094 |
|
|
volatile cyg_uint8 si_siram[0x200]; /* SI routing ram */
|
| 1095 |
|
|
volatile cyg_uint8 RESERVED77[0x1200]; /* Reserved area */
|
| 1096 |
|
|
|
| 1097 |
|
|
/*-----------------------------------------------------------------*/
|
| 1098 |
|
|
/* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */
|
| 1099 |
|
|
/*-----------------------------------------------------------------*/
|
| 1100 |
|
|
|
| 1101 |
|
|
union
|
| 1102 |
|
|
{
|
| 1103 |
|
|
struct qmc_chan_pram qcp[64];
|
| 1104 |
|
|
struct user_data ud;
|
| 1105 |
|
|
cyg_uint8 RESERVED[0x1c00];
|
| 1106 |
|
|
} qcp_or_ud;
|
| 1107 |
|
|
|
| 1108 |
|
|
|
| 1109 |
|
|
/*-----------------------------------------------------------------------*/
|
| 1110 |
|
|
/* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */
|
| 1111 |
|
|
/* of an identical size. See the Parameter RAM definition in the MPC860 */
|
| 1112 |
|
|
/* user's manual. */
|
| 1113 |
|
|
/*-----------------------------------------------------------------------*/
|
| 1114 |
|
|
|
| 1115 |
|
|
/*------------------------*/
|
| 1116 |
|
|
/* Base + 0x3C00 (page 1) */
|
| 1117 |
|
|
/* + 0x3D00 (page 2) */
|
| 1118 |
|
|
/* + 0x3E00 (page 3) */
|
| 1119 |
|
|
/* + 0x3F00 (page 4) */
|
| 1120 |
|
|
/*------------------------*/
|
| 1121 |
|
|
|
| 1122 |
|
|
union
|
| 1123 |
|
|
|
| 1124 |
|
|
{
|
| 1125 |
|
|
struct page_of_pram
|
| 1126 |
|
|
|
| 1127 |
|
|
{
|
| 1128 |
|
|
/*------------------------------------------------------------*/
|
| 1129 |
|
|
/* scc parameter area - 1st memory block (protocol dependent) */
|
| 1130 |
|
|
/*------------------------------------------------------------*/
|
| 1131 |
|
|
|
| 1132 |
|
|
union
|
| 1133 |
|
|
|
| 1134 |
|
|
{
|
| 1135 |
|
|
struct hdlc_pram h;
|
| 1136 |
|
|
struct uart_pram u;
|
| 1137 |
|
|
struct bisync_pram b;
|
| 1138 |
|
|
struct transparent_pram t;
|
| 1139 |
|
|
struct async_hdlc_pram a;
|
| 1140 |
|
|
cyg_uint8 RESERVED78[0x80];
|
| 1141 |
|
|
|
| 1142 |
|
|
} scc;
|
| 1143 |
|
|
|
| 1144 |
|
|
/*----------------------------------------------------------------*/
|
| 1145 |
|
|
/* Other protocol areas for the rest of the memory blocks in each */
|
| 1146 |
|
|
/* page. */
|
| 1147 |
|
|
/*----------------------------------------------------------------*/
|
| 1148 |
|
|
|
| 1149 |
|
|
union
|
| 1150 |
|
|
|
| 1151 |
|
|
{
|
| 1152 |
|
|
/*---------------------------------------------------------------*/
|
| 1153 |
|
|
/* This structure defines the rest of the blocks on the 1st page */
|
| 1154 |
|
|
/*---------------------------------------------------------------*/
|
| 1155 |
|
|
|
| 1156 |
|
|
struct
|
| 1157 |
|
|
|
| 1158 |
|
|
{
|
| 1159 |
|
|
struct i2c_pram i2c; /* I2C */
|
| 1160 |
|
|
struct misc_pram misc; /* MISC */
|
| 1161 |
|
|
struct idma_pram idma1; /* IDMA1 */
|
| 1162 |
|
|
|
| 1163 |
|
|
} i2c_idma;
|
| 1164 |
|
|
|
| 1165 |
|
|
/*---------------------------------------------------------------*/
|
| 1166 |
|
|
/* This structure defines the rest of the blocks on the 2nd page */
|
| 1167 |
|
|
/*---------------------------------------------------------------*/
|
| 1168 |
|
|
|
| 1169 |
|
|
struct
|
| 1170 |
|
|
|
| 1171 |
|
|
{
|
| 1172 |
|
|
struct spi_pram spi; /* SPI */
|
| 1173 |
|
|
struct timer_pram timer; /* Timers */
|
| 1174 |
|
|
struct idma_pram idma2; /* IDMA2 */
|
| 1175 |
|
|
|
| 1176 |
|
|
} spi_timer_idma;
|
| 1177 |
|
|
|
| 1178 |
|
|
/*---------------------------------------------------------------*/
|
| 1179 |
|
|
/* This structure defines the rest of the blocks on the 3rd page */
|
| 1180 |
|
|
/*---------------------------------------------------------------*/
|
| 1181 |
|
|
|
| 1182 |
|
|
struct
|
| 1183 |
|
|
|
| 1184 |
|
|
{
|
| 1185 |
|
|
union
|
| 1186 |
|
|
|
| 1187 |
|
|
{
|
| 1188 |
|
|
struct smc_uart_pram u1; /* SMC1 */
|
| 1189 |
|
|
struct smc_trnsp_pram t1; /* SMC1 */
|
| 1190 |
|
|
cyg_uint8 RESERVED78[0x80]; /* declare full block */
|
| 1191 |
|
|
|
| 1192 |
|
|
} psmc1;
|
| 1193 |
|
|
|
| 1194 |
|
|
} smc_dsp1;
|
| 1195 |
|
|
|
| 1196 |
|
|
|
| 1197 |
|
|
/*---------------------------------------------------------------*/
|
| 1198 |
|
|
/* This structure defines the rest of the blocks on the 4th page */
|
| 1199 |
|
|
/*---------------------------------------------------------------*/
|
| 1200 |
|
|
|
| 1201 |
|
|
struct
|
| 1202 |
|
|
|
| 1203 |
|
|
{
|
| 1204 |
|
|
union
|
| 1205 |
|
|
|
| 1206 |
|
|
{
|
| 1207 |
|
|
struct smc_uart_pram u2; /* SMC2 */
|
| 1208 |
|
|
struct smc_trnsp_pram t2; /* SMC2 */
|
| 1209 |
|
|
struct centronics_pram c; /* Uses SM2's space */
|
| 1210 |
|
|
cyg_uint8 RESERVED79[0x80]; /* declare full block */
|
| 1211 |
|
|
|
| 1212 |
|
|
} psmc2;
|
| 1213 |
|
|
|
| 1214 |
|
|
} smc_dsp2;
|
| 1215 |
|
|
|
| 1216 |
|
|
cyg_uint8 RESERVED80[0x80]; /* declare full block */
|
| 1217 |
|
|
|
| 1218 |
|
|
} other;
|
| 1219 |
|
|
|
| 1220 |
|
|
} pg;
|
| 1221 |
|
|
|
| 1222 |
|
|
/*---------------------------------------------------------------*/
|
| 1223 |
|
|
/* When selecting Ethernet as protocol for an SCC, this protocol */
|
| 1224 |
|
|
/* uses a complete page of Parameter RAM memory. */
|
| 1225 |
|
|
/*---------------------------------------------------------------*/
|
| 1226 |
|
|
|
| 1227 |
|
|
struct ethernet_pram enet_scc;
|
| 1228 |
|
|
|
| 1229 |
|
|
/*---------------------------------------------------------------*/
|
| 1230 |
|
|
/* When using QMC as a mode for an SCC, the QMC global parameter */
|
| 1231 |
|
|
/* ram uses from SCC BASE to BASE+AC. */
|
| 1232 |
|
|
/*---------------------------------------------------------------*/
|
| 1233 |
|
|
|
| 1234 |
|
|
struct global_qmc_pram gqp;
|
| 1235 |
|
|
|
| 1236 |
|
|
/*--------------------------------------------------------*/
|
| 1237 |
|
|
/* declaration to guarantee a page of memory is allocated */
|
| 1238 |
|
|
/*--------------------------------------------------------*/
|
| 1239 |
|
|
|
| 1240 |
|
|
cyg_uint8 RESERVED83[0x100];
|
| 1241 |
|
|
|
| 1242 |
|
|
} PRAM[4]; /* end of union */
|
| 1243 |
|
|
|
| 1244 |
|
|
} EPPC;
|
| 1245 |
|
|
|
| 1246 |
|
|
|
| 1247 |
|
|
/***************************************************************************/
|
| 1248 |
|
|
/* General Global Definitions */
|
| 1249 |
|
|
/***************************************************************************/
|
| 1250 |
|
|
|
| 1251 |
|
|
|
| 1252 |
|
|
#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */
|
| 1253 |
|
|
#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */
|
| 1254 |
|
|
#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */
|
| 1255 |
|
|
#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */
|
| 1256 |
|
|
|
| 1257 |
|
|
#define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */
|
| 1258 |
|
|
#define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */
|
| 1259 |
|
|
#define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */
|
| 1260 |
|
|
#define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */
|
| 1261 |
|
|
|
| 1262 |
|
|
|
| 1263 |
|
|
/*--------------------------------*/
|
| 1264 |
|
|
/* KEEP ALIVE POWER REGISTERS KEY */
|
| 1265 |
|
|
/*--------------------------------*/
|
| 1266 |
|
|
|
| 1267 |
|
|
#define KEEP_ALIVE_KEY 0x55ccaa33
|
| 1268 |
|
|
|
| 1269 |
|
|
|
| 1270 |
|
|
#define SMC2_REG 1 /* SMC Regs Array Index for SMC2 */
|
| 1271 |
|
|
|
| 1272 |
|
|
/*-------------------------*/
|
| 1273 |
|
|
/* Single buffer component */
|
| 1274 |
|
|
/*-------------------------*/
|
| 1275 |
|
|
|
| 1276 |
|
|
typedef struct BufferPool
|
| 1277 |
|
|
|
| 1278 |
|
|
{
|
| 1279 |
|
|
cyg_uint8 RxBuffer;
|
| 1280 |
|
|
cyg_uint8 TxBuffer;
|
| 1281 |
|
|
|
| 1282 |
|
|
} LB;
|
| 1283 |
|
|
|
| 1284 |
|
|
|
| 1285 |
|
|
/*--------------------------*/
|
| 1286 |
|
|
/* Buffer Descriptor Format */
|
| 1287 |
|
|
/*--------------------------*/
|
| 1288 |
|
|
|
| 1289 |
|
|
typedef struct BufferDescriptor
|
| 1290 |
|
|
|
| 1291 |
|
|
{
|
| 1292 |
|
|
cyg_uint16 bd_cstatus; /* control and status */
|
| 1293 |
|
|
cyg_uint16 bd_length; /* transfer length */
|
| 1294 |
|
|
cyg_uint8 *bd_addr; /* buffer address */
|
| 1295 |
|
|
|
| 1296 |
|
|
} BD;
|
| 1297 |
|
|
|
| 1298 |
|
|
|
| 1299 |
|
|
/*-------------------------------*/
|
| 1300 |
|
|
/* Buffer Descriptor Ring format */
|
| 1301 |
|
|
/*-------------------------------*/
|
| 1302 |
|
|
|
| 1303 |
|
|
typedef struct BufferDescRings
|
| 1304 |
|
|
|
| 1305 |
|
|
{
|
| 1306 |
|
|
volatile BD RxBD; /* Rx BD ring */
|
| 1307 |
|
|
volatile BD TxBD; /* Tx BD ring */
|
| 1308 |
|
|
|
| 1309 |
|
|
} BDRINGS;
|
| 1310 |
|
|
|
| 1311 |
|
|
|
| 1312 |
|
|
#endif /* CYGONCE_HAL_PPC_FADS_PPC_860_H */
|
