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##=============================================================================
2
##
3
##      mbx.S
4
##
5
##      MBX board hardware setup
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later version.
16
##
17
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
## for more details.
21
##
22
## You should have received a copy of the GNU General Public License along
23
## with eCos; if not, write to the Free Software Foundation, Inc.,
24
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
##
26
## As a special exception, if other files instantiate templates or use macros
27
## or inline functions from this file, or you compile this file and link it
28
## with other works to produce a work based on this file, this file does not
29
## by itself cause the resulting work to be covered by the GNU General Public
30
## License. However the source code for this file must still be made available
31
## in accordance with section (3) of the GNU General Public License.
32
##
33
## This exception does not invalidate any other reasons why a work based on
34
## this file might be covered by the GNU General Public License.
35
##
36
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
## at http://sources.redhat.com/ecos/ecos-license/
38
## -------------------------------------------
39
#####ECOSGPLCOPYRIGHTEND####
40
##=============================================================================
41
#######DESCRIPTIONBEGIN####
42
##
43
## Author(s):   hmt
44
## Contributors:hmt
45
## Date:        1999-06-08
46
## Purpose:     MBX board hardware setup
47
## Description: This file contains any code needed to initialize the
48
##              hardware on a MBX860 or 821 PowerPC board.
49
##
50
######DESCRIPTIONEND####
51
##
52
##=============================================================================
53
 
54
#include 
55
#include 
56
#include 
57
#include 
58
 
59
#include                /* register symbols et al */
60
#include                /* on-chip resource layout, special */
61
                                        /* registers, IMM layout...         */
62
#include        /* more of the same */
63
 
64
#------------------------------------------------------------------------------
65
# this is kept thus for commonality with CygMon code
66
 
67
#if 40 == CYGHWR_HAL_POWERPC_BOARD_SPEED
68
# define __40MHZ 1
69
#elif 50 == CYGHWR_HAL_POWERPC_BOARD_SPEED
70
# define __50MHZ 1
71
#else
72
# error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H
73
#endif
74
 
75
#------------------------------------------------------------------------------
76
# this is controlled with one define for tidiness:
77
# (and it is undefined by default)
78
 
79
//#define CYGPRI_RAM_START_PROGRAMS_UPMS
80
 
81
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
82
# define CYGPRI_DO_PROGRAM_UPMS
83
#endif
84
 
85
#if defined(CYGPRI_RAM_START_PROGRAMS_UPMS) && defined(CYGSEM_HAL_ROM_MONITOR)
86
/* use old tables in a StubROM build iff RAM start will reprogram them */
87
# define CYGPRI_USE_OLD_UPM_TABLES
88
#endif
89
 
90
/* The intention is that we only set up the UPMs in ROM start, be it actual
91
 * ROM application start or Stub ROMs that we built from the same sources.
92
 *
93
 * The alternative approach - in which we have reliability doubts - is to
94
 * program the UPMs with *old* timing data in StubROM start, then
95
 * *reprogram* them with *new* timing data in RAM start - and of course
96
 * program with *new* timing data in plain ROM application start.
97
 * (Re-programming from new to new timing data fails - hence the suspicion
98
 * of reprogramming _at_all_, hence this private configuration)
99
 *
100
 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
101
 * - programming the UPMs exactly once - is obtained.  Define it to get the
102
 * latter, untrusted behaviour.
103
 */
104
 
105
#------------------------------------------------------------------------------
106
 
107
// LED macro uses r3, r5: r4 left alone
108
#define LED( x ) \
109
        lwi     r5,0xfa100001;         \
110
        lwi     r3,((x) & 0xe);        \
111
        stb     r3,0(r5)
112
 
113
 
114
#------------------------------------------------------------------------------
115
 
116
FUNC_START( hal_hardware_init )
117
 
118
        # Throughout this routine, r4 is the base address of the control
119
        # registers.  r3 and r5 are scratch in general.
120
 
121
        lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
122
        mtspr   CYGARC_REG_IMMR,r4
123
 
124
        LED( 0 )                        # turn all LEDs on
125
 
126
#define CACHE_UNLOCKALL         0x0a00
127
#define CACHE_DISABLE           0x0400
128
#define CACHE_INVALIDATEALL     0x0c00
129
#define CACHE_ENABLE            0x0200
130
#define CACHE_ENABLEBIT         0x8000
131
 
132
#define CACHE_FORCEWRITETHROUGH 0x0100
133
#define CACHE_NOWRITETHROUGH    0x0300
134
#define CACHE_CLEAR_LE_SWAP     0x0700
135
 
136
        # DATA CACHE
137
        mfspr   r3,CYGARC_REG_DC_CST            /* clear error bits */
138
        lis     r3,CACHE_UNLOCKALL
139
        sync
140
        mtspr   CYGARC_REG_DC_CST,r3            /* unlock all lines */
141
 
142
        lis     r3,CACHE_INVALIDATEALL
143
        sync
144
        mtspr   CYGARC_REG_DC_CST,r3            /* invalidate all lines */
145
 
146
        lis     r3,CACHE_DISABLE
147
        sync
148
        mtspr   CYGARC_REG_DC_CST,r3            /* disable */
149
 
150
        lis     r3,CACHE_FORCEWRITETHROUGH
151
        sync
152
        mtspr   CYGARC_REG_DC_CST,r3            /* set force-writethrough mode */
153
 
154
        lis     r3,CACHE_CLEAR_LE_SWAP
155
        sync
156
        mtspr   CYGARC_REG_DC_CST,r3            /* clear little-endian swap mode */
157
        /* (dunno what this is, but it sounds like a bad thing) */
158
 
159
        # INSTRUCTION CACHE (no writeback modes)
160
        mfspr   r3,CYGARC_REG_IC_CST            /* clear error bits */
161
        lis     r3,CACHE_UNLOCKALL
162
        mtspr   CYGARC_REG_IC_CST,r3            /* unlock all lines */
163
        isync
164
        lis     r3,CACHE_INVALIDATEALL
165
        mtspr   CYGARC_REG_IC_CST,r3            /* invalidate all lines */
166
        isync
167
        lis     r3,CACHE_DISABLE
168
        mtspr   CYGARC_REG_IC_CST,r3            /* disable */
169
        isync
170
 
171
        sync
172
 
173
        /*
174
         * SIU Initialization.
175
         */
176
/*        lwi   r3,0x0062A900*/
177
/*        lwi   r3,0x006A2900*/
178
        lwi     r3,0x00602400
179
        stw     r3,SIUMCR(r4)
180
 
181
        /*
182
         * Enable bus monitor. Disable Watchdog timer.
183
         */
184
        lwi     r3,0xffffff88
185
        stw     r3,SYPCR(r4)
186
 
187
        /*
188
         * Clear REFA & REFB. Enable but freeze timebase.
189
         */
190
        lwi     r3,0x00c2
191
        sth     r3,TBSCR(r4)
192
 
193
        /*
194
         * Unlock some RTC registers (see section 5.11.2)
195
         */
196
        lwi     r3,0x55ccaa33
197
        stw     r3,RTCSCK(r4)
198
        stw     r3,RTCK(r4)
199
        stw     r3,RTSECK(r4)
200
        stw     r3,RTCALK(r4)
201
 
202
        /*
203
         * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
204
         */
205
        li      r3,0x00c3
206
        sth     r3,RTCSC(r4)
207
 
208
        /*
209
         * Clear periodic timer interrupt status.
210
         * Enable periodic timer and stop it on freeze.
211
         */
212
        li      r3,0x0083
213
        sth     r3,PISCR(r4)
214
 
215
#ifdef CYGPRI_DO_PROGRAM_UPMS
216
        /*
217
         * Perform UPM programming by writing to its 64 RAM locations.
218
         * Note that UPM initialization must be done before the Bank Register
219
         * initialization. Otherwise, system may hang when writing to Bank
220
         * Registers in certain cases.
221
         */
222
        lis     r5,__upmtbl_start@h
223
        ori     r5,r5,__upmtbl_start@l
224
        lis     r6,__upmtbl_end@h
225
        ori     r6,r6,__upmtbl_end@l
226
        sub     r7,r6,r5      /* size of table */
227
        srawi   r7,r7,2       /* in words */
228
 
229
        li      r6,0x0000     /* Command - OP=Write, UPMA, MAD=0 */
230
    1:
231
        lwz     r3,0(r5)      /* get data from table */
232
        stw     r3,MDR(r4)    /* store the data to MD register */
233
        stw     r6,MCR(r4)    /* issue command to MCR register */
234
        addi    r5,r5,4       /* next entry in the table */
235
        addi    r6,r6,1       /* next MAD address */
236
        cmpw    r6,r7         /* done yet ? */
237
        blt     1b
238
#endif // CYGPRI_DO_PROGRAM_UPMS
239
 
240
        /*
241
         * Set refresh timer prescaler to divide by 8.
242
         */
243
        li      r3,PTP_DIV32
244
        sth     r3,MPTPR(r4)
245
 
246
        /*
247
         * See Table 15-16 MPC860 User's Manual.
248
         *
249
         * PTA = 0x13 (clock dependent)
250
         * PTAE = enabled
251
         * AMA = 0
252
         * DSA = 2 cycle disable
253
         * G0CLA = A12
254
         * GPL_A4DIS = 0
255
         * RLFA = 0
256
         * WLFA = 0
257
         * TLFA = 0
258
         */
259
#ifdef __50MHZ
260
        lwi     r3,0x18801000
261
#else
262
        lwi     r3,0x13801000
263
#endif
264
        stw     r3,MAMR(r4)
265
 
266
        /*
267
         * Base Register initialization.
268
         */
269
        /* BOOT ROM */
270
        lwi     r3,0xfe000401   # 8-bit, GPCM
271
#ifdef __50MHZ
272
        lwi     r5,0xff800960 /* for 120nS devices, else 0xff800940 */
273
#else
274
        lwi     r5,0xff800930
275
#endif
276
#ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
277
        // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
278
        stw     r3,BR7(r4)
279
        stw     r5,OR7(r4)
280
#else   // Boot from 8-bit ROM - the default, on CS0
281
        stw     r3,BR0(r4)
282
        stw     r5,OR0(r4)
283
#endif
284
        /* ONBOARD DRAM */
285
        lwi     r3,0x00000081   # 32-bit, UPMA
286
        lwi     r5,0xffc00400
287
        stw     r3,BR1(r4)
288
        stw     r5,OR1(r4)
289
 
290
        /* DRAM DIMM BANK0 */
291
        lwi     r3,0x00000080   # 32-bit, UPMA, INVALID
292
        lwi     r5,0x00000400
293
        stw     r3,BR2(r4)
294
        stw     r5,OR2(r4)
295
 
296
        /* DRAM DIMM BANK1 */
297
        lwi     r3,0x00000080   # 32-bit, UPMA, INVALID
298
        lwi     r5,0x00000400
299
        stw     r3,BR3(r4)
300
        stw     r5,OR3(r4)
301
 
302
        /* NVRAM */
303
        lwi     r3,0xfa000401   # 8-bit, GPCM
304
#ifdef __50MHZ
305
        lwi     r5,0xffe00930
306
#else
307
        lwi     r5,0xffe00920
308
#endif
309
        stw     r3,BR4(r4)
310
        stw     r5,OR4(r4)
311
 
312
        /* PCI BRIDGE MEM/IO */
313
        lwi     r3,0x80000001   # 32-bit, GPCM
314
        lwi     r5,0xa0000108
315
        stw     r3,BR5(r4)
316
        stw     r5,OR5(r4)
317
 
318
        /* PCI BRIDGE REGISTERS */
319
        lwi     r3,0xfa210001   # 32-bit, GPCM
320
        lwi     r5,0xffff0108
321
        stw     r3,BR6(r4)
322
        stw     r5,OR6(r4)
323
 
324
        /* FLASH */
325
        lwi     r3,0xfc000001   # 32-bit, GPCM
326
#ifdef __50MHZ
327
        lwi     r5,0xff800940
328
#else
329
        lwi     r5,0xff800930
330
#endif
331
#ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
332
        // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
333
        stw     r3,BR0(r4)
334
        stw     r5,OR0(r4)
335
#else   // Boot from 8-bit ROM - so the 32-bit FLASH is on CS7
336
        stw     r3,BR7(r4)
337
        stw     r5,OR7(r4)
338
#endif
339
        /*
340
         *  SYSTEM CLOCK CONTROL REGISTER
341
         *
342
         *  COM   (1:2)   = 0
343
         *  TBS   (6)     = 1
344
         *  RTDIV (7)     = 0
345
         *  RTSEL (8)     = 0
346
         *  CRQEN (9)     = 0
347
         *  PRQEN (10)    = 0
348
         *  EBDF  (13:14) = 0
349
         *  DFSYNC(17:18) = 0
350
         *  DFBRG (19:20) = 0
351
         *  DFNL  (21:23) = 0
352
         *  DFNH  (24:26) = 0
353
         */
354
        lwi     r3,0x02000000
355
        stw     r3,SCCR(r4)
356
 
357
        /*
358
         *  The following sets up a 40MHz CPU clock.
359
         *  I've seen 2 variations of MBX boards. One
360
         *  uses a direct feed (1:1) 40MHz clock on
361
         *  EXTCLK inputs. The other uses a 32KHz
362
         *  oscillator on the OSCM inputs.
363
         */
364
        lwz     r3,PLPRCR(r4)
365
        rlwinm  r3,r3,12,20,31
366
        cmpwi   r3,0
367
        beq     1f
368
 
369
        /*
370
         *  PLL, LOW POWER, AND RESET CONTROL REGISTER
371
         *
372
         *  MF    (0:11)  = depends on source clock
373
         *  SPLSS (16)    = 1
374
         *  TEXPS (17)    = 1
375
         *  TMIST (19)    = 1
376
         *  CSRC  (21)    = 0
377
         *  LPM   (22:23) = 0
378
         *  CSR   (24)    = 0
379
         *  LOLRE (25)    = 0
380
         *  FIOPD (26)    = 0
381
         */
382
        /*  MF    (0:11)  = 0x4c4 = 1220 = (40MHz/32.768KHz) */
383
#ifdef __50MHZ
384
        lwi     r3,0x5f50d000
385
#else
386
        lwi     r3,0x4c40d000
387
#endif
388
        b       2f
389
    1:
390
        /*  MF    (0:11)  = 0x000 = 1 = (1:1) */
391
        lwi     r3,0x0000d000
392
    2:
393
        stw     r3,PLPRCR(r4)
394
 
395
        # mask interrupt sources in the SIU
396
        lis     r2,0
397
        lwi     r3,CYGARC_REG_IMM_SIMASK
398
        stw     r2,0(r3)
399
 
400
        # set the decrementer to maxint
401
        lwi     r2,0
402
        not     r2,r2
403
        mtdec   r2
404
 
405
        # and enable the timebase and decrementer to make sure
406
        li      r2,1                            # TBEnable and not TBFreeze
407
        lwi     r3,CYGARC_REG_IMM_TBSCR
408
        sth     r2,0(r3)
409
 
410
        LED( 8 ) # turn red led off
411
 
412
#ifdef CYG_HAL_STARTUP_ROM
413
        # move return address to where the ROM is
414
        mflr    r3
415
        andi.   r3,r3,0xffff
416
        oris    r3,r3,CYGMEM_REGION_rom>>16
417
        mtlr    r3
418
#endif
419
 
420
        blr
421
FUNC_END( hal_hardware_init )
422
 
423
 
424
#ifdef CYGPRI_DO_PROGRAM_UPMS
425
# -------------------------------------------------------------------------
426
# this table initializes the User Programmable Machine (UPM) nastiness
427
# in the QUICC to control DRAM timing.
428
 
429
__upmtbl_start:
430
 
431
#ifdef __25MHZ
432
        /* UPM contents for 25MHz clk. DRAM: EDO,4K,60ns */
433
 
434
        /* Single read. (offset 0 in upm RAM) */
435
        .long   0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
436
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
437
 
438
        /* Burst read. (offset 8 in upm RAM) */
439
        .long   0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
440
        .long   0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
441
        .long   0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
442
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
443
 
444
        /* Single write. (offset 18 in upm RAM) */
445
        .long   0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x33ff6c0f
446
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
447
 
448
        /* Burst write. (offset 20 in upm RAM) */
449
        .long   0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x03ff2c0c
450
        .long   0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
451
        .long   0x08ff2c00, 0x33ff6c0f, 0xffffec07, 0xffffec07
452
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
453
 
454
        /* Refresh (offset 30 in upm RAM) */
455
        .long   0xc0ffec04, 0x07ffec04, 0x3fffec07, 0xffffec07
456
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
457
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
458
 
459
        /* Exception. (offset 3c in upm RAM) */
460
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
461
#endif
462
 
463
#ifdef __33MHZ
464
        /* UPM contents for 33MHz clk. DRAM: EDO,4K,60ns */
465
 
466
        /* Single read. (offset 0 in upm RAM) */
467
        .long   0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
468
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
469
 
470
        /* Burst read. (offset 8 in upm RAM) */
471
        .long   0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
472
        .long   0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
473
        .long   0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
474
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
475
 
476
        /* Single write. (offset 18 in upm RAM) */
477
        .long   0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x33ff6c07
478
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
479
 
480
        /* Burst write. (offset 20 in upm RAM) */
481
        .long   0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x03ff2c0c
482
        .long   0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
483
        .long   0x08ff2c00, 0x33ff6c07, 0xffffec07, 0xffffec07
484
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
485
 
486
        /* Refresh (offset 30 in upm RAM) */
487
        .long   0xc0ffec04, 0x03ffec04, 0x1fffec07, 0xffffec07
488
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
489
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
490
 
491
        /* Exception. (offset 3c in upm RAM) */
492
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
493
#endif
494
 
495
#ifdef CYGPRI_USE_OLD_UPM_TABLES
496
 
497
        // BUT new tables received from motorola are further down
498
 
499
        // And I just discovered a good reason for using the NEW TABLES:
500
        // with the old tables, the cache zero-a-line command does not
501
        // work.  It only zeros the first 12 bytes of the line, not all 16.
502
        // This may be related to having the cache set up write-through, as
503
        // seems necessary to have it work on this platform.
504
 
505
#ifdef __40MHZ
506
        /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
507
 
508
        /* Single read. (offset 0 in upm RAM) */
509
        .long   0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
510
        .long   0x03af2c08, 0xffffec07, 0xffffec07, 0xffffec07
511
 
512
        /* Burst read. (offset 8 in upm RAM) */
513
        .long   0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
514
        .long   0x03af2c08, 0x0caf2c04, 0x00af2c04, 0x03af2c08
515
        .long   0x0caf2c04, 0x00af2c04, 0x03af2c08, 0x0caf2c04
516
        .long   0x00af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
517
 
518
        /* Single write. (offset 18 in upm RAM) */
519
        .long   0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
520
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
521
 
522
        /* Burst write. (offset 20 in upm RAM) */
523
        .long   0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
524
        .long   0x0fff2c0c, 0x0cff2c00, 0x03ff2c0c, 0x0cff2c00
525
        .long   0x03ff2c0c, 0x0cff2c00, 0x33ff6c07, 0xffffec07
526
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
527
 
528
        /* Refresh (offset 30 in upm RAM) */
529
        .long   0xf0ffec04, 0x00ffec04, 0x0fffec04, 0x0fffec04
530
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
531
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
532
 
533
        /* Exception. (offset 3c in upm RAM) */
534
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
535
#endif
536
 
537
#ifdef __50MHZ
538
        /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
539
 
540
        /* Single read. (offset 0 in upm RAM) */
541
        .long   0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
542
        .long   0x00af2c04, 0x0faf2c08, 0xffffec07, 0xffffec07
543
 
544
        /* Burst read. (offset 8 in upm RAM) */
545
        .long   0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
546
        .long   0x00af2c04, 0x0faf2c08, 0x0caf2c04, 0x00af2c04
547
        .long   0x0faf2c08, 0x0caf2c04, 0x00af2c04, 0x0faf2c08
548
        .long   0x0caf2c04, 0x00af2c04, 0x0faf2c08, 0xffffec07
549
 
550
        /* Single write. (offset 18 in upm RAM) */
551
        .long   0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
552
        .long   0x00ff2c00, 0xffffec07, 0xffffec07, 0xffffec07
553
 
554
        /* Burst write. (offset 20 in upm RAM) */
555
        .long   0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
556
        .long   0x00ff2c00, 0x0fff2c08, 0x0cff2c04, 0x00ff2c00
557
        .long   0x0fff2c00, 0x0cff2c04, 0x00ff2c00, 0x0fff2c08
558
        .long   0x0cff2c04, 0x00ff2c00, 0xffffec07, 0xffffec07
559
 
560
        /* Refresh (offset 30 in upm RAM) */
561
        .long   0xf0ffec04, 0xc0ffec04, 0x00ffec04, 0x0fffec04
562
        .long   0x1fffec07, 0xffffec07, 0xffffec07, 0xffffec07
563
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
564
 
565
        /* Exception. (offset 3c in upm RAM) */
566
        .long   0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
567
#endif
568
 
569
#else // !CYGPRI_USE_OLD_UPM_TABLES: use the NEW TABLES
570
 
571
        // for RAM startup or ROM application when NOT making a stub rom,
572
        // ie. CYGSEM_HAL_ROM_MONITOR not defined.
573
 
574
#ifdef __40MHZ
575
        /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
576
        .long   0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x30af0c00
577
        .long   0xf1bf4805, 0xffffc005, 0xffffc005, 0xffffc005
578
 
579
        .long   0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x03af0c08
580
        .long   0x0caf0c04, 0x03af0c08, 0x0caf0c04, 0x03af0c08
581
        .long   0x0caf0c04, 0x30af0c00, 0xf3bf4805, 0xffffc005
582
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
583
 
584
        .long   0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x33ff4804
585
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
586
 
587
        .long   0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
588
        .long   0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
589
        .long   0x0cff0c00, 0x33ff4804, 0xffffc005, 0xffffc005
590
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
591
 
592
        .long   0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
593
        .long   0x3fffc004, 0xffffc005, 0xffffc005, 0xffffc005
594
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
595
 
596
        .long   0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
597
#endif
598
 
599
#ifdef __50MHZ
600
        /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
601
 
602
        .long   0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x10af0c04
603
        .long   0xf0af0c00, 0xf3bf4805, 0xffffc005, 0xffffc005
604
 
605
        .long   0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x00af0c04
606
        .long   0x07af0c08, 0x0caf0c04, 0x01af0c04, 0x0faf0c08
607
        .long   0x0caf0c04, 0x01af0c04, 0x0faf0c08, 0x0caf0c04
608
        .long   0x10af0c04, 0xf0afc000, 0xf3bf4805, 0xffffc005
609
 
610
        .long   0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x13ff4804
611
        .long   0xffffc004, 0xffffc005, 0xffffc005, 0xffffc005
612
 
613
        .long   0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
614
        .long   0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
615
        .long   0x0cff0c00, 0x13ff4804, 0xffffc004, 0xffffc005
616
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
617
 
618
        .long   0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
619
        .long   0x1fffc004, 0xffffc004, 0xffffc005, 0xffffc005
620
        .long   0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
621
 
622
        .long   0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
623
#endif
624
#endif  // OLD/NEW TABLES == CYGPRI_USE_OLD_UPM_TABLES or not.
625
        // depending on CYGSEM_HAL_ROM_MONITOR and whether RAM
626
        // start re-initializes.
627
 
628
__upmtbl_end:
629
#endif // CYGPRI_DO_PROGRAM_UPMS
630
 
631
FUNC_START(hal_mbx_set_led)
632
        andi.   r3,r3,0x0e
633
        lwi     r4,0xfa100001
634
        stb     r3,0(r4)
635
        blr
636
FUNC_END(hal_mbx_set_led)
637
 
638
FUNC_START(hal_mbx_flash_led)
639
        lwi     r4,0xfa100001
640
    1:
641
        li      r5,10
642
        stb     r5,0(r4)
643
 
644
        lis     r5,10
645
        mtctr   r5
646
    2:
647
        bdnz    2b
648
 
649
        li      r5,12
650
        stb     r5,0(r4)
651
 
652
        lis     r5,10
653
        mtctr   r5
654
    3:
655
        bdnz    3b
656
 
657
        subi    r3,r3,1
658
        cmpwi   r3,0
659
        bge     1b
660
 
661
        li      r5,6
662
        stb     r5,0(r4)
663
 
664
        lis     r5,20
665
        mtctr   r5
666
    4:
667
        bdnz    4b
668
 
669
        blr
670
FUNC_END(hal_mbx_flash_led)
671
 
672
 
673
#------------------------------------------------------------------------------
674
# end of mbx.S

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