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#ifndef CYGONCE_VAR_CACHE_H
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#define CYGONCE_VAR_CACHE_H
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//=============================================================================
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//
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// var_cache.h
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//
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// Variant HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): pfine
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// Contributors:nickg, jskov
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// Date: 2001-12-12
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// Purpose: Variant cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations on the MPC8260 variant CPU.
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// Usage: Is included via the architecture cache header:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/ppc_regs.h>
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#include <cyg/hal/var_regs.h>
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#include <cyg/hal/plf_cache.h>
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//-----------------------------------------------------------------------------
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// Cache dimensions
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// Data cache
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#define HAL_DCACHE_SIZE 16384 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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#define HAL_DCACHE_WAYS 4 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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#define HAL_ICACHE_WAYS 4 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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cyg_uint32 tmp1, tmp2; \
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asm volatile ( \
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"mfspr %1, %2;" \
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"li %0, 0x4000;" \
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"rlwimi %1,%0,0,17,17;" \
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"sync;" \
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"mtspr %2,%1;" \
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"isync;" \
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"sync;" \
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: "=r" (tmp1), "=r" (tmp2) \
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: "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
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CYG_MACRO_END
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// Disable the data cache
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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register cyg_uint32 tmp1; \
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register cyg_uint32 tmp2; \
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for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \
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tmp2 = *((cyg_uint32 *) tmp1); \
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asm volatile ( \
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"mfspr %1, %2;" \
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"li %0, 0x0;" \
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"rlwimi %1,%0,0,17,17;" \
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"sync;" \
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"mtspr %2,%1;" \
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"isync;" \
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"sync;" \
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: "=r" (tmp1), "=r" (tmp2) \
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: "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_DCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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cyg_uint32 tmp1, tmp2; \
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asm volatile ("sync;" \
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"mfspr %0, %2;" \
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"ori %0, %0, 0x0400;" \
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"mtspr %2, %0;" \
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"li %1, 0;" \
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"rlwimi %0,%1,0,21,21;" \
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"mtspr %2, %0;" \
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"sync;" \
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: "=r" (tmp1), "=r" (tmp2) \
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: "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// Use a brute force method until something better appears in my head
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// By loading memory from 0x0 to HAL_DCACHE_SIZE, incremented by
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// HAL_DCACHE_LINE_SIZE, it will ensure that the contents of the data
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// cache is known. Then, I will traverse the loop again, this time
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// flushing the address, not loading it.
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#if 1
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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volatile cyg_uint32 tmp1,tmp2; \
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for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \
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tmp2 = *((cyg_uint32 *) tmp1); \
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HAL_DCACHE_FLUSH(0x0, HAL_DCACHE_SIZE); \
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CYG_MACRO_END
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#else
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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cyg_uint32 __base = 0x0, _tmp; \
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cyg_int32 __size = HAL_DCACHE_SIZE; \
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while (__size > 0) { \
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asm volatile ( \
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"lwz %0,0(%1);" \
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:"=r" (_tmp) : "r" (__base) \
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); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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HAL_DCACHE_FLUSH( 0x0 , HAL_DCACHE_SIZE ); \
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CYG_MACRO_END
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#endif
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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asm volatile ("mfspr %0, %1;" \
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"rlwinm %0,%0,18,31,31;" \
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: "=r" (_state_) : "I" (CYGARC_REG_HID0))
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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//#define HAL_DCACHE_WRITETHRU_MODE 0
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//#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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#define HAL_DCACHE_UNLOCK_ALL() \
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asm volatile ("isync;" \
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"mfspr %0, %2;" \
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"oris %1, 0,0xFFFF;" \
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"ori %1,%1,0xEFFF;" \
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"and %0,%0,%1;" \
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"mtspr %2,%0;" \
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"isync;" \
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"sync;" \
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: /* No output */ \
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: "I" (5) /* %0 ==> r5 */, \
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"I" (6) /* %1 ==> r6 */, \
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"I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Invalidate cache lines in the given range without writing to memory.
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// NOTE: The errata for the 603e processor indicates use of the dcbf
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// command as the dcbi command will only invalidate modified blocks.
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#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Write dirty cache lines to memory for the given address range.
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#define HAL_DCACHE_STORE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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| 262 |
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// Allocate and zero the cache lines associated with the given range.
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| 263 |
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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| 265 |
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//-----------------------------------------------------------------------------
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| 266 |
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// Global control of Instruction cache
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| 267 |
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| 268 |
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// Enable the instruction cache
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| 269 |
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#define HAL_ICACHE_ENABLE() \
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| 270 |
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CYG_MACRO_START \
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| 271 |
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cyg_uint32 tmp1, tmp2; \
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| 272 |
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asm volatile ( \
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| 273 |
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"mfspr %1, %2;" \
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"li %0, 0x4000;" \
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| 275 |
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"rlwimi %1,%0,1,16,16;" \
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| 276 |
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"sync;" \
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| 277 |
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"isync;" \
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| 278 |
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"mtspr %2,%1;" \
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| 279 |
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"isync;" \
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| 280 |
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"sync;" \
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| 281 |
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: "=r" (tmp1), "=r" (tmp2) \
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| 282 |
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: "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
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| 283 |
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CYG_MACRO_END
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// Disable the instruction cache
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| 286 |
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#define HAL_ICACHE_DISABLE() \
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| 287 |
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CYG_MACRO_START \
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| 288 |
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cyg_uint32 tmp1, tmp2; \
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| 289 |
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asm volatile ( \
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| 290 |
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"mfspr %1, %2;" \
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| 291 |
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"li %0, 0x0;" \
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| 292 |
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"rlwimi %1,%0,0,16,16;" \
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| 293 |
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"sync;" \
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| 294 |
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"isync;" \
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| 295 |
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"mtspr %2,%1;" \
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| 296 |
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"isync;" \
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| 297 |
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"sync;" \
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| 298 |
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: "=r" (tmp1), "=r" (tmp2) \
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| 299 |
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: "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
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| 300 |
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CYG_MACRO_END
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| 301 |
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| 302 |
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// Invalidate the entire cache
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| 303 |
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#if 1
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| 304 |
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#define HAL_ICACHE_INVALIDATE_ALL() \
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| 305 |
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CYG_MACRO_START \
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| 306 |
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cyg_uint32 tmp1, tmp2; \
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| 307 |
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asm volatile ("sync;" \
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| 308 |
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"mfspr %0, %2;" \
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| 309 |
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"ori %1, %0, 0x8000;" \
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| 310 |
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"isync;" \
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| 311 |
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"mtspr %2, %1;" \
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| 312 |
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"ori %1, %0, 0x0800;" \
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| 313 |
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"mtspr %2, %1;" \
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| 314 |
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"mtspr %2, %0;" \
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| 315 |
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"isync;" \
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| 316 |
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"sync;" \
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| 317 |
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: "=r" (tmp1), "=r" (tmp2) \
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| 318 |
|
|
: "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
|
| 319 |
|
|
CYG_MACRO_END
|
| 320 |
|
|
#else
|
| 321 |
|
|
#define HAL_ICACHE_INVALIDATE_ALL() \
|
| 322 |
|
|
CYG_MACRO_START \
|
| 323 |
|
|
cyg_uint32 tmp1, tmp2; \
|
| 324 |
|
|
asm volatile ("sync;" \
|
| 325 |
|
|
"mfspr %0, %2;" \
|
| 326 |
|
|
"ori %0, %0, 0x0800;" \
|
| 327 |
|
|
"isync;" \
|
| 328 |
|
|
"mtspr %2, %0;" \
|
| 329 |
|
|
"li %1, 0;" \
|
| 330 |
|
|
"rlwimi %0,%1,0,20,20;" \
|
| 331 |
|
|
"isync;" \
|
| 332 |
|
|
"mtspr %2, %0;" \
|
| 333 |
|
|
"isync;" \
|
| 334 |
|
|
"sync;" \
|
| 335 |
|
|
: "=r" (tmp1), "=r" (tmp2) \
|
| 336 |
|
|
: "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
|
| 337 |
|
|
CYG_MACRO_END
|
| 338 |
|
|
#endif
|
| 339 |
|
|
// Synchronize the contents of the cache with memory.
|
| 340 |
|
|
#define HAL_ICACHE_SYNC() \
|
| 341 |
|
|
HAL_ICACHE_INVALIDATE_ALL()
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
// Query the state of the instruction cache
|
| 345 |
|
|
#define HAL_ICACHE_IS_ENABLED(_state_) \
|
| 346 |
|
|
asm volatile ("mfspr %0, %1;" \
|
| 347 |
|
|
"rlwinm %0,%0,17,31,31;" \
|
| 348 |
|
|
: "=r" (_state_) : "I" (CYGARC_REG_HID0))
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
// Set the instruction cache refill burst size
|
| 352 |
|
|
//#define HAL_ICACHE_BURST_SIZE(_size_)
|
| 353 |
|
|
|
| 354 |
|
|
// Load the contents of the given address range into the instruction cache
|
| 355 |
|
|
// and then lock the cache so that it stays there.
|
| 356 |
|
|
//#define HAL_ICACHE_LOCK(_base_, _size_)
|
| 357 |
|
|
|
| 358 |
|
|
// Undo a previous lock operation
|
| 359 |
|
|
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
|
| 360 |
|
|
|
| 361 |
|
|
// Unlock entire cache
|
| 362 |
|
|
#define HAL_ICACHE_UNLOCK_ALL() \
|
| 363 |
|
|
asm volatile ("isync;" \
|
| 364 |
|
|
"mfspr %0, %2;" \
|
| 365 |
|
|
"oris %1, 0,0xFFFF;" \
|
| 366 |
|
|
"ori %1,%1,0xDFFF;" \
|
| 367 |
|
|
"and %0,%0,%1;" \
|
| 368 |
|
|
"isync;" \
|
| 369 |
|
|
"mtspr %2,%0;" \
|
| 370 |
|
|
"isync;" \
|
| 371 |
|
|
"sync;" \
|
| 372 |
|
|
: /* No output */ \
|
| 373 |
|
|
: "I" (5) /* %0 ==> r5 */, \
|
| 374 |
|
|
"I" (6) /* %1 ==> r6 */, \
|
| 375 |
|
|
"I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
|
| 376 |
|
|
|
| 377 |
|
|
//-----------------------------------------------------------------------------
|
| 378 |
|
|
// Instruction cache line control
|
| 379 |
|
|
|
| 380 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 381 |
|
|
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
|
| 382 |
|
|
|
| 383 |
|
|
//-----------------------------------------------------------------------------
|
| 384 |
|
|
#endif // ifndef CYGONCE_VAR_CACHE_H
|
| 385 |
|
|
// End of var_cache.h
|
