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#ifndef CYGONCE_VAR_CACHE_H
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#define CYGONCE_VAR_CACHE_H
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//=============================================================================
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//
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// var_cache.h
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//
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// Variant HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors:nickg, jskov
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// Date: 2000-04-02
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// Purpose: Variant cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations on the MPC8xx variant CPUs.
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// Usage: Is included via the architecture cache header:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/ppc_regs.h>
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#include <cyg/hal/plf_cache.h>
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//-----------------------------------------------------------------------------
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// Cache dimensions - these vary between the 8xx sub-models
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#if defined(CYGPKG_HAL_POWERPC_MPC860)
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// Data cache
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#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 2 // Associativity of the cache
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#endif // defined(CYGPKG_HAL_POWERPC_MPC860)
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#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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// Data cache
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#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 2 // Associativity of the cache
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#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
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// Disable the data cache
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#define HAL_DCACHE_DISABLE() \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
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// Invalidate the entire cache
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// Note: Any locked lines will not be invalidated.
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#define HAL_DCACHE_INVALIDATE_ALL() \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), \
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"r" (CYGARC_REG_DC_CMD_IA))
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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cyg_int32 i; \
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for (i = 0; i < HAL_DCACHE_SETS; i++){ \
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asm volatile ("sync;" \
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"mtspr %0, %2;" \
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"mtspr %1, %4;" \
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"mtspr %0, %3;" \
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"mtspr %1, %4;" \
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: /* no output */ \
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: /* %0 */ "I" (CYGARC_REG_DC_ADR), \
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/* %1 */ "I" (CYGARC_REG_DC_CST), \
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/* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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|(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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/* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \
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|(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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/* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \
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} \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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asm volatile ("mfspr %0, %1;" \
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"rlwinm %0,%0,1,31,31;" \
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: "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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#define HAL_DCACHE_WRITE_MODE( _mode_ ) \
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CYG_MACRO_START \
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if (_mode_ == HAL_DCACHE_WRITETHRU_MODE) { \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), \
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"r" (CYGARC_REG_DC_CMD_SW)); \
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} \
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if (_mode_ == HAL_DCACHE_WRITEBACK_MODE) { \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), \
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"r" (CYGARC_REG_DC_CMD_CW)); \
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} \
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CYG_MACRO_END
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#define HAL_DCACHE_WRITETHRU_MODE 0
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#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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// Restrictions: This implementation only allows a single area to be
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// locked at any one time. This area must be 2kB or less in size.
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// Implementation: Flush entire cache, then invalidate it. This
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// ensures that the fetched data go into way0.
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#define HAL_DCACHE_LOCK(_base_, _size_) \
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CYG_MACRO_START \
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cyg_int32 __scratch; \
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cyg_uint32 __base = (cyg_uint32)(_base_); \
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cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \
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cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \
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HAL_DCACHE_DISABLE(); \
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HAL_DCACHE_SYNC (); \
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HAL_DCACHE_INVALIDATE_ALL (); \
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HAL_DCACHE_ENABLE(); \
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do { \
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asm volatile ("lbz %0,0(%1);" \
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"sync;" \
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"mtspr %2, %4;" \
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"mtspr %3, %5;" \
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: /* %0 */ "=&r" (__scratch) \
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: /* %1 */ "b" (__base), \
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/* %2 */ "I" (CYGARC_REG_DC_ADR), \
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/* %3 */ "I" (CYGARC_REG_DC_CST), \
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/* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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|(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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/* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \
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__l++; \
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__base += HAL_DCACHE_LINE_SIZE; \
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} while (__count--); \
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CYG_MACRO_END
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// Undo a previous lock operation
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// Implementation: Unlocks entire cache.
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#define HAL_DCACHE_UNLOCK(_base_, _size_) \
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HAL_DCACHE_UNLOCK_ALL()
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// Unlock entire cache
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#define HAL_DCACHE_UNLOCK_ALL() \
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CYG_MACRO_START \
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asm volatile ("sync;" \
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"mtspr %0, %1;" \
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: : "I" (CYGARC_REG_DC_CST), \
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"r" (CYGARC_REG_DC_CMD_UA)); \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Invalidate cache lines in the given range without writing to memory.
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#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Write dirty cache lines to memory for the given address range.
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#define HAL_DCACHE_STORE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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while (__size > 0) { \
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asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Preread the given range into the cache with the intention of reading
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// from it later.
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#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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CYG_MACRO_START \
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| 275 |
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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cyg_int32 __size = (cyg_int32) (_size_); \
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| 277 |
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while (__size > 0) { \
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asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Preread the given range into the cache with the intention of writing
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// to it later.
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#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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| 287 |
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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| 289 |
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cyg_int32 __size = (cyg_int32) (_size_); \
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| 290 |
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while (__size > 0) { \
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asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Allocate and zero the cache lines associated with the given range.
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| 298 |
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#define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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| 299 |
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CYG_MACRO_START \
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cyg_uint32 __base = (cyg_uint32) (_base_); \
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| 301 |
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cyg_int32 __size = (cyg_int32) (_size_); \
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| 302 |
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while (__size > 0) { \
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asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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__base += HAL_DCACHE_LINE_SIZE; \
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__size -= HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
|
| 311 |
|
|
|
| 312 |
|
|
// Enable the instruction cache
|
| 313 |
|
|
#define HAL_ICACHE_ENABLE() \
|
| 314 |
|
|
asm volatile ("isync;" \
|
| 315 |
|
|
"mtspr %0, %1;" \
|
| 316 |
|
|
"isync" \
|
| 317 |
|
|
: : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
|
| 318 |
|
|
|
| 319 |
|
|
// Disable the instruction cache
|
| 320 |
|
|
#define HAL_ICACHE_DISABLE() \
|
| 321 |
|
|
asm volatile ("isync;" \
|
| 322 |
|
|
"mtspr %0, %1;" \
|
| 323 |
|
|
"isync" \
|
| 324 |
|
|
: : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
|
| 325 |
|
|
|
| 326 |
|
|
// Invalidate the entire cache
|
| 327 |
|
|
#define HAL_ICACHE_INVALIDATE_ALL() \
|
| 328 |
|
|
asm volatile ("isync;" \
|
| 329 |
|
|
"mtspr %0, %1;" \
|
| 330 |
|
|
"isync" \
|
| 331 |
|
|
: : "I" (CYGARC_REG_IC_CST), \
|
| 332 |
|
|
"r" (CYGARC_REG_IC_CMD_IA))
|
| 333 |
|
|
|
| 334 |
|
|
// Synchronize the contents of the cache with memory.
|
| 335 |
|
|
#define HAL_ICACHE_SYNC() \
|
| 336 |
|
|
HAL_ICACHE_INVALIDATE_ALL()
|
| 337 |
|
|
|
| 338 |
|
|
// Query the state of the instruction cache
|
| 339 |
|
|
#define HAL_ICACHE_IS_ENABLED(_state_) \
|
| 340 |
|
|
asm volatile ("mfspr %0, %1;" \
|
| 341 |
|
|
"rlwinm %0,%0,1,31,31;" \
|
| 342 |
|
|
: "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
|
| 343 |
|
|
|
| 344 |
|
|
// Set the instruction cache refill burst size
|
| 345 |
|
|
//#define HAL_ICACHE_BURST_SIZE(_size_)
|
| 346 |
|
|
|
| 347 |
|
|
|
| 348 |
|
|
// Load the contents of the given address range into the instruction cache
|
| 349 |
|
|
// and then lock the cache so that it stays there.
|
| 350 |
|
|
|
| 351 |
|
|
// Restrictions: This implementation only allows a single area to be
|
| 352 |
|
|
// locked at any one time. This area must be 2kB or less in size.
|
| 353 |
|
|
|
| 354 |
|
|
// Implementation: Flush entire cache, then invalidate it. This
|
| 355 |
|
|
// ensures that the fetched data go into way0.
|
| 356 |
|
|
|
| 357 |
|
|
#define HAL_ICACHE_LOCK(_base_, _size_) \
|
| 358 |
|
|
CYG_MACRO_START \
|
| 359 |
|
|
unsigned long __base = \
|
| 360 |
|
|
((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \
|
| 361 |
|
|
int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \
|
| 362 |
|
|
do { \
|
| 363 |
|
|
asm volatile ("mtspr %0, %2;" \
|
| 364 |
|
|
"mtspr %1, %3;" \
|
| 365 |
|
|
"isync;" \
|
| 366 |
|
|
: /* no output */ \
|
| 367 |
|
|
: /* %0 */ "I" (CYGARC_REG_IC_ADR), \
|
| 368 |
|
|
/* %1 */ "I" (CYGARC_REG_IC_CST), \
|
| 369 |
|
|
/* %2 */ "r" (__base), \
|
| 370 |
|
|
/* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \
|
| 371 |
|
|
__base += HAL_ICACHE_LINE_SIZE; \
|
| 372 |
|
|
} while (__count--); \
|
| 373 |
|
|
CYG_MACRO_END
|
| 374 |
|
|
|
| 375 |
|
|
// Undo a previous lock operation
|
| 376 |
|
|
|
| 377 |
|
|
// Implementation: Unlocks entire cache.
|
| 378 |
|
|
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
|
| 379 |
|
|
HAL_ICACHE_UNLOCK_ALL()
|
| 380 |
|
|
|
| 381 |
|
|
// Unlock entire cache
|
| 382 |
|
|
#define HAL_ICACHE_UNLOCK_ALL() \
|
| 383 |
|
|
CYG_MACRO_START \
|
| 384 |
|
|
asm volatile ("sync;" \
|
| 385 |
|
|
"mtspr %0, %1;" \
|
| 386 |
|
|
: : "I" (CYGARC_REG_IC_CST), \
|
| 387 |
|
|
"r" (CYGARC_REG_IC_CMD_UA)); \
|
| 388 |
|
|
CYG_MACRO_END
|
| 389 |
|
|
|
| 390 |
|
|
//-----------------------------------------------------------------------------
|
| 391 |
|
|
// Instruction cache line control
|
| 392 |
|
|
|
| 393 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 394 |
|
|
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
|
| 395 |
|
|
|
| 396 |
|
|
//-----------------------------------------------------------------------------
|
| 397 |
|
|
#endif // ifndef CYGONCE_VAR_CACHE_H
|
| 398 |
|
|
// End of var_cache.h
|
