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//==========================================================================
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//
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// var_intr.c
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//
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// PowerPC variant interrupt handlers
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov, gthomas
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// Date: 2000-02-11
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// Purpose: PowerPC variant interrupt handlers
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// Description: This file contains code to handle interrupt related issues
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// on the PowerPC variant.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#include <cyg/hal/ppc_regs.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/infra/cyg_type.h>
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extern void hal_platform_IRQ_init(void);
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static cyg_uint32 exier_mask[] = {
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0x00000000, // Unused
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0x00000000, // Unused
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0x80000000, // CYGNUM_HAL_INTERRUPT_CRITICAL 2
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0x08000000, // CYGNUM_HAL_INTERRUPT_SERIAL_RCV 3
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0x04000000, // CYGNUM_HAL_INTERRUPT_SERIAL_XMT 4
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0x02000000, // CYGNUM_HAL_INTERRUPT_JTAG_RCV 5
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0x01000000, // CYGNUM_HAL_INTERRUPT_JTAG_XMT 6
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0x00800000, // CYGNUM_HAL_INTERRUPT_DMA0 7
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0x00400000, // CYGNUM_HAL_INTERRUPT_DMA1 8
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0x00200000, // CYGNUM_HAL_INTERRUPT_DMA2 9
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0x00100000, // CYGNUM_HAL_INTERRUPT_DMA3 10
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0x00000010, // CYGNUM_HAL_INTERRUPT_EXT0 11
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0x00000008, // CYGNUM_HAL_INTERRUPT_EXT1 12
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0x00000004, // CYGNUM_HAL_INTERRUPT_EXT2 13
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0x00000002, // CYGNUM_HAL_INTERRUPT_EXT3 14
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0x00000001, // CYGNUM_HAL_INTERRUPT_EXT4 15
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};
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// This table inverts bit number to signal number
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cyg_uint32 EXISR_TAB[] = {
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CYGNUM_HAL_INTERRUPT_CRITICAL, // 0x80000000
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0x00000000, // 0x40000000
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0x00000000, // 0x20000000
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0x00000000, // 0x10000000
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CYGNUM_HAL_INTERRUPT_SERIAL_RCV, // 0x08000000
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CYGNUM_HAL_INTERRUPT_SERIAL_XMT, // 0x04000000
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CYGNUM_HAL_INTERRUPT_JTAG_RCV, // 0x02000000
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CYGNUM_HAL_INTERRUPT_JTAG_XMT, // 0x01000000
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CYGNUM_HAL_INTERRUPT_DMA0, // 0x00800000
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CYGNUM_HAL_INTERRUPT_DMA1, // 0x00400000
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CYGNUM_HAL_INTERRUPT_DMA2, // 0x00200000
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CYGNUM_HAL_INTERRUPT_DMA3, // 0x00100000
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0x00000000, // 0x00080000
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0x00000000, // 0x00040000
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0x00000000, // 0x00020000
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0x00000000, // 0x00010000
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0x00000000, // 0x00008000
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0x00000000, // 0x00004000
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0x00000000, // 0x00002000
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0x00000000, // 0x00001000
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0x00000000, // 0x00000800
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0x00000000, // 0x00000400
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0x00000000, // 0x00000200
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0x00000000, // 0x00000100
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0x00000000, // 0x00000080
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0x00000000, // 0x00000040
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0x00000000, // 0x00000020
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CYGNUM_HAL_INTERRUPT_EXT0, // 0x00000010
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CYGNUM_HAL_INTERRUPT_EXT1, // 0x00000008
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CYGNUM_HAL_INTERRUPT_EXT2, // 0x00000004
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CYGNUM_HAL_INTERRUPT_EXT3, // 0x00000002
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CYGNUM_HAL_INTERRUPT_EXT4 // 0x00000001
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};
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cyg_uint32 _hold_tcr = 0; // Shadow of hardware register
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externC void
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hal_variant_IRQ_init(void)
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{
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cyg_uint32 iocr;
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// Ensure all interrupts masked (disabled) & cleared
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CYGARC_MTDCR(DCR_EXIER, 0);
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CYGARC_MTDCR(DCR_EXISR, 0xFFFFFFFF);
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// Configure all external interrupts to be level/low
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CYGARC_MFDCR(DCR_IOCR, iocr);
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iocr &= ~0xFFC00000;
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CYGARC_MTDCR(DCR_IOCR, iocr);
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// Disable timers
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CYGARC_MTSPR(SPR_TCR, 0);
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// Let the platform do any overrides
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hal_platform_IRQ_init();
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}
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externC void
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hal_ppc40x_interrupt_mask(int vector)
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{
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cyg_uint32 exier, tcr;
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_CRITICAL:
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case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
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case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
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case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
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case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
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case CYGNUM_HAL_INTERRUPT_DMA0:
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case CYGNUM_HAL_INTERRUPT_DMA1:
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case CYGNUM_HAL_INTERRUPT_DMA2:
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case CYGNUM_HAL_INTERRUPT_DMA3:
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case CYGNUM_HAL_INTERRUPT_EXT0:
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case CYGNUM_HAL_INTERRUPT_EXT1:
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case CYGNUM_HAL_INTERRUPT_EXT2:
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case CYGNUM_HAL_INTERRUPT_EXT3:
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case CYGNUM_HAL_INTERRUPT_EXT4:
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CYGARC_MFDCR(DCR_EXIER, exier);
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exier &= ~exier_mask[vector];
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CYGARC_MTDCR(DCR_EXIER, exier);
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break;
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case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr &= ~TCR_PIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr &= ~TCR_FIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr &= ~TCR_WIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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default:
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}
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}
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externC void
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hal_ppc40x_interrupt_unmask(int vector)
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{
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cyg_uint32 exier, tcr;
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_CRITICAL:
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case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
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case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
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case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
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case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
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case CYGNUM_HAL_INTERRUPT_DMA0:
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case CYGNUM_HAL_INTERRUPT_DMA1:
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case CYGNUM_HAL_INTERRUPT_DMA2:
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case CYGNUM_HAL_INTERRUPT_DMA3:
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case CYGNUM_HAL_INTERRUPT_EXT0:
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case CYGNUM_HAL_INTERRUPT_EXT1:
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case CYGNUM_HAL_INTERRUPT_EXT2:
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case CYGNUM_HAL_INTERRUPT_EXT3:
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case CYGNUM_HAL_INTERRUPT_EXT4:
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CYGARC_MFDCR(DCR_EXIER, exier);
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exier |= exier_mask[vector];
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CYGARC_MTDCR(DCR_EXIER, exier);
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break;
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case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr |= TCR_PIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr |= TCR_FIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
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CYGARC_MFSPR(SPR_TCR, tcr);
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tcr = _hold_tcr;
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tcr |= TCR_WIE;
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CYGARC_MTSPR(SPR_TCR, tcr);
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_hold_tcr = tcr;
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break;
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default:
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}
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}
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externC void
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hal_ppc40x_interrupt_acknowledge(int vector)
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{
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_EXT0:
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case CYGNUM_HAL_INTERRUPT_EXT1:
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case CYGNUM_HAL_INTERRUPT_EXT2:
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case CYGNUM_HAL_INTERRUPT_EXT3:
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case CYGNUM_HAL_INTERRUPT_EXT4:
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CYGARC_MTDCR(DCR_EXISR, exier_mask[vector]);
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break;
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case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
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CYGARC_MTSPR(SPR_TSR, TSR_PIS); // clear & acknowledge interrupt
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break;
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case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
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CYGARC_MTSPR(SPR_TSR, TSR_FIS); // clear & acknowledge interrupt
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break;
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case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
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CYGARC_MTSPR(SPR_TSR, TSR_WIS); // clear & acknowledge interrupt
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break;
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case CYGNUM_HAL_INTERRUPT_CRITICAL:
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case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
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case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
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case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
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case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
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case CYGNUM_HAL_INTERRUPT_DMA0:
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case CYGNUM_HAL_INTERRUPT_DMA1:
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case CYGNUM_HAL_INTERRUPT_DMA2:
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case CYGNUM_HAL_INTERRUPT_DMA3:
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| 268 |
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default:
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}
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| 270 |
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}
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| 271 |
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| 272 |
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// Note: These functions are only [well] defined for "external" interrupts
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// which can be controlled via the EXIER register.
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externC void
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| 275 |
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hal_ppc40x_interrupt_configure(int vector, int level, int dir)
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| 276 |
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{
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| 277 |
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cyg_uint32 mask, new_state, iocr;
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| 278 |
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| 279 |
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if ((vector >= CYGNUM_HAL_INTERRUPT_EXT0) &&
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| 280 |
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(vector <= CYGNUM_HAL_INTERRUPT_EXT4)) {
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| 281 |
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mask = 0x03 << (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
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| 282 |
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new_state = (dir & 0x01); // Up/Down
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| 283 |
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if (level == 0) {
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| 284 |
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// Edge triggered
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| 285 |
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new_state = 0x02;
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| 286 |
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}
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| 287 |
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new_state <<= (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
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| 288 |
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CYGARC_MFDCR(DCR_IOCR, iocr);
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| 289 |
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iocr = (iocr & ~mask) | new_state;
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| 290 |
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CYGARC_MTDCR(DCR_IOCR, iocr);
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| 291 |
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}
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| 292 |
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}
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| 293 |
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| 294 |
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externC void
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| 295 |
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hal_ppc40x_interrupt_set_level(int vector, int level)
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| 296 |
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{
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| 297 |
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}
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| 298 |
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| 299 |
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// -------------------------------------------------------------------------
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// EOF var_intr.c
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