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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [ppc40x/] [v2_0/] [src/] [var_misc.c] - Blame information for rev 174

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//==========================================================================
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//
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//      var_misc.c
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//
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//      HAL implementation miscellaneous functions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    jskov
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// Contributors: jskov, gthomas
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// Date:         2000-02-04
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// Purpose:      HAL miscellaneous functions
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// Description:  This file contains miscellaneous functions provided by the
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//               HAL.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#include <cyg/hal/ppc_regs.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_mem.h>
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void hal_ppc40x_clock_initialize(cyg_uint32 period);
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//--------------------------------------------------------------------------
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void hal_variant_init(void)
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{
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    // Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
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    hal_ppc40x_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
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}
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//--------------------------------------------------------------------------
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// Variant specific idle thread action.
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bool
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hal_variant_idle_thread_action( cyg_uint32 count )
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{
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    // Let architecture idle thread action run
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    return true;
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}
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//---------------------------------------------------------------------------
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// Use MMU resources to map memory regions.  
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// Takes and returns an int used to ID the MMU resource to use. This ID
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// is increased as resources are used and should be used for subsequent
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// invocations.
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//
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// The PPC4xx CPUs do not have BATs. Fortunately we don't currently
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// use the MMU, so we can simulate BATs by using the TLBs.
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int
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cyg_hal_map_memory (int id, CYG_ADDRESS virt, CYG_ADDRESS phys,
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                    cyg_int32 size, cyg_uint8 flags)
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{
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    cyg_uint32 epn, rpn;
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    int sv, lv, max_tlbs;
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    // There are 64 TLBs.
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    max_tlbs = 64;
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    // Use the smallest "size" value which is big enough (round up)
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    for (sv = 0, lv = 0x400;  sv < 8;  sv++, lv <<= 2) {
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        if (lv >= size) break;
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    }
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    // Note: the process ID comes from the PID register (always 0)
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    epn = (virt & M_EPN_EPNMASK) | M_EPN_EV | M_EPN_SIZE(sv);
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    rpn = (phys & M_RPN_RPNMASK) | M_RPN_EX | M_RPN_WR;
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    if (flags & CYGARC_MEMDESC_CI) {
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        rpn |= M_RPN_I;
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    }
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    if (flags & CYGARC_MEMDESC_GUARDED)
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        rpn |= M_RPN_G;
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    CYGARC_TLBWE(id, epn, rpn);
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    id++;
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    // Make caches default disabled when MMU is disabled.
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    return id;
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}
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// Initialize MMU to a sane (NOP) state.
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//
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// Initialize TLBs with 0, Valid bits unset.
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void
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cyg_hal_clear_MMU (void)
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{
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    cyg_uint32 tlbhi = 0;
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    cyg_uint32 tlblo = 0;
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    int id, max_tlbs;
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    // There are 64 TLBs.
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    max_tlbs = 64;
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    CYGARC_MTSPR (SPR_PID, 0);
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    for (id = 0; id < max_tlbs; id++) {
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        CYGARC_TLBWE(id, tlbhi, tlblo);
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    }
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}
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//--------------------------------------------------------------------------
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// Clock control - use the programmable (variable period) timer
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static cyg_uint32 _period;
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extern cyg_uint32 _hold_tcr;  // Shadow of TCR register which can't be read
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void
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hal_ppc40x_clock_initialize(cyg_uint32 period)
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{
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    cyg_uint32 tcr;
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    // Enable auto-reload
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    CYGARC_MFSPR(SPR_TCR, tcr);
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    tcr = _hold_tcr;
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    tcr |= TCR_ARE;
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    CYGARC_MTSPR(SPR_TCR, tcr);
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    _hold_tcr = tcr;
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    // Set up the counter register
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    _period = period;
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    CYGARC_MTSPR(SPR_PIT, period);
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}
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// Returns the number of clocks since the last interrupt
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externC void
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hal_ppc40x_clock_read(cyg_uint32 *val)
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{
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    cyg_uint32 cur_val;
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    CYGARC_MFSPR(SPR_PIT, cur_val);
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    *val = _period - cur_val;
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}
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externC void
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hal_ppc40x_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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{
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    hal_ppc40x_clock_initialize(period);
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}
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//
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// Delay for the specified number of microseconds.
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// Assumption: _period has been set already and corresponds to the
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// system clock frequency, normally 10ms.
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//
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externC void
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hal_ppc40x_delay_us(int us)
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{
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    cyg_uint32 delay_period, delay, diff;
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    cyg_uint32 pit_val1, pit_val2;
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    delay_period = (_period * us) / 10000;
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    delay = 0;
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    CYGARC_MFSPR(SPR_PIT, pit_val1);
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    while (delay < delay_period) {
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        // Wait for clock to "tick"
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        while (true) {
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            CYGARC_MFSPR(SPR_PIT, pit_val2);
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            if (pit_val2 != pit_val1) break;
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        }
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        if (pit_val2 > pit_val1) {
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            diff = pit_val2 - pit_val1;
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        } else {
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            diff = (pit_val2 + _period) - pit_val1;
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        }
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        delay += diff;
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        pit_val1 = pit_val2;
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    }
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}
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//--------------------------------------------------------------------------
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// End of var_misc.c

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