OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [ppc60x/] [v2_0/] [include/] [var_intr.h] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_VAR_INTR_H
2
#define CYGONCE_VAR_INTR_H
3
//=============================================================================
4
//
5
//      var_intr.h
6
//
7
//      Variant HAL interrupt and clock support
8
//
9
//=============================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
// Copyright (C) 2002 Gary Thomas
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//=============================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):   nickg
47
// Contributors:nickg, jskov, jlarmour, hmt, gthomas
48
// Date:        2000-04-02
49
// Purpose:     Variant interrupt support
50
// Description: The macros defined here provide the HAL APIs for handling
51
//              interrupts and the clock on the PPC60x variant CPUs.
52
// Usage:       Is included via the architecture interrupt header:
53
//              #include <cyg/hal/hal_intr.h>
54
//              ...
55
//
56
//####DESCRIPTIONEND####
57
//
58
//=============================================================================
59
 
60
// Additional trap/exceptions on PPC60x
61
#define CYGNUM_HAL_VECTOR_ITLB_MISS        0x10
62
#define CYGNUM_HAL_VECTOR_DTLB_LOAD_MISS   0x11
63
#define CYGNUM_HAL_VECTOR_DTLB_STORE_MISS  0x12
64
#define CYGNUM_HAL_VECTOR_SMI              0x13
65
 
66
#define CYGNUM_HAL_VSR_MAX                 CYGNUM_HAL_VECTOR_SMI
67
 
68
// No builtin interrupt controller in the PPC60x CPUs.
69
 
70
#include <cyg/hal/plf_intr.h>  // Maybe something on the platform though
71
 
72
//-----------------------------------------------------------------------------
73
#endif // ifndef CYGONCE_VAR_INTR_H
74
// End of var_intr.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.