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#ifndef CYGONCE_HAL_VAR_REGS_H
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#define CYGONCE_HAL_VAR_REGS_H
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//==========================================================================
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//
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// var_regs.h
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//
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// PowerPC 60x variant CPU definitions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov
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// Date: 2000-02-04
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// Purpose: Provide PPC60x register definitions
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// Description: Provide PPC60x register definitions
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// The short difinitions (sans CYGARC_REG_) are exported only
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// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
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// Usage: Included via the acrhitecture register header:
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// #include <cyg/hal/ppc_regs.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <cyg/hal/plf_regs.h> // Get any platform specifics
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//--------------------------------------------------------------------------
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// Cache
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#define CYGARC_REG_HID0 1008
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#define _HID0 CYGARC_REG_HID0
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#define _HID0_EMCP 0x80000000 // Enable machine check
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#define _HID0_EBA 0x20000000 // Enable bus address parity
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#define _HID0_EBD 0x10000000 // Enable bus data parity
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#define _HID0_BCLK 0x08000000
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#define _HID0_EICE 0x04000000
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#define _HID0_ECLK 0x02000000
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#define _HID0_PAR 0x01000000
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#define _HID0_DOZE 0x00800000
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#define _HID0_NAP 0x00400000
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#define _HID0_SLEEP 0x00200000
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#define _HID0_DPM 0x00100000
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#define _HID0_ICE 0x00008000 // Enable Instruction Cache
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#define _HID0_DCE 0x00004000 // Enable Data Cache
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#define _HID0_ILOCK 0x00002000 // Instruction Cache Lock
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#define _HID0_DLOCK 0x00001000 // Data Cache Lock
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#define _HID0_ICFI 0x00000800 // Instruction Cache [flash] Invalidate
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#define _HID0_DCFI 0x00000400 // Data Cache [flash] Invalidate
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#define _HID0_IFEM 0x00000080
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#define _HID0_FBIOB 0x00000010
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#define _HID0_ABE 0x00000008
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#define _HID0_NOOPT 0x00000001
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//--------------------------------------------------------------------------
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// BATs
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#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#define IBAT0U 528
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#define IBAT0L 529
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#define IBAT1U 530
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#define IBAT1L 531
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#define IBAT2U 532
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#define IBAT2L 533
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#define IBAT3U 534
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#define IBAT3L 535
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#define DBAT0U 536
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#define DBAT0L 537
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#define DBAT1U 538
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#define DBAT1L 539
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#define DBAT2U 540
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#define DBAT2L 541
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#define DBAT3U 542
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#define DBAT3L 543
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#define UBAT_BEPIMASK 0xfffe0000 // effective address mask
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#define UBAT_BLMASK 0x00001ffc // block length mask
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#define UBAT_VS 0x00000002 // supervisor mode valid bit
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#define UBAT_VP 0x00000001 // problem mode valid bit
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#define LBAT_BRPNMASK 0xfffe0000 // real address mask
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#define LBAT_W 0x00000040 // write-through
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#define LBAT_I 0x00000020 // caching-inhibited
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#define LBAT_M 0x00000010 // memory coherence
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#define LBAT_G 0x00000008 // guarded
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#define LBAT_PP_NA 0x00000000 // no access
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#define LBAT_PP_RO 0x00000001 // read-only
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#define LBAT_PP_RW 0x00000002 // read/write
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#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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//-----------------------------------------------------------------------------
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#endif // ifdef CYGONCE_HAL_VAR_REGS_H
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// End of var_regs.h
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