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//=============================================================================
//
//      hal_aux.c
//
//      HAL auxiliary objects and code; per platform
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   pfine
// Contributors:hmt
// Date:        2002-02-27
// Purpose:     HAL aux objects: startup tables.
// Description: Tables for per-platform initialization
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/hal_mem.h>            // HAL memory definitions
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_if.h>             // hal_if_init
#include <cyg/hal/hal_io.h>             // hal_if_init
#include <cyg/hal/hal_misc.h>           // cyg_hal_is_break
 
#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/mpc8260.h>            // Needed for IMMR structure
 
// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
    // Mapping for the Motorola MPC8260 development board
    CYGARC_MEMDESC_CACHE( 0x00000000, 0x04000000 ), // Main memory 60x SDRAM
    // Mapping for the FPGA and the MPC8260 Internal memory
    CYGARC_MEMDESC_NOCACHE( 0x04500000, 0x00400000 ),
    // Mapping for the Cluster Bus
    CYGARC_MEMDESC_NOCACHE( 0xE0000000, 0x10000000 ),
    // Mapping for the FLASH
    CYGARC_MEMDESC_NOCACHE( 0xff800000, 0x00800000 ), // ROM region
 
    CYGARC_MEMDESC_TABLE_END
};
 
 
/***********************/
/* Global Declarations */
/***********************/
//#define USE_SMC1
 
volatile t_PQ2IMM  *IMM;   /* IMM base pointer */
 
// Define some space in high SDRAM that I can use for debugging
#define nPFDEBUG
#ifdef PFDEBUG
cyg_uint32 *dbg_values = (cyg_uint32 *) 0x00FFFF00;
#endif
 
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
 
// Ports and Pins assigned for General Purpose I/O
// PORT  PIN(s) DIR (I/O)   Name      Init Value Comment
//-------------------------------------------------------------------
//  A    30-31     TBD                    TBD    Wires to RF Board
//  A      29       O     TS_RESET_L       0     Tiger Sharc Reset 
//  A      28       O     LP_ENB_L         1     Link Port Buffer Enable
//  A    26-27     TBD                    TBD    Wires to RF Board
//  A    18-23     TBD                    TBD    Wires to each Tiger Sharc
//  A    12-17      O     xxxxxxxxxx       0     Tiger Sharc Interrupt
//  B     4-7       O     xxxxxxxxxx      TBD    User controlled LEDs
//  C      8        I     xxxxxxxxxx      xxx    RF Board Interrupt
//  C      6        I     xxxxxxxxxx      xxx    FPGA Interrupt
//  C     0-5       I     xxxxxxxxxx      xxx    TSn Interrupt
//  D      20       ?     PPC_WAIT        TBD    Open Drain == High Z
//  D     7-9       O     CIMP 0-2        110    TS Impedance ctrl
//  D     4-6       O     DS 0-2          100    TS Drive Strength
 
 
// Ports and Pins assigned for Dedicated Pin Assignment
// PORT  PIN(s) DIR (I/O)   Name      Init Value Comment
//-------------------------------------------------------------------
//  D    16-19      x                     TBD    SPI to RF Board
//  D    14-15      x                     TBD    I2C
 
 
 
#define TS6_PPARA_INIT_MASK 0xFFF00000
#define TS6_PDIRA_INIT_MASK 0x3003F000
#define TS6_PDATA_INIT_MASK 0x1003F000
    IMM =  (t_PQ2IMM *)0x04700000;  /* MPC8260 internal register map  */
 
   /*-------------------------------------------*/
        /* Program the Port Pin Registers */
   /*-------------------------------------------*/
 
    IMM->io_regs[PORT_A].ppar &= 0xFFF00000;  /* Clear bits for GPIO */
    IMM->io_regs[PORT_A].pdir |= 0x000FC00C;  /* Set bits on outputs */
    IMM->io_regs[PORT_A].pdat |= 0x00000008;  /* Set high outputs bits */
    IMM->io_regs[PORT_A].pdat &= 0xFFF03FFB;  /* Clear low output bits */
 
// Initialize Port B Pins 4,5,6,7 general purpose IO
// Pin == 0 ==> LED on
// Pin 4 LED 18, Red
// Pin 5 LED 18, Green
// Pin 6 LED 17, Red
// Pin 7 LED 17, Green
    IMM->io_regs[PORT_B].ppar &= 0xF0FFFFFF;  /* Clear 4-7 */
    IMM->io_regs[PORT_B].pdir |= 0x0F000000;  /* Set  4-7 as outputs */
    IMM->io_regs[PORT_B].pdat |= 0x0F000000;  /* Clear LED's */
    IMM->io_regs[PORT_B].pdat &= 0xFDFFFFFF;  /* Set LED's 17 to green */
 
    IMM->io_regs[PORT_C].ppar &= 0x007FFFFF;  /* Clear 0 -8 */
    IMM->io_regs[PORT_C].pdir &= 0x007FFFFF;  /* Configure as inputs */
    //IMM->io_regs[PORT_C].podr &= 0xFF800000;  /* Configure as inputs */
 
    IMM->io_regs[PORT_D].ppar &= 0xF03FF7FF;
    IMM->io_regs[PORT_D].pdir |= 0x0FC00000;
    IMM->io_regs[PORT_D].podr |= 0x00000800;
    IMM->io_regs[PORT_D].pdat |= 0x09800000;
 
    // Dedicated Pin assignments for SPI
    IMM->io_regs[PORT_D].ppar |= 0x0000F000;
    IMM->io_regs[PORT_D].podr &= 0xFFFF0FFF;
    IMM->io_regs[PORT_D].pdir |= 0x0000F000;
 
 
#ifdef PFDEBUG
  int i;
  for(i = 0; i < 20;i++)
    dbg_values[i] = 0;
#endif
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
    hal_if_init();
#endif
 
}
// EOF hal_aux.c

Line No.	Rev	Author	Line
1	27	unneback	`//=============================================================================`
2			`//`
3			`// hal_aux.c`
4			`//`
5			`// HAL auxiliary objects and code; per platform`
6			`//`
7			`//=============================================================================`
8			`//####ECOSGPLCOPYRIGHTBEGIN####`
9			`// -------------------------------------------`
10			`// This file is part of eCos, the Embedded Configurable Operating System.`
11			`// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
12			`// Copyright (C) 2002 Gary Thomas`
13			`//`
14			`// eCos is free software; you can redistribute it and/or modify it under`
15			`// the terms of the GNU General Public License as published by the Free`
16			`// Software Foundation; either version 2 or (at your option) any later version.`
17			`//`
18			`// eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
19			`// WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`// for more details.`
22			`//`
23			`// You should have received a copy of the GNU General Public License along`
24			`// with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
26			`//`
27			`// As a special exception, if other files instantiate templates or use macros`
28			`// or inline functions from this file, or you compile this file and link it`
29			`// with other works to produce a work based on this file, this file does not`
30			`// by itself cause the resulting work to be covered by the GNU General Public`
31			`// License. However the source code for this file must still be made available`
32			`// in accordance with section (3) of the GNU General Public License.`
33			`//`
34			`// This exception does not invalidate any other reasons why a work based on`
35			`// this file might be covered by the GNU General Public License.`
36			`//`
37			`// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
38			`// at http://sources.redhat.com/ecos/ecos-license/`
39			`// -------------------------------------------`
40			`//####ECOSGPLCOPYRIGHTEND####`
41			`//=============================================================================`
42			`//#####DESCRIPTIONBEGIN####`
43			`//`
44			`// Author(s): pfine`
45			`// Contributors:hmt`
46			`// Date: 2002-02-27`
47			`// Purpose: HAL aux objects: startup tables.`
48			`// Description: Tables for per-platform initialization`
49			`//`
50			`//####DESCRIPTIONEND####`
51			`//`
52			`//=============================================================================`
53
54			`#include <pkgconf/hal.h>`
55			`#include <cyg/hal/hal_mem.h> // HAL memory definitions`
56			`#include <cyg/infra/cyg_type.h>`
57			`#include <cyg/hal/hal_if.h> // hal_if_init`
58			`#include <cyg/hal/hal_io.h> // hal_if_init`
59			`#include <cyg/hal/hal_misc.h> // cyg_hal_is_break`
60
61			`#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED`
62			`#include <cyg/hal/hal_diag.h>`
63			`#include <cyg/hal/ppc_regs.h>`
64			`#include <cyg/hal/hal_intr.h>`
65			`#include <cyg/hal/mpc8260.h> // Needed for IMMR structure`
66
67			`// The memory map is weakly defined, allowing the application to redefine`
68			`// it if necessary. The regions defined below are the minimum requirements.`
69			`CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {`
70			`// Mapping for the Motorola MPC8260 development board`
71			`CYGARC_MEMDESC_CACHE( 0x00000000, 0x04000000 ), // Main memory 60x SDRAM`
72			`// Mapping for the FPGA and the MPC8260 Internal memory`
73			`CYGARC_MEMDESC_NOCACHE( 0x04500000, 0x00400000 ),`
74			`// Mapping for the Cluster Bus`
75			`CYGARC_MEMDESC_NOCACHE( 0xE0000000, 0x10000000 ),`
76			`// Mapping for the FLASH`
77			`CYGARC_MEMDESC_NOCACHE( 0xff800000, 0x00800000 ), // ROM region`
78
79			`CYGARC_MEMDESC_TABLE_END`
80			`};`
81
82
83			`/***********************/`
84			`/* Global Declarations */`
85			`/***********************/`
86			`//#define USE_SMC1`
87
88			`volatile t_PQ2IMM IMM; / IMM base pointer */`
89
90			`// Define some space in high SDRAM that I can use for debugging`
91			`#define nPFDEBUG`
92			`#ifdef PFDEBUG`
93			`cyg_uint32 dbg_values = (cyg_uint32 ) 0x00FFFF00;`
94			`#endif`
95
96			`//--------------------------------------------------------------------------`
97			`// Platform init code.`
98			`void`
99			`hal_platform_init(void)`
100			`{`
101
102			`// Ports and Pins assigned for General Purpose I/O`
103			`// PORT PIN(s) DIR (I/O) Name Init Value Comment`
104			`//-------------------------------------------------------------------`
105			`// A 30-31 TBD TBD Wires to RF Board`
106			`// A 29 O TS_RESET_L 0 Tiger Sharc Reset`
107			`// A 28 O LP_ENB_L 1 Link Port Buffer Enable`
108			`// A 26-27 TBD TBD Wires to RF Board`
109			`// A 18-23 TBD TBD Wires to each Tiger Sharc`
110			`// A 12-17 O xxxxxxxxxx 0 Tiger Sharc Interrupt`
111			`// B 4-7 O xxxxxxxxxx TBD User controlled LEDs`
112			`// C 8 I xxxxxxxxxx xxx RF Board Interrupt`
113			`// C 6 I xxxxxxxxxx xxx FPGA Interrupt`
114			`// C 0-5 I xxxxxxxxxx xxx TSn Interrupt`
115			`// D 20 ? PPC_WAIT TBD Open Drain == High Z`
116			`// D 7-9 O CIMP 0-2 110 TS Impedance ctrl`
117			`// D 4-6 O DS 0-2 100 TS Drive Strength`
118
119
120			`// Ports and Pins assigned for Dedicated Pin Assignment`
121			`// PORT PIN(s) DIR (I/O) Name Init Value Comment`
122			`//-------------------------------------------------------------------`
123			`// D 16-19 x TBD SPI to RF Board`
124			`// D 14-15 x TBD I2C`
125
126
127
128			`#define TS6_PPARA_INIT_MASK 0xFFF00000`
129			`#define TS6_PDIRA_INIT_MASK 0x3003F000`
130			`#define TS6_PDATA_INIT_MASK 0x1003F000`
131			`IMM = (t_PQ2IMM )0x04700000; / MPC8260 internal register map */`
132
133			`/-------------------------------------------/`
134			`/* Program the Port Pin Registers */`
135			`/-------------------------------------------/`
136
137			`IMM->io_regs[PORT_A].ppar &= 0xFFF00000; /* Clear bits for GPIO */`
138			`IMM->io_regs[PORT_A].pdir \|= 0x000FC00C; /* Set bits on outputs */`
139			`IMM->io_regs[PORT_A].pdat \|= 0x00000008; /* Set high outputs bits */`
140			`IMM->io_regs[PORT_A].pdat &= 0xFFF03FFB; /* Clear low output bits */`
141
142			`// Initialize Port B Pins 4,5,6,7 general purpose IO`
143			`// Pin == 0 ==> LED on`
144			`// Pin 4 LED 18, Red`
145			`// Pin 5 LED 18, Green`
146			`// Pin 6 LED 17, Red`
147			`// Pin 7 LED 17, Green`
148			`IMM->io_regs[PORT_B].ppar &= 0xF0FFFFFF; /* Clear 4-7 */`
149			`IMM->io_regs[PORT_B].pdir \|= 0x0F000000; /* Set 4-7 as outputs */`
150			`IMM->io_regs[PORT_B].pdat \|= 0x0F000000; /* Clear LED's */`
151			`IMM->io_regs[PORT_B].pdat &= 0xFDFFFFFF; /* Set LED's 17 to green */`
152
153			`IMM->io_regs[PORT_C].ppar &= 0x007FFFFF; /* Clear 0 -8 */`
154			`IMM->io_regs[PORT_C].pdir &= 0x007FFFFF; /* Configure as inputs */`
155			`//IMM->io_regs[PORT_C].podr &= 0xFF800000; /* Configure as inputs */`
156
157			`IMM->io_regs[PORT_D].ppar &= 0xF03FF7FF;`
158			`IMM->io_regs[PORT_D].pdir \|= 0x0FC00000;`
159			`IMM->io_regs[PORT_D].podr \|= 0x00000800;`
160			`IMM->io_regs[PORT_D].pdat \|= 0x09800000;`
161
162			`// Dedicated Pin assignments for SPI`
163			`IMM->io_regs[PORT_D].ppar \|= 0x0000F000;`
164			`IMM->io_regs[PORT_D].podr &= 0xFFFF0FFF;`
165			`IMM->io_regs[PORT_D].pdir \|= 0x0000F000;`
166
167
168			`#ifdef PFDEBUG`
169			`int i;`
170			`for(i = 0; i < 20;i++)`
171			`dbg_values[i] = 0;`
172			`#endif`
173			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
174			`hal_if_init();`
175			`#endif`
176
177			`}`
178			`// EOF hal_aux.c`

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [ts6/] [v2_0/] [src/] [hal_aux.c] - Blame information for rev 502