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#==============================================================================
2
##
3
##      vads.S
4
##
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##      MPC8260 VADS board hardware setup
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
## Copyright (C) 2002 Gary Thomas
13
##
14
## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
16
## Software Foundation; either version 2 or (at your option) any later version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License along
24
## with eCos; if not, write to the Free Software Foundation, Inc.,
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26
##
27
## As a special exception, if other files instantiate templates or use macros
28
## or inline functions from this file, or you compile this file and link it
29
## with other works to produce a work based on this file, this file does not
30
## by itself cause the resulting work to be covered by the GNU General Public
31
## License. However the source code for this file must still be made available
32
## in accordance with section (3) of the GNU General Public License.
33
##
34
## This exception does not invalidate any other reasons why a work based on
35
## this file might be covered by the GNU General Public License.
36
##
37
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38
## at http://sources.redhat.com/ecos/ecos-license/
39
## -------------------------------------------
40
#####ECOSGPLCOPYRIGHTEND####
41
##=============================================================================
42
#######DESCRIPTIONBEGIN####
43
##
44
## Author(s):    nickg
45
## Contributors: wpd, gthomas
46
## Date:         2002-12-09
47
## Purpose:      VADS MPC8260 board hardware setup
48
## Description:  This file contains any code needed to initialize the
49
##               hardware on the Motorola VADS MPC8260 board.
50
##
51
######DESCRIPTIONEND####
52
##
53
##=============================================================================
54
 
55
#include 
56
 
57
#include 
58
#include                /* on-chip resource layout, special */
59
#------------------------------------------------------------------------------
60
 
61
        .globl  hal_hardware_init
62
hal_hardware_init:
63
// It is possible that the board may experience a soft reset, which
64
// will cause this hal_hardware_init routine to be called.  As a
65
// result of the soft reset, the IMMR, memory controller, system
66
// protection logic, interrupt controller and parallel I/O pins are
67
// NOT reset (MPC8260 User Manual p 5-2), and therefor we do not want to
68
// run the setup in this routine.  Luckily, a hard reset will clear
69
// the NHR bit (bit 15) of the HID0 register.  We will check for this bit
70
// to be 0 (implying a hard reset).  If it is 0, we will run the
71
// initialization.  If non-zero, we will skip the initialization.
72
//
73
// If we do the initialization, then we must set the NHR bit so that
74
// next time we hit this point in the routine, we can determine the type
75
// of reset.
76
//#ifdef DCSPRI_HAL_VADS_ROM_MLT_RAM
77
        // Today, we will totally skip over all of this if we are using
78
        // the RAM memory layout
79
//      b       hardware_init_done
80
//#endif
81
 
82
   mfspr  r22,CYGARC_REG_HID0    # Get contents of HID0
83
   rlwinm r23,r22,0,15,15 #shift r0 by 0, mask HID0 with 0x10000, store in r23
84
   cmpwi  r23,0       # Compare r23 with 0
85
   bne    hardware_init_done
86
 
87
        mfspr r31,CYGARC_REG_LR
88
 
89
 
90
   #----------------------------------------------
91
   # Load the IMMR register with the base address
92
   #----------------------------------------------
93
 
94
   addis    r4,0,0x0471   # IMMR base addr = 0x04700000+10000. We add
95
                          # 0x10000 because using relative addressing
96
                          # in load and store instructions only allow a
97
                          # offset from the base of +/-32767.
98
   addis    r5,0,0x0470
99
 
100
   addis    r3,0,0x0F01
101
 
102
# The default IMMR base address was 0x0F0000000 as
103
# originally programmed into the Hard Reset
104
# Configuration Word.
105
   stw      r5,CYGARC_REG_IMM_IMMR(r3)
106
 
107
 
108
 
109
   mfspr    r21,CYGARC_REG_HID0   # get HID0 in R21
110
   oris     r21,r21,0x1     # Set bit 15 of HID0 (NHR)
111
 
112
   mtspr    CYGARC_REG_HID0,r21       # load HID0 with NHR set
113
 
114
 
115
   #*******************************************
116
   # Main System Clock Configuration Registers
117
   #*******************************************
118
 
119
   #-------------------------------------------------------------------------
120
   # We only need to program the System Clock Control Register (SCCR). The
121
   # System Clock Mode Register (SCMR) doesn t need to be programmed here
122
   # because the MODCLK_HI bits in the Hard Reset Configuration Word and the
123
   # MODCK pins dictate the values in the SCCR during power-on reset.
124
   #-------------------------------------------------------------------------
125
 
126
   #-------------------------------------------------------------------------
127
   # Program the System Clock Control Register (SCCR).
128
   #
129
   # - Bits 0 - 28 Reserved. Clear to 0.
130
   #
131
   # - CLPD (CPM Low Power Disable) = 0 =
132
   #
133
   #     CPM does not enter low power mode when the core enters low power
134
   #     mode.
135
   #
136
   # - DFBRG (Division Factor of BRGCLK) = 01 - Divide by 8.
137
   #
138
   #-------------------------------------------------------------------------
139
 
140
 
141
   addis    r3,0,0x0000
142
   ori      r3,r3,0x0001   # SCCR = 0x00000001
143
   stw      r3,CYGARC_REG_IMM_SCCR(r4)
144
 
145
   #~~~~~~~~~~~~~~~~~~~~
146
   # Initialize the SIU
147
   #~~~~~~~~~~~~~~~~~~~~
148
 
149
   bl       init_siu
150
 
151
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
152
   # Initialize the memory controller and SDRAM
153
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
154
 
155
   bl       init_memc
156
 
157
   mtspr    CYGARC_REG_LR,r31      # restore original Link Register value
158
 
159
hardware_init_done:
160
        bclr 20,0
161
 
162
 
163
#########################################################################
164
# Function: init_siu
165
#
166
# Description: Initializes the System Interface Unit
167
#
168
#  History:
169
#
170
#
171
#########################################################################
172
 
173
init_siu:
174
 
175
   #-----------------------------------------------------------------------
176
   # Program the System Protection Control Register with the following
177
   # values:
178
   #
179
   # - SWTC (Software Watchdog Timer Count) = 0xFFFF = programmed to max
180
   #   count value.
181
   #
182
   # - BMT (Bus Monitor Timing) = 0xFF = Set to max timeout period.
183
   #
184
   # - PBME (60x Bus Monitor Enable) = 1 = enabled.
185
   #
186
   # - LBME (Local Bus Monitor Enable) = 1 = enabled.
187
   #
188
   # - Bits 26-28 Reserved. Set to 0.
189
   #
190
   # - SWE (Software Watchdog Enabled) = 0 = disabled for now. User will
191
   #   have to enable this in a non-debug application.
192
   #
193
   # - SWRI (Software Watchdog Reset/Interrupt Select) = 1 = Software
194
   #   watchdog timeout or bus monitor time-out causes a soft reset.
195
   #
196
   # - SWP (Software Watchdog Prescale) = 1 = clock is prescaled.
197
   #-----------------------------------------------------------------------
198
 
199
   addis    r3,0,0xFFFF
200
   ori      r3,r3,0xFFC3   # SYPCR = 0xFFFFFFC3
201
   stw      r3,CYGARC_REG_IMM_SYPCR(r4)
202
 
203
 
204
   #-------------------------------------------------------------------------
205
   # Program the Bus Configuration Register. The details are as follows:
206
   #
207
   # - EBM (External Bus Mode) = 0 = Single MPC8260 bus mode is assumed.
208
   #
209
   # - APD (Address Phase delay) = 001 =
210
   #
211
   #     One address tenure wait states for address operations initiated by
212
   #     a 60x bus master.
213
   #
214
   # - L2C (Secondary Cache Controller) = 0 = No secondary cache controller
215
   #                                          is assumed.
216
   #
217
   # - L2D (L2 cache hit Delay) = 000 = This is a don t care because we re
218
   #                                    not using the L2 cache.
219
   #
220
   # - PLDP (PipeLine maximum Depth) = 0 = The pipeline max depth is one.
221
   #
222
   # - Bits 9-11 = Reserved. Set to 0.
223
   #
224
   # - ETM (Compatibility Mode enable) = 1 = Extended transfer mode is
225
   #                                         enabled.
226
   #
227
   # - LETM (Local Bus Compatibility Mode Enable) = 1 =
228
   #
229
   #     Extended transfer mode is enabled on the local bus.
230
   #
231
   # - EPAR (Even Parity) = 0 = This is a do not care.
232
   #
233
   # - LEPAR (Local Bus Even Parity) = 0 = This is a do not care.
234
   #
235
   # - Bits 16-20 = Reserved. Set to 0.
236
   #
237
   # - EXDD (External Master Delay Disable) = 0 =
238
   #
239
   #     The memory controller inserts one wait state between the assertion
240
   #     of TS and the assertion of CS when an external master accesses an
241
   #     address space controlled by the memory controller.
242
   #
243
   # - Bits 22-26 = Reserved. Set to 0.
244
   #
245
   # - ISPS (Internal Space Port Size) = 0 =
246
   #
247
   #     MPC8260 acts as a 64-bit slave to external master accesses to its
248
   #     internal space.
249
   #
250
   # - Bits 28-31 = Reserved. Set to 0.
251
   #
252
   #-------------------------------------------------------------------------
253
 
254
   addis    r3,0,0x100c
255
   stw      r3,CYGARC_REG_IMM_BCR(r4)
256
 
257
   #-------------------------------------------------------------------------
258
   # Program the 60x Bus Arbiter Configuration Register. The details are as
259
   # follows:
260
   #
261
   # - Bits 0-1 = Reserved. Set to 0.
262
   #
263
   # - DBGD (Data Bus Grant Delay) = Minimum of zero wait states for PowerPC
264
   #                                 master-initiated data operations. This
265
   #                                 is the minimum delay between TS/ and
266
   #                                 DBG/.
267
   #
268
   # - Bits 3 = Reserved. Set to 0.
269
   #
270
   # - PRKM (Parking Master) = 0010 = CPM is at a low request level for the
271
   #                                  parked master.
272
   #
273
   #-------------------------------------------------------------------------
274
 
275
   addi     r3,0,0x0002
276
   stb      r3,CYGARC_REG_IMM_PPC_ACR(r4)
277
 
278
 
279
   #-------------------------------------------------------------------------
280
   # Program the 60x Bus Arbitration-Level[High] Register. The priority for
281
   # potential bus masters are defined by locating the value associated with
282
   # a particular master from the PRKM field in the PPC_ACR register and
283
   # inserting its value in the priority field. Priority field 0 is the
284
   # highest priority and the lowest is Priority field 15 in the PPC_ALRH
285
   # register.
286
   #
287
   # - Priority Field 0 = 0000 = CPM high request level
288
   #
289
   # - Priority Field 1 = 0001 = CPM middle request level
290
   #
291
   # - Priority Field 2 = 0010 = CPM low request level
292
   #
293
   # - Priority Field 3 = 0110 = Internal Core
294
   #
295
   # - Priority Field 4 = 0111 = External Master 1
296
   #
297
   # - Priority Field 5 = 1000 = External Master 2
298
   #
299
   # - Priority Field 6 = 1001 = External Master 3
300
   #
301
   # - Priority Field 7 = 0011 = Reserved
302
   #
303
   #-------------------------------------------------------------------------
304
 
305
   addis    r3,0,0x0126
306
   ori      r3,r3,0x7893
307
   stw      r3,CYGARC_REG_IMM_PPC_ALRH(r4)
308
 
309
 
310
   #------------------------------------------------------------------------
311
   #
312
   # First program the SIUMCR. The details are as follows:
313
   #
314
   # - BBD (Bus Busy Disable) = 0 = [ABB/]/[IRQ2] pin is ABB/ and [DBB/]/IRQ2
315
   #                                pin is DBB/.
316
   #
317
   # - ESE (External Snoop Enable = 0 = [GPL/]/[IRQ1/] pin is IRQ1/
318
   #
319
   # - PBSE (Parity Byte Select Enable) = 0 = Parity byte select is disabled.
320
   #
321
   # - CDIS (Core DISable) = 0 = The PowerQUICCII CPU core is enabled.
322
   #
323
   # - DPPC (Data Parity Pins Configuration) = 10 =
324
   #
325
   #    Gives the following pin meanings:   DP(0)|RSRV/|EXT_BR2/  = RSRV/
326
   #                                        DP(1)|IRQ1/|EXT_BG2/  = IRQ1/
327
   #                                        DP(2)|TLBISYNC/|IRQ2/ = TLBISYNC/
328
   #                                        DP(3)|IRQ3/           = IRQ3/
329
   #                                        DP(4)|IRQ4/           = IRQ4/
330
   #                                        DP(5)|TBEN/|IRQ5      = TBEN/
331
   #                                        DP(6)|CSE(0)|IRQ6/    = CSE(0)
332
   #                                        DP(7)|CSE(1)|IRQ7/    = CSE(1)
333
   #
334
   # - L2CPC (L2 Cache Pins Configuration) = 00 =
335
   #
336
   #    Gives the following pin meanings:   CI/|BADDR(29)|IRQ2/ = CI/
337
   #                                        WT/|BADDR(30)|IRQ3/ = WT/
338
   #                                        L2_HIT/|IRQ4        = L2_HIT/
339
   #
340
   #                                        CPU_BG/|BADDR(31)
341
   #                                        |IRQ5/              = CPU_BG/
342
   #
343
   # - LBPC (Local Bus Pins Configuration) = 00 =
344
   #
345
   #    Local Bus pins function as local bus.
346
   #
347
   # - APPC (Address Parity Pins Configuration) = 10 =
348
   #
349
   #    Gives the following pin meanings: MODCK1|AP(1)|TC(0)  = BNKSEL(0)
350
   #                                      MODCK2|AP(2)|TC(1)  = BNKSEL(1)
351
   #                                      MODCK3|AP(3)|TC(2)  = BNKSEL(2)
352
   #                                      IRQ7/|APE/|INT_OUT/ = IRQ7/+INT_OUT/
353
   #                                      CS11/|AP(0)         = CS11/
354
   #
355
   # - CS10PC (Chip Select 10-pin Configuration) = 00 =
356
   #
357
   #    CS10/|BCTL1/|DBG_DIS/ = CS10/
358
   #
359
   # - BCTLC (Buffer Control Configuration) = 00 =
360
   #
361
   #    BCTL0 pin is used as W|R/ control. BCTL1 is used as OE/ control if
362
   #    BCTL1 was connected to its alternate pin.
363
   #
364
   # - MMR (Mask Masters Requests) = 00 = No masking on bus request lines.
365
   #
366
   # - LPBSE (Local Bus Parity Byte Select Enable) = 0
367
   #
368
   #    Parity byte select is disabled.
369
   #
370
   # Bits 19-31 are reserved and set to 0.
371
   #
372
   #------------------------------------------------------------------------
373
 
374
   #--------------------------------------------------------------------------
375
   # Program the 60x Bus Transfer Error Status and Control Register 1. The
376
   # details are as follows:
377
   #
378
   # - DMD (Data Errors Disable) = 1 =
379
   #
380
   #     Disable all data errors on the 60x bus. Also parity single and double
381
   #     ECC error.
382
   #
383
   # - All other bits are either status or reserved bits. All reserved bits
384
   #   should be set to 0.
385
   #--------------------------------------------------------------------------
386
 
387
   addis    r3,0,0x0000
388
   ori      r3,r3,0x4000
389
   stw      r3,CYGARC_REG_IMM_TESCR1(r4)
390
 
391
   #--------------------------------------------------------------------------
392
   # Program the Local Bus Transfer Error Status and Control Register 1. The
393
   # details are as follows:
394
   #
395
   # - DMD (Data Errors Disable) = 1 =
396
   #
397
   #     Disable parity errors on the Local bus.
398
   #
399
   # - All other bits are either status or reserved bits. All reserved bits
400
   #   should be set to 0.
401
   #--------------------------------------------------------------------------
402
 
403
   addis    r3,0,0x0000
404
   ori      r3,r3,0x4000
405
   stw      r3,CYGARC_REG_IMM_LTESCR1(r4)
406
 
407
 
408
   #-------------------------------------------------------------------------
409
   # First, program the Memory Periodic Timer Prescaler Register (MPTPR).
410
   # Finding the value to this ties in with the desired SDRAM Refresh
411
   # Timer (PSRT) value and the required Refresh Command interval for
412
   # refreshing each row. The Refresh Command interval is found by
413
   # determining the number of rows on the SDRAM device. In this case
414
   # its 2048. The "total time between refresh" value in the AC characteristic
415
   # section of the data sheet is 32.8 msec. This value is divided by the
416
   # number of rows to give the number of Refresh commands that needs to be
417
   # sent in a 32.8 msec interval. This value is 32.8 Msec/2048 = 16.02 usec.
418
   # Due to probable contention from time to time with other memory
419
   # controller bus requests, lets make the refresh command interval to be
420
   # around 15.5 usec.
421
   #
422
   # Now let us divide the input VADs system clock by 64 (somewhat arbitrary).
423
   # If this is our prescaler value then the input frequency to the Refresh
424
   # timer is 1.031 Mhz. Using the formula:
425
   #
426
   #        Timer Period = PSRT
427
   #                       ----
428
   #                       F(MPTC)
429
   #
430
   #        - Where F(MPTC) is the output from the MPT Prescaler block
431
   #          or 66 Mhz/64 = 1.031 Mhz.
432
   #
433
   #        - Timer Period = 15.5 usec
434
   #
435
   # The PSRT value would be approximately 16.
436
   #
437
   # The clock distribution block diagram looks like this:
438
   #
439
   #   ----------      -------------         -----------    -------------
440
   #   | Clock   |     |   MPT     |         | SDRAM   |    | Refresh   |
441
   #   | Gen.    |-----| Prescaler |---------| Refresh |----| Command   |
442
   #   | 66 Mhz  |     -------------         | Timer   |    | Logic in  |
443
   #   | on Vads |                           -----------    | Mem.Cont. |
444
   #   | Board   |                                          -------------
445
   #   -----------
446
   #
447
   #-------------------------------------------------------------------------
448
 
449
   addi     r5,0,0x4000      # load 0x40 or 64 into the PTP field of MPTPR
450
   sth      r5,CYGARC_REG_IMM_MPTPR(r4)     # store half word - bits[16-31]
451
 
452
 
453
 
454
   #-----------------------
455
   # return from init_siu
456
   #-----------------------
457
 
458
   bclr  20,0           # jump unconditionally to effective address in Link
459
                        # register
460
 
461
 
462
#########################################################################
463
# Function: init_memc
464
#
465
# Description:
466
#
467
#  The following registers directly control the memory controllers
468
#  operation:
469
#
470
#  BR0-BR11 - Base Register Banks 0-11
471
#  OR0-OR11 - Option Register Banks 0-11
472
#  PSDMR    - 60x bus SDRAM machine mode register
473
#  LSDMR    - Local bus SDRAM machine mode register
474
#  MAMR     - UPMA mode register
475
#  MBMR     - UPMB mode register
476
#  MCMR     - UPMC mode register
477
#  MDR      - Memory data register
478
#  MAR      - Memory address register
479
#  MPTPR    - Memory periodic timer pre-scaler register
480
#  PURT     - 60x bus assigned UPM refresh timer
481
#  PSRT     - 60x bus assigned SDRAM refresh timer
482
#  LURT     - Local Bus assigned UPM refresh timer
483
#  LSRT     - Local Bus assigned SDRAM refresh timer
484
#
485
#  This example will program the following registers. The rest will remain at
486
#  their default values.
487
#
488
#  BR0      - Base Register for Flash Memory
489
#  OR0      - Option Register for Flash Memory
490
#  BR1      - Base Register for BCSR (Board Control and Status Registers)
491
#  OR1      - Option Register for BCSR
492
#  BR2      - Base Register for 60x SDRAM
493
#  OR2      - Option Register for 60x SDRAM
494
#  BR3      - Base Register for 60x Local Bus SDRAM
495
#  OR3      - Option Register for 60x Local Bus SDRAM
496
#  PSDMR    - 60x bus SDRAM machine mode register
497
#  LSDMR    - Local bus SDRAM machine mode register
498
#  MPTPR    - Memory periodic timer pre-scaler register
499
#  PSRT     - 60x bus assigned SDRAM refresh timer
500
#  LSRT     - Local Bus assigned SDRAM refresh timer
501
#
502
#
503
#  History:
504
#
505
#########################################################################
506
 
507
init_memc:
508
 
509
   mfspr    r30,CYGARC_REG_LR        # Save the Link Register value. The link registers
510
                          # value will be restored so that this function
511
                          # can return to the calling address.
512
 
513
   bl    init_flash        # 8 Mbyte of flash memory
514
 
515
   bl    init_bcsr         # Board Control and Status Registers
516
 
517
   bl    init_local_sdram  # Local Bus SDRAM
518
 
519
   bl    init_60x_sdram    # Main 60x Bus SDRAM
520
 
521
   #-----------------------
522
   # return from init_memc
523
   #-----------------------
524
 
525
   mtspr    CYGARC_REG_LR,r30      # restore original Link Register value
526
 
527
   bclr  20,0           # jump unconditionally to effective address in Link
528
                        # register
529
 
530
 
531
 
532
############################################################################
533
# Function: init_flash
534
#
535
# Description: This function programs Base Register 0 and Option Register 0
536
#              designating bank 0 for the 8Mbyte flash SIMM on the VADS
537
#              board. Programming these two registers describes how the
538
#              MPC8260 will inter-operate with this memory space and thus
539
#              this memory device.
540
#
541
#  History:
542
#
543
############################################################################
544
 
545
init_flash:
546
 
547
   #-------------------------------------------------------------------------
548
   # Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
549
   #                        flash that resides on the MPC8260 VADS board.
550
   #                        The particulars are defined here.
551
   #
552
   # BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value
553
   #                     represents the upper 17 bits of the base address.
554
   #
555
   # Bits 17-18 reserved. = 00
556
   #
557
   # PS (Port Size) = 11b = 32 bit port size
558
   #
559
   # DECC (Data Error Correction and Checking) = 00 = Data errors checking
560
   #                                                  Disabled.
561
   #
562
   # WP (Write Protect) = 0 = both read and write accesses are allowed
563
   #
564
   # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
565
   #                             for 60x bus Selected
566
   #
567
   # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
568
   #                                                 the memory controller
569
   #                                                 according to MSEL.
570
   #
571
   # ATOM (Atomic Operation) = 00 = The address space controlled by the
572
   #                                memory controller bank is not used for
573
   #                                atomic operations.
574
   #
575
   # DR (Delayed Read) = 0 = Normal operation.
576
   #
577
   # V (Valid Bit) =  1 = Valid bit set
578
   #-------------------------------------------------------------------------
579
#define nPFHACK
580
#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000
581
   addis    r3,0,0xFE00   # R3 holds the value temporarily
582
#else
583
   addis    r3,0,0xFF80   # R3 holds the value temporarily
584
#endif
585
   ori      r3,r3,0x1801
586
   #-------------------------------------------------------------------------
587
   # Option Register 0 (OR0) for GPCM use: further flash definitions
588
   #
589
   # AM (Address Mask) = 0xFF80+0b = We have masked the upper 9 bits which
590
   #                                 defines a 8 Mbyte memory block.
591
   #
592
   # Bits 17-19 Reserved - set to 000.
593
   #
594
   # CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter
595
   #                                        of a clock early.
596
   #
597
   # ACS (Address To Chip-Select Setup) = 00 = CS/ is output the same time as
598
   #                                           the addr lines.
599
   #
600
   # Bit 23 Reserved - set to 0.
601
   #
602
   # SCY (Cycle Length In Clocks) = 0011 = Add a 3 clock cycle wait state
603
   #
604
   # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated
605
   #                                            internally by the memory
606
   #                                            controller unless GTA/ is
607
   #                                            asserted earlier externally.
608
   #
609
   # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
610
   #
611
   # EHTR (Extended Hold Time On Read Accesses) = 1 =
612
   #
613
   #     Extended hold time is generated by the memory controller. An idle
614
   #     clock cycle is inserted between a read access from the current bank
615
   #     and any write or read access to a different bank.
616
   #
617
   # Bit 31 Reserved - set to 0.
618
   #-------------------------------------------------------------------------
619
 
620
#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000
621
   addis    r5,0,0xFE00     # R5 holds the value temporarily
622
#else
623
   addis    r5,0,0xFF80     # R5 holds the value temporarily
624
#endif
625
   ori      r5,r5,0x0836
626
 
627
   #------------------------------------------------------------------------
628
   # It is important to note the order in which OR0 and BR0 are programmed.
629
   # When coming out of reset and CS0 is the global chip select, OR0 MUST be
630
   # programmed AFTER BR0. In all other cases BRx would be programmed after
631
   # ORx.
632
   #------------------------------------------------------------------------
633
 
634
   #------------------
635
   # Write the values
636
   #------------------
637
 
638
   stw        r3,CYGARC_REG_IMM_BR0(r4)
639
   stw        r5,CYGARC_REG_IMM_OR0(r4)
640
 
641
 
642
   bclr  20,0           # jump unconditionally to effective address in Link
643
                        # register
644
 
645
 
646
#########################################################################
647
# Function: init_bcsr
648
#
649
# Description: This function programs Base Register 1 and Option Register 1
650
#              designating bank 1 for BCSR0, BCSR1, and BCSR2 on the VADS
651
#              board. BCSR stands for Board Control and Status Register.
652
#              This space is treated as general I/O. Programming the
653
#              following 2 registers describes how the MPC8260 will inter-
654
#              operate with this memory space.
655
#
656
#  History:
657
#
658
#  Jan 9/99    jay
659
#
660
#########################################################################
661
 
662
init_bcsr:
663
 
664
 
665
   #-------------------------------------------------------------------------
666
   # Base Register 1 (BR1): Bank 1 is assigned to the Board Control and
667
   #                        Status Registers (BCSRs). There are 3
668
   #                        that resides on the MPC8260 VADS board.
669
   #                        The particulars are defined here.
670
   #
671
   # BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value
672
   #                     represents the upper 17 bits of the base address.
673
   #
674
   # Bits 17-18 reserved. = 00
675
   #
676
   # PS (Port Size) = 11b = 32 bit port size
677
   #
678
   # DECC (Data Error Correction and Checking) = 00 = Data errors checking
679
   #                                                  Disabled.
680
   #
681
   # WP (Write Protect) = 0 = both read and write accesses are allowed
682
   #
683
   # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
684
   #                             for 60x bus Selected
685
   #
686
   # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
687
   #                                                 the memory controller
688
   #                                                 according to MSEL.
689
   #
690
   # ATOM (Atomic Operation) = 00 = The address space controlled by the
691
   #                                memory controller bank is not used for
692
   #                                atomic operations.
693
   #
694
   # DR (Delayed Read) = 0 = Normal operation.
695
   #
696
   # V (Valid Bit) =  1 = Valid bit set
697
   #-------------------------------------------------------------------------
698
 
699
   addis    r3,0,0x0450     # R3 holds the value temporarily
700
   ori      r3,r3,0x1801
701
 
702
   #-------------------------------------------------------------------------
703
   # Option Register 1 (OR1) for GPCM use: further BCSR definitions
704
   #
705
   # AM (Address Mask) = 0xFFFF +1b = We have masked the upper 17 bits which
706
   #                                  which defines a 32 Kbyte memory block.
707
   #
708
   # Bits 17-19 Reserved - set to 000.
709
   #
710
   # CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
711
   #
712
   # ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same
713
   #                                           time as the addr lines.
714
   #
715
   # Bit 23 Reserved - set to 0.
716
   #
717
   # SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state
718
   #
719
   # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated
720
   #                                            internally by the memory
721
   #                                            controller unless GTA/ is
722
   #                                            asserted earlier externally.
723
   #
724
   # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
725
   #
726
   # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is
727
   #                                                  generated by the memory
728
   #                                                  controller
729
   #
730
   # Bit 31 Reserved - set to 0.
731
   #-------------------------------------------------------------------------
732
 
733
   addis    r5,0,0xFFFF     # R5 holds the value temporarily
734
   ori      r5,r5,0x8010
735
 
736
   #------------------
737
   # Write the values
738
   #------------------
739
 
740
   stw        r5,CYGARC_REG_IMM_OR1(r4)
741
   stw        r3,CYGARC_REG_IMM_BR1(r4)
742
 
743
 
744
   bclr  20,0    # jump unconditionally to effective address in Link
745
                 # register
746
 
747
 
748
 
749
#########################################################################
750
# Function: init_60x_sdram
751
#
752
# Description: This function programs the 16 Mbyte SDRAM DIMM on the VADS
753
#              board. This memory functions as the RAM for the 603 core and
754
#              is connected to the 60x bus. Base and Option Register 2 are
755
#              used as well as the SDRAM Machine #1 and Chip Select #2.
756
#
757
#  History:
758
#
759
#  Jan /9/99    jay      Initial Release
760
#
761
#########################################################################
762
 
763
init_60x_sdram:
764
 
765
 
766
   ##################
767
   # Program Refresh
768
   ##################
769
 
770
 
771
   #-------------------------------------------------------------------------
772
   # Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT).
773
   #-------------------------------------------------------------------------
774
 
775
   addi     r5,0,0x0010      # load 0x10 or 16
776
   stb      r5,CYGARC_REG_IMM_PSRT(r4)      # store byte - bits[24-31]
777
 
778
 
779
   #########################
780
   # Program Bank Registers
781
   #########################
782
 
783
 
784
   #-------------------------------------------------------------------------
785
   # Base Register 2 (BR2): Bank 2 is assigned to the 16 Mbyte 60x SDRAM DIMM
786
   #                        that resides on the MPC8260 VADS board. The
787
   #                        particulars are defined here.
788
   #
789
   # - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This
790
   #                       value represents the upper 17 bits of the base
791
   #                       address.
792
   #
793
   # - Bits 17-18 reserved. = 00 = cleared to 0.
794
   #
795
   # - PS (Port Size) = 00b = 64 bit port size
796
   #
797
   # - DECC (Data Error Correction and Checking) = 00 = Data errors checking
798
   #                                                    Disabled.
799
   #
800
   # - WP (Write Protect) = 0 = both read and write accesses are allowed
801
   #
802
   # - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected
803
   #
804
   # - EMEMC (External Memory Controller Enable) = 0 =
805
   #
806
   #    Accesses are handled by the memory controller according to MSEL.
807
   #
808
   # - ATOM (Atomic Operation) = 00 = The address space controlled by the
809
   #                                  memory controller bank is not used for
810
   #                                  atomic operations.
811
   #
812
   # - DR (Delayed Read) = 0 = Normal operation.
813
   #
814
   # - V (Valid Bit) =  1 = Valid bit set
815
   #-------------------------------------------------------------------------
816
 
817
   addis    r3,0,0x0000     # R3 holds the value temporarily
818
   ori      r3,r3,0x0041
819
 
820
   #-------------------------------------------------------------------------
821
   # Option Register 2 (OR2) for SDRAM Machine use: further SDRAM definitions
822
   #
823
   # - USDAM (Upper SDRAM Address Mask) = 11111b =
824
   #
825
   #    We have masked all 5 bits which defines a maximum 128 Mbyte block.
826
   #    Note that since the maximum SDRAM block size is 128 Mbyte, this field
827
   #    should always be 11111b.
828
   #
829
   # - SDAM (SDRAM Address Mask) = 1110000b = 16 Mbyte block.
830
   #
831
   # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size.
832
   #
833
   # - BPD (Banks Per Device) = 00 = 2 internal banks per device.
834
   #
835
   # - ROWST (Row Start Address Bit) = 011 = A9 being the row start address
836
   #                                         bit.
837
   #
838
   # - Bit 22 Reserved - set to 0.
839
   #
840
   # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines.
841
   #
842
   # - PMSEL (Page Mode Select) = 1 = Reserved
843
   #
844
   # - IBID (Internal bank interleaving within same device disable) = 0 =
845
   #
846
   #    Bank interleaving allowed.
847
   #
848
   # - AACKR (AACK/ release) = 0 = Normal operation.
849
   #
850
   # - Bits 29-31 Reserved - set to 0.
851
   #-------------------------------------------------------------------------
852
 
853
#define nCYGHWR_HAL_POWERPC_VADS_64MB_DIMM
854
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
855
   addis    r5,0,0xFC00     # R5 holds the value temporarily
856
   ori      r5,r5,0x28E0
857
#else
858
   addis    r5,0,0xFF00     # R5 holds the value temporarily
859
   ori      r5,r5,0x0CA0
860
#endif
861
 
862
   #------------------
863
   # Write the values
864
   #------------------
865
 
866
   stw        r5,CYGARC_REG_IMM_OR2(r4)
867
   stw        r3,CYGARC_REG_IMM_BR2(r4)
868
 
869
 
870
   ###########################################
871
   # Perform Initialization sequence to SDRAM
872
   ###########################################
873
 
874
   #-------------------------------------------------------------------------
875
   # Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used
876
   # to configure operations pertaining to SDRAM. Program the PSDMR, turning
877
   # off refresh services and changing the SDRAM operation to "Precharge all
878
   # banks". Then do a single write to an arbitrary location. Writing 0xFF
879
   # to address 0 will do the trick.
880
   #
881
   # - Bit 0 is reserved. Set to 0.
882
   #
883
   # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit
884
   #                               will be set later in this function as a
885
   #                               last step.
886
   #
887
   # - OP (SDRAM Operation) = 000 = Precharge all banks.
888
   #
889
   # - SDAM (Address Multiplex Size = 001 =
890
   #
891
   #   Coming up the value for this field is one of the most confusing
892
   #   and non-intuitive steps in the SDRAM programming process. This is how
893
   #   it works... The SDRAM device is a 16 Mbit DIMM that has a data width
894
   #   of 64 bits or 8 bytes. The bank size is 64 bits so the SDRAM will
895
   #   ignore the least significant 3 bits. Given this information and
896
   #   knowing that the number of row address lines is 11 and the column
897
   #   addresses is 9 and also knowing that the row addresses must be
898
   #   multiplexed, write out the following:
899
   #
900
   #   addresses ignored by SDRAM : A29 A30 A31
901
   #
902
   #   column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28
903
   #
904
   #   row addresses:   A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
905
   #
906
   #   When the memory controller multiplexes the addresses it puts the
907
   #   column addresses out on the actual physical pins that matches its
908
   #   corresponding effective address bits.
909
   #
910
   #   According to the SDRAM Address Multiplexing table in the memory
911
   #   controller section of the manual, SDAM selection of 001 fits the
912
   #   address layout given above. Because its the row that is multiplexed on
913
   #   designated column address pins, the row addresses are put out on the
914
   #   following column pins:
915
   #
916
   #   column ---------------------->  A20 A21 A22 A23 A24 A25 A26 A27 A28
917
   #                                    |   |   |   |   |   |   |   |   |
918
   #   row address -----------> A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
919
   #   on corresponding
920
   #   column pins.
921
   #
922
   #   Column pins A19, A18, and A17 were not connected to the DIMM device so
923
   #   A9 and A10 as well as the bank select address which is A8 are put out
924
   #   on their respective pins because it was decided that these address
925
   #   pins would be directly connected to the DIMM. That is, A10 of the real
926
   #   address is put out on the A10 pin, A9 on the A9 pin, etc.
927
   #
928
   #   As a final note on this subject, the row address is output on the
929
   #   address bus first on the actual column address pins according to the
930
   #   multiplexing scheme in the SDRAM address multiplexing table, then the
931
   #   column address follows which makes up the most significant part of the
932
   #   real address which is connected to the memory device.
933
   #
934
   #   Any entries in the multiplexing table that show a "-" means nothing is
935
   #   multiplexed on the physical pins shown on the top row of the table
936
   #   and therefore any part of the row address will also show up on its
937
   #   respective physical pin if this pin is not used for multiplexing. For
938
   #   example, for a SDAM of 001, the multiplexing table shows that A13
939
   #   through A0 are not multiplexed because they have "-" in their
940
   #   respective boxes. This means that A13 through A5 of the real address
941
   #   will show up multiplexed on address pins A22 through A14 and A13
942
   #   through A0 of the real address will also show up on their actual
943
   #   respective physical pins.
944
   #
945
   # - BSMA (Bank Select Multiplexed Address line) = 011 = A15-A17
946
   #
947
   #    BSMA determines how BNKSEL[0:2] will operate. This SDRAM has only 2
948
   #    banks, so only BANKSEL2 is of concern because its the least
949
   #    significant bit. BANKSEL2 should be programmed to operate as physical
950
   #    pin A17. Because we are multiplexing 9 column addresses, it will
951
   #    actually behave as A8.
952
   #
953
   # - SDA10 ("A10 Control") = 011 =
954
   #
955
   #    A9 is the address pin used for the activate command. The A10/AP pin
956
   #    the SDRAM needs to act as a command line during on phase of the
957
   #    access and as an address line in the other phase. The SDA10 pin on
958
   #    MPC8260 takes care of this function. Instead of connecting the
959
   #    A10/AP pin to A9 on the address bus, connect it to SDA10 and program
960
   #    SDA10 to function as A9.
961
   #
962
   # - RFRC (ReFresh ReCovery) = 101 =
963
   #
964
   #   Once a  refresh request is granted, the memory controller begins
965
   #   issuing auto-refresh commands to each device associated with the
966
   #   refresh timer in one clock intervals. After the last REFRESH
967
   #   command is issued, the memory controller waits for 7 clocks before
968
   #   the ACTIVATE command and before normal read/write operations can
969
   #   resume.
970
   #
971
   # - PRETOACT (PREcharge TO ACTivate interval) = 011 =
972
   #
973
   #   Wait 3 clock cycles before an activate command. This parameter is
974
   #   determined by the requirements of the SDRAM at a particular clock
975
   #   speed.
976
   #
977
   # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles.
978
   #
979
   # - BL (Burst Length) = 0 = SDRAM burst length is 4. This is programmed
980
   #                          into the SDRAM via the MRS commmand.
981
   #
982
   # - LDOTOPRE (Last Data Out TO PREcharge) = 01 =
983
   #
984
   #   The delay required from the last data out to precharge state is 1 clock
985
   #   cycle. This parameter is determined by the requirements of the SDRAM at
986
   #   a particular clock speed.
987
   #
988
   # - WRC (Write Recovery Time) = 01 =
989
   #
990
   #   Time needed to elapse before another operation is 1 clock cycle. This
991
   #   parameter is determined by the requirements of the SDRAM at a
992
   #   particular clock speed.
993
   #
994
   # - EAMUX (External Address MUltipleXing) = 0 No external address
995
   #                                             multiplexing.
996
   #
997
   # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control
998
   #                                       lines.
999
   #
1000
   # - CL (CAS Latency) = 10 =
1001
   #
1002
   #    CAS latency is 2. Two cycles after column address is registered, data
1003
   #    is valid. This parameter is determined by the requirements of the
1004
   #    SDRAM at a particular clock speed.
1005
   #
1006
   #-------------------------------------------------------------------------
1007
 
1008
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
1009
   addis    r3,0,0x294E
1010
   ori      r3,r3,0xB452
1011
#else
1012
   addis    r3,0,0x296E
1013
   ori      r3,r3,0xB452
1014
#endif
1015
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)
1016
   addis    r0,0,0
1017
 
1018
   addi     r3,0,0x00FF      # Load 0x000000FF into r3
1019
   stb      r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
1020
 
1021
 
1022
   #-------------------------------------------------------------------------
1023
   # Program the PSDMR keeping refresh services off and changing the
1024
   # SDRAM operation to "CBR Refresh". This step is responsible for issuing
1025
   # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
1026
   # by issuing the CBR Refresh command by programming the OP field of the
1027
   # PSDMR register and writing 0xFF 8 times to an arbitrary address.
1028
   #-------------------------------------------------------------------------
1029
 
1030
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
1031
   addis    r3,0,0x094E
1032
   ori      r3,r3,0xB452
1033
#else
1034
   addis    r3,0,0x096E
1035
   ori      r3,r3,0xB452
1036
#endif
1037
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)
1038
 
1039
   #------------------------------------------
1040
   # Loop 8 times, writing 0xFF to address 0
1041
   #------------------------------------------
1042
 
1043
   addi  r6,0,0x0008
1044
   mtspr CYGARC_REG_CTR,r6             # Load CTR with 8. The CTR special purpose
1045
                            # is spr 9
1046
 
1047
   addi  r3,0,0x00FF      # Load 0x000000FF into r3
1048
 
1049
write_loop:
1050
 
1051
   stb   r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
1052
 
1053
   bc    16,0,write_loop  # Decrement CTR, then branch if the decremented CTR
1054
                          # is not equal to 0
1055
 
1056
   #-------------------------------------------------------------------------
1057
   # Program the PSDMR again turning off refresh services and changing the
1058
   # SDRAM operation to "Mode Register Write". Then do a single write to an
1059
   # arbitrary location. The various fields that will be programmed in the
1060
   # mode register on the SDRAM were specified in fields of the PSDMR, like
1061
   # the BR (burst length) and the CL (CAS Latency) field.
1062
   #-------------------------------------------------------------------------
1063
 
1064
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
1065
   addis    r3,0,0x194E
1066
   ori      r3,r3,0xB452
1067
#else
1068
   addis    r3,0,0x196E
1069
   ori      r3,r3,0xB452
1070
#endif
1071
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)
1072
 
1073
   addi     r3,0,0x00FF      # Load 0x000000FF into r3
1074
   stb      r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
1075
 
1076
   #-------------------------------------------------------------------------
1077
   # Program the PSDMR one last time turning on refresh services and changing
1078
   # the SDRAM operation to "Normal Operation".
1079
   #-------------------------------------------------------------------------
1080
 
1081
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
1082
   addis    r3,0,0x414E
1083
   ori      r3,r3,0xB452
1084
#else
1085
   addis    r3,0,0x416E
1086
   ori      r3,r3,0xB452
1087
#endif
1088
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)
1089
 
1090
   #----------------------------
1091
   # return from init_60x_sdram
1092
   #----------------------------
1093
 
1094
   bclr  20,0    # jump unconditionally to effective address in Link
1095
                 # register
1096
 
1097
 
1098
#########################################################################
1099
# Function: init_local_sdram
1100
#
1101
# Description: This function programs the 4 Mbytes of SDRAM on the Local
1102
#              Bus on the VADS board. This memory functions as storage for
1103
#              connection tables and data buffers for the CPM peripherals.
1104
#              Base and Option Register 4 are used. SDRAM Machine #2
1105
#              and Chip Select #4 is used in the memory controller.
1106
#
1107
#  History:
1108
#
1109
#  Jan 9/99    jay
1110
#
1111
#########################################################################
1112
 
1113
init_local_sdram:
1114
 
1115
   ##################
1116
   # Program Refresh
1117
   ##################
1118
 
1119
   #-------------------------------------------------------------------------
1120
   # Program the Local Bus Assigned SDRAM Refresh Timer (LSRT). Note that the
1121
   # MPTPR register was programmed in the init_siu function which also
1122
   # dictates the frequency to the LSRT block. Because the frequency rating
1123
   # for the local bus SDRAM is same as the 60x SDRAM DIMM, only the LSRT
1124
   # needs to be programmed and it is going to be the same as the PSRT
1125
   # register.
1126
   #-------------------------------------------------------------------------
1127
 
1128
   addi     r5,0,0x0010      # load 0x10 or 16
1129
   stb      r5,CYGARC_REG_IMM_LSRT(r4)      # store byte - bits[24-31]
1130
 
1131
 
1132
   #########################
1133
   # Program Bank Registers
1134
   #########################
1135
 
1136
 
1137
   #-------------------------------------------------------------------------
1138
   # Base Register 4 (BR4): Bank 4 is assigned to the 4 Mbyte Local SDRAM
1139
   #                        bank that resides on the MPC8260 VADS board. The
1140
   #                        particulars are defined here.
1141
   #
1142
   # - BA (Base Address) = 0x0400+0b for a total of 17 address bits. This
1143
   #                       value represents the upper 17 bits of the base
1144
   #                       address.
1145
   #
1146
   # - Bits 17-18 reserved. = 00 = cleared to 0.
1147
   #
1148
   # - PS (Port Size) = 11b = 32 bit port size
1149
   #
1150
   # - DECC (Data Error Correction and Checking) = 00 = Data errors checking
1151
   #                                                    Disabled.
1152
   #
1153
   # - WP (Write Protect) = 0 = both read and write accesses are allowed
1154
   #
1155
   # - MS (Machine Select) = 011 = SDRAM Machine for Local bus Selected
1156
   #
1157
   # - EMEMC (External Memory Controller Enable) = 0 =
1158
   #
1159
   #    Accesses are handled by the memory controller according to MSEL.
1160
   #
1161
   # - ATOM (Atomic Operation) = 00 =
1162
   #
1163
   #    The address space controlled by the memory controller bank is not
1164
   #    used for atomic operations.
1165
   #
1166
   # - DR (Delayed Read) = 0 = Normal operation.
1167
   #
1168
   # - V (Valid Bit) =  1 = Valid bit set
1169
   #-------------------------------------------------------------------------
1170
 
1171
   addis    r3,0,0x0400     # R3 holds the value temporarily
1172
   ori      r3,r3,0x1861
1173
 
1174
   #-------------------------------------------------------------------------
1175
   # Option Register 4 (OR4) for SDRAM Machine use: further SDRAM definitions
1176
   #
1177
   # - USDAM (Upper SDRAM Address Mask) = 11111b =
1178
   #
1179
   #    We have masked all 5 bits which defines a maximum 128 Mbyte block Note
1180
   #    that since the maximum SDRAM block size is 128 Mbyte, this field
1181
   #    should always be 11111b.
1182
   #
1183
   # - SDAM (SDRAM Address Mask) = 1111100b = 4 Mbyte block.
1184
   #
1185
   # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size.
1186
   #
1187
   # - BPD (Banks Per Device) = 00 = 2 internal banks per device.
1188
   #
1189
   # - ROWST (Row Start Address Bit) = 101 = A11 being the row start address
1190
   #                                         bit.
1191
   #
1192
   # - Bit 22 Reserved - set to 0.
1193
   #
1194
   # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines.
1195
   #
1196
   # - PMSEL (Page Mode Select) = 0 = back-to-back page mode (normal
1197
   #                                  operation).
1198
   #
1199
   # - IBID (Internal bank interleaving within same device disable) = 0 =
1200
   #
1201
   #    Bank interleaving allowed.
1202
   #
1203
   # - AACKR (AACK/ release) = 0 = Normal operation.
1204
   #
1205
   # - Bits 29-31 Reserved - set to 0.
1206
   #-------------------------------------------------------------------------
1207
 
1208
   addis    r5,0,0xFFC0     # R5 holds the value temporarily
1209
   ori      r5,r5,0x1480
1210
 
1211
   #------------------
1212
   # Write the values
1213
   #------------------
1214
 
1215
   stw        r5,CYGARC_REG_IMM_OR4(r4)
1216
   stw        r3,CYGARC_REG_IMM_BR4(r4)
1217
 
1218
 
1219
   ###########################################
1220
   # Perform Initialization sequence to SDRAM
1221
   ###########################################
1222
 
1223
   #-------------------------------------------------------------------------
1224
   # Program the Local SDRAM Mode Registr (LSDMR). This register is used
1225
   # to configure operations pertaining to SDRAM on the Local bus. Turn off
1226
   # refresh services and change the SDRAM operation to "Precharge all banks".
1227
   # Then do a single write to an arbitrary location. Writing 0 top
1228
   # address 0 will do the trick.
1229
   #
1230
   # - Bit 0 is reserved. Set to 0.
1231
   #
1232
   # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit
1233
   #                               will be set later in this function as a
1234
   #                               last step.
1235
   #
1236
   # - OP (SDRAM Operation) = 101 = Precharge all banks.
1237
   #
1238
   # - SDAM (Address Multiplex Size = 000 =
1239
   #
1240
   #   Coming up the value for this field is one of the most confusing
1241
   #   and non-intuitive steps in the SDRAM programming process. This is how
1242
   #   it works... The SDRAM device is a 4 Mbit chip set that has a data
1243
   #   width of 32 bits or 4 bytes so the SDRAM will ignore the least
1244
   #   significant 2 bits. Given this information and knowing that the
1245
   #   number of row address lines is 11 and the column addresses is 8 and
1246
   #   also knowing that the row addresses must be multiplexed, write out the
1247
   #   following:
1248
   #
1249
   #   addresses ignored by SDRAM : A30 A31
1250
   #
1251
   #   column addresses: A22 A23 A24 A25 A26 A27 A28 A29
1252
   #
1253
   #   row addresses:   A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
1254
   #
1255
   #   When the memory controller multiplexes the addresses it puts the
1256
   #   column addresses out on the actual physical pins that matches its
1257
   #   corresponding effective address bits.
1258
   #
1259
   #   According to the SDRAM Address Multiplexing table in the memory
1260
   #   controller section of the manual, SDAM selection of 000 fits the
1261
   #   address layout given above. Because the row is what is multiplexed
1262
   #   on designated column address pins, the row addresses are put out on the
1263
   #   following column pins:
1264
   #
1265
   #.                                  8 column addresses
1266
   #                                   |
1267
   #   column ------------->A19 A20 A21|A22 A23 A24 A25 A26 A27 A28 A29
1268
   #                         |   |   |   |   |   |   |   |   |   |   |
1269
   #.  11 row addresses---->A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
1270
   #   on corresponding
1271
   #   column pins.
1272
   #
1273
   #   The row address is output on the address bus first, then the column
1274
   #   address.
1275
   #
1276
   # - BSMA (Bank Select Multiplexed Address line) = 100 = A16-A18
1277
   #
1278
   #    For Local bus accesses, this field is a "do not care". BNKSEL[0:2]
1279
   #    are associated with this field and these pins are only used for
1280
   #    60x compatible mode for 60x bus transactions.
1281
   #
1282
   # - SDA10 ("A10 Control") = 001 = A11 is the address pin used for the
1283
   #                                 activate command.
1284
   #
1285
   # - RFRC (ReFresh ReCovery) = 101 =
1286
   #
1287
   #   Once a refresh request is granted, the memory controller begins
1288
   #   issuing auto-refresh commands to each device associated with the
1289
   #   refresh timer in one clock intervals. After the last REFRESH
1290
   #   command is issued, the memory controller waits for 7 clocks before
1291
   #   the ACTIVATE command and before normal read/write operations can
1292
   #   resume.
1293
   #
1294
   # - PRETOACT (PREcharge TO ACTivate interval) = 010 =
1295
   #
1296
   #   Wait 2 clock cycles before an activate command.
1297
   #
1298
   # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles.
1299
   #
1300
   # - BL (Burst Length) = 1 = SDRAM burst length is 8. This is programmed
1301
   #                           into the SDRAM via the MRS commmand.
1302
   #
1303
   # - LDOTOPRE (Last Data Out TO PREcharge) = 00 =
1304
   #
1305
   #   The delay required from the last data out to precharge state is 0 clock
1306
   #   cycles.
1307
   #
1308
   # - WRC (Write Recovery Time) = 01 =
1309
   #
1310
   #   Time needed to elapse before another operation is 1 clock cycle.
1311
   #
1312
   # - EAMUX (External Address MUltipleXing) = 0 No external address
1313
   #                                             multiplexing.
1314
   #
1315
   # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control
1316
   #                                       lines.
1317
   #
1318
   # - CL (CAS Latency) = 10 = CAS latency is 2. Two cycles after column
1319
   #                           address is registered, data is valid.
1320
   #
1321
   #-------------------------------------------------------------------------
1322
 
1323
   addis    r3,0,0x2886
1324
   ori      r3,r3,0xA522
1325
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)
1326
 
1327
   addis    r2,0,0x0400
1328
   addi     r3,0,-1
1329
   stb      r3,0(r2)         # Write 0xFF to address 0x04000000
1330
 
1331
 
1332
   #-------------------------------------------------------------------------
1333
   # Program the LSDMR keeping refresh services off and changing the
1334
   # SDRAM operation to "CBR Refresh". This step is responsible for issuing
1335
   # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
1336
   # by issuing the CBR Refresh command by programming the OP field of the
1337
   # PSDMR register and writing 0xFF 8 times to an arbitrary address.
1338
   #-------------------------------------------------------------------------
1339
 
1340
   addis    r3,0,0x0886
1341
   ori      r3,r3,0xA522
1342
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)
1343
 
1344
   #--------------------------------------------------
1345
   # Loop 8 times, writing 0xFF to address 0x04000000
1346
   #--------------------------------------------------
1347
 
1348
   addis r6,0,0
1349
   ori   r6,r6,8
1350
   mtspr CYGARC_REG_CTR,r6           # Load CTR with 8.
1351
 
1352
   addi  r3,0,-1          # Load 0xFs into r3
1353
 
1354
write_loop1:
1355
 
1356
   stb   r3,0(r2)         # Write 0 to address 0x04000000
1357
 
1358
   bc    16,0,write_loop1 # Decrement CTR, then branch if the decremented CTR
1359
                          # is not equal to 0
1360
 
1361
   #-------------------------------------------------------------------------
1362
   # Program the LSDMR again turning off refresh services and changing the
1363
   # SDRAM operation to "Mode Register Write". Then do a single write to an
1364
   # arbitrary location. The various fields that will be programmed in the
1365
   # mode register on the SDRAM were specified in fields of the LSDMR, like
1366
   # the BR (burst length) and the CL (CAS Latency) field.
1367
   #-------------------------------------------------------------------------
1368
 
1369
   addis    r3,0,0x1886
1370
   ori      r3,r3,0xA522
1371
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)
1372
 
1373
   addi     r3,0,-1
1374
   stb      r3,0(r2)         # Write 0xFF to address 0x04000000
1375
 
1376
   #-------------------------------------------------------------------------
1377
   # Program the LSDMR one last time turning on refresh services and changing
1378
   # the SDRAM operation to "Normal Operation".
1379
   #-------------------------------------------------------------------------
1380
 
1381
   addis    r3,0,0x4086
1382
   ori      r3,r3,0xA522
1383
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)
1384
 
1385
   #------------------------------
1386
   # return from init_local_sdram
1387
   #------------------------------
1388
 
1389
   bclr  20,0    # jump unconditionally to effective address in Link
1390
                 # register
1391
 
1392
#------------------------------------------------------------------------------
1393
# end of vads.S

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