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##=============================================================================
2
##
3
##      viper.S
4
##
5
##      VIPER board hardware setup
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
## Copyright (C) 2002 Gary Thomas
13
##
14
## eCos is free software; you can redistribute it and/or modify it under
15
## the terms of the GNU General Public License as published by the Free
16
## Software Foundation; either version 2 or (at your option) any later version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License along
24
## with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26
##
27
## As a special exception, if other files instantiate templates or use macros
28
## or inline functions from this file, or you compile this file and link it
29
## with other works to produce a work based on this file, this file does not
30
## by itself cause the resulting work to be covered by the GNU General Public
31
## License. However the source code for this file must still be made available
32
## in accordance with section (3) of the GNU General Public License.
33
##
34
## This exception does not invalidate any other reasons why a work based on
35
## this file might be covered by the GNU General Public License.
36
##
37
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38
## at http://sources.redhat.com/ecos/ecos-license/
39
## -------------------------------------------
40
#####ECOSGPLCOPYRIGHTEND####
41
##=============================================================================
42
#######DESCRIPTIONBEGIN####
43
##
44
## Author(s):   hmt
45
## Contributors:hmt, gthomas
46
## Date:        1999-06-08
47
## Purpose:     VIPER board hardware setup
48
## Description: This file contains any code needed to initialize the
49
##              hardware on a VIPER PPC860 board.
50
##
51
######DESCRIPTIONEND####
52
##
53
##=============================================================================
54
 
55
#include 
56
 
57
#include                /* register symbols et al */
58
#include                /* on-chip resource layout, special */
59
                                        /* registers, IMM layout...         */
60
#include        /* more of the same */
61
 
62
#------------------------------------------------------------------------------
63
# this is controlled with one define for tidiness:
64
# (and it is undefined by default)
65
 
66
//#define CYGPRI_RAM_START_PROGRAMS_UPMS
67
 
68
#if defined(CYG_HAL_STARTUP_ROM) \
69
 || defined(CYG_HAL_STARTUP_ROMRAM) \
70
 || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
71
# define CYGPRI_DO_PROGRAM_UPMS
72
#endif
73
 
74
/* The intention is that we only set up the UPMs in ROM start, be it actual
75
 * ROM application start or Stub ROMs that we built from the same sources.
76
 *
77
 * The alternative approach - in which we have reliability doubts - is to
78
 * program the UPMs with *old* timing data in StubROM start, then
79
 * *reprogram* them with *new* timing data in RAM start - and of course
80
 * program with *new* timing data in plain ROM application start.
81
 * (Re-programming from new to new timing data fails - hence the suspicion
82
 * of reprogramming _at_all_, hence this private configuration)
83
 *
84
 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
85
 * - programming the UPMs exactly once - is obtained.  Define it to get the
86
 * latter, untrusted behaviour.
87
 */
88
 
89
#------------------------------------------------------------------------------
90
 
91
// LED macro uses r23, r25: r4 left alone
92
#define LED( x ) \
93
        lwi     r25,0xFA100018;         \
94
        lwi     r23,(x);                \
95
        stb     r23,0(r25)
96
 
97
#------------------------------------------------------------------------------
98
 
99
FUNC_START( hal_hardware_init )
100
 
101
        # Throughout this routine, r4 is the base address of the control
102
        # registers.  r3 and r5 are scratch in general.
103
 
104
        lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
105
        mtspr   CYGARC_REG_IMMR,r4
106
 
107
        LED( 0 )                        # turn all LEDs off
108
 
109
#define CACHE_UNLOCKALL         0x0a00
110
#define CACHE_DISABLE           0x0400
111
#define CACHE_INVALIDATEALL     0x0c00
112
#define CACHE_ENABLE            0x0200
113
#define CACHE_ENABLEBIT         0x8000
114
 
115
#define CACHE_FORCEWRITETHROUGH 0x0100
116
#define CACHE_NOWRITETHROUGH    0x0300
117
#define CACHE_CLEAR_LE_SWAP     0x0700
118
 
119
        # DATA CACHE
120
        mfspr   r3,CYGARC_REG_DC_CST            /* clear error bits */
121
        lis     r3,CACHE_UNLOCKALL
122
        sync
123
        mtspr   CYGARC_REG_DC_CST,r3            /* unlock all lines */
124
 
125
        lis     r3,CACHE_INVALIDATEALL
126
        sync
127
        mtspr   CYGARC_REG_DC_CST,r3            /* invalidate all lines */
128
 
129
        lis     r3,CACHE_DISABLE
130
        sync
131
        mtspr   CYGARC_REG_DC_CST,r3            /* disable */
132
 
133
        lis     r3,CACHE_FORCEWRITETHROUGH
134
        sync
135
        mtspr   CYGARC_REG_DC_CST,r3            /* set force-writethrough mode */
136
 
137
        lis     r3,CACHE_CLEAR_LE_SWAP
138
        sync
139
        mtspr   CYGARC_REG_DC_CST,r3            /* clear little-endian swap mode */
140
        /* (dunno what this is, but it sounds like a bad thing) */
141
 
142
        # INSTRUCTION CACHE (no writeback modes)
143
        mfspr   r3,CYGARC_REG_IC_CST            /* clear error bits */
144
        lis     r3,CACHE_UNLOCKALL
145
        mtspr   CYGARC_REG_IC_CST,r3            /* unlock all lines */
146
        isync
147
        lis     r3,CACHE_INVALIDATEALL
148
        mtspr   CYGARC_REG_IC_CST,r3            /* invalidate all lines */
149
        isync
150
        lis     r3,CACHE_DISABLE
151
        mtspr   CYGARC_REG_IC_CST,r3            /* disable */
152
        isync
153
 
154
        sync
155
 
156
        LED( 0x01 )
157
 
158
        /*
159
         * SIU Initialization.
160
         */
161
        lwi     r3,0x00610400
162
        stw     r3,SIUMCR(r4)
163
 
164
#ifdef CYG_HAL_STARTUP_ROMRAM
165
// Need to set the PC into the FLASH (ROM) before the address map changes
166
        lwi     r3,10f
167
        lwi     r5,0xFE000000
168
        or      r3,r3,r5
169
        mtctr   r3
170
        bctr
171
10:
172
#endif
173
 
174
        /*
175
         * Enable bus monitor. Disable Watchdog timer.
176
         */
177
        lwi     r3,0xffffff88
178
        stw     r3,SYPCR(r4)
179
 
180
        /*
181
         * Clear REFA & REFB. Enable but freeze timebase.
182
         */
183
        lwi     r3,0x0000            // FIXME:   should this be 0x0000 or 0x00C2
184
        sth     r3,TBSCR(r4)
185
 
186
        /*
187
         * Unlock some RTC registers (see section 5.11.2)
188
         */
189
        lwi     r3,0x55ccaa33
190
        stw     r3,RTCSCK(r4)
191
        stw     r3,RTCK(r4)
192
        stw     r3,RTSECK(r4)
193
        stw     r3,RTCALK(r4)
194
 
195
        /*
196
         * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
197
         */
198
        li      r3,0x0000            // FIXME:   should this be 0x0000 or 0x00C3
199
        sth     r3,RTCSC(r4)
200
 
201
        /*
202
         * Clear periodic timer interrupt status.
203
         * Enable periodic timer and stop it on freeze.
204
         */
205
        li      r3,0x0001            // FIXME:   should this be 0x0001 or 0x0083
206
        sth     r3,PISCR(r4)
207
 
208
        LED( 0x02 )
209
#ifdef CYGPRI_DO_PROGRAM_UPMS
210
        /*
211
         * Perform UPM programming by writing to its 64 RAM locations.
212
         * Note that UPM initialization must be done before the Bank Register
213
         * initialization. Otherwise, system may hang when writing to Bank
214
         * Registers in certain cases.
215
         */
216
        lis     r5,__upmtbl_start@h
217
        ori     r5,r5,__upmtbl_start@l
218
        lis     r6,__upmtbl_end@h
219
        ori     r6,r6,__upmtbl_end@l
220
        sub     r7,r6,r5      /* size of table */
221
        srawi   r7,r7,2       /* in words */
222
 
223
        li      r6,0x00000000     /* Command - OP=Write, UPMA, MAD=0 */
224
    1:
225
        lwz     r3,0(r5)      /* get data from table */
226
        stw     r3,MDR(r4)    /* store the data to MD register */
227
        stw     r6,MCR(r4)    /* issue command to MCR register */
228
        addi    r5,r5,4       /* next entry in the table */
229
        addi    r6,r6,1       /* next MAD address */
230
        cmpw    r6,r7         /* done yet ? */
231
        blt     1b
232
#endif // CYGPRI_DO_PROGRAM_UPMS
233
        LED( 0x12 )
234
 
235
        /*
236
         * Set refresh timer prescaler to divide by 8.
237
         */
238
        li      r3,PTP_DIV32
239
        sth     r3,MPTPR(r4)
240
 
241
        /*
242
         * See Table 15-16 MPC860 User's Manual.
243
         *
244
// Set the value of Machine A Mode Register (MAMR) to $5E802114.
245
//      Field PTA (bits 0-7) = 94
246
//      Field PTAE (bit 8) = 1
247
//      Field AMA (bits 9-11) = 0
248
//      Field Reserved (bit 12) = 0
249
//      Field DSA (bits 13-14) = 0
250
//      Field Reserved (bit 15) = 0
251
//      Field G0CLA (bits 16-18) = 1
252
//      Field GPL_A4DIS (bit 19) = 0
253
//      Field RLFA (bits 20-23) = 1
254
//      Field WLFA (bits 24-27) = 1
255
//      Field TLFA (bits 28-31) = 4
256
         */
257
 
258
//
259
// PTA field is (System Clock in MHz * Refresh rate in us) / Prescale
260
// e.g.  ((14*3.6864)*62.5)/32 => 100.8 => 101
261
//
262
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47)
263
#define PLPRCR_PTX 0x00C // (47MHz/3.6864MHz)-1
264
#define MAMR_PTA 94
265
#endif
266
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 51)
267
#define PLPRCR_PTX 0x00D // (51.6MHz/3.6864MHz)-1
268
#define MAMR_PTA 101
269
#endif
270
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 55)
271
#define PLPRCR_PTX 0x00E // (55.3MHz/3.6864MHz)-1
272
#define MAMR_PTA 108
273
#endif
274
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 59)
275
#define PLPRCR_PTX 0x00F // (58.9MHz/3.6864MHz)-1
276
#define MAMR_PTA 116
277
#endif
278
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 63)
279
#define PLPRCR_PTX 0x010 // (62.7MHz/3.6864MHz)-1
280
#define MAMR_PTA 123
281
#endif
282
//#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF)
283
        lwi     r3,0x00802114|(MAMR_PTA<<24)
284
        stw     r3,MAMR(r4)
285
        stw     r3,MBMR(r4)
286
 
287
        /*
288
         * Base Register initialization.
289
         */
290
 
291
        /* BOOT ROM */
292
        lwi     r3,0xFE000401   # 8-bit, GPCM
293
        lwi     r5,0xFF800774   # 7 wait states, up to 8MB
294
        stw     r3,BR0(r4)
295
        stw     r5,OR0(r4)
296
 
297
        /* Misc I/O, 16 bit port */
298
        lwi     r3,0xFA100801
299
        lwi     r5,0xFFFF8730
300
        stw     r3,BR2(r4)
301
        stw     r5,OR2(r4)
302
 
303
        /* ONBOARD DRAM */
304
        lwi     r3,0x00000081   # 32-bit, UPMA
305
        lwi     r5,0xFF800E00
306
        stw     r3,BR1(r4)
307
        stw     r5,OR1(r4)
308
 
309
        /* DRAM DIMM BANK1 */
310
        lwi     r3,0x00000080   # 32-bit, UPMA, INVALID
311
        lwi     r5,0xFFFF87FC
312
        stw     r3,BR3(r4)
313
        stw     r5,OR3(r4)
314
 
315
#if 0
316
        /* NVRAM */
317
        lwi     r3,0xfa000401   # 8-bit, GPCM
318
        lwi     r5,0xffe00930
319
        stw     r3,BR4(r4)
320
        stw     r5,OR4(r4)
321
 
322
        /* PCI BRIDGE MEM/IO */
323
        lwi     r3,0x80000001   # 32-bit, GPCM
324
        lwi     r5,0xa0000108
325
        stw     r3,BR5(r4)
326
        stw     r5,OR5(r4)
327
 
328
        /* PCI BRIDGE REGISTERS */
329
        lwi     r3,0xfa210001   # 32-bit, GPCM
330
        lwi     r5,0xffff0108
331
        stw     r3,BR6(r4)
332
        stw     r5,OR6(r4)
333
 
334
        /* FLASH */
335
        lwi     r3,0xfc000001   # 32-bit, GPCM
336
        lwi     r5,0xff800940
337
        stw     r3,BR7(r4)
338
        stw     r5,OR7(r4)
339
#endif
340
 
341
        /*
342
         *  SYSTEM CLOCK CONTROL REGISTER
343
// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
344
//      Field Reserved (bit 0) = 0
345
//      Field COM (bits 1-2) = 0
346
//      Field Reserved (bits 3-5) = 0
347
//      Field TBS (bit 6) = 0
348
//      Field RTDIV (bit 7) = 0
349
//      Field RTSEL (bit 8) = 0
350
//      Field CRQEN (bit 9) = 1
351
//      Field PRQEN (bit 10) = 0
352
//      Field Reserved (bits 11-12) = 0
353
//      Field EBDF (bits 13-14) = 0
354
//      Field Reserved (bits 15-16) = 0
355
//      Field DFSYNC (bits 17-18) = 0
356
//      Field DFBRG (bits 19-20) = 0
357
//      Field DFNL (bits 21-23) = 0
358
//      Field DFNH (bits 24-26) = 0
359
//      Field Reserved (bits 27-31) = 0
360
         */
361
        lwi     r3,0x00400000
362
        stw     r3,SCCR(r4)
363
 
364
        LED( 0x03 )
365
 
366
        /*
367
         *  PLL, LOW POWER, AND RESET CONTROL REGISTER
368
// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
369
//      Field MF (bits 0-11) = 12
370
//      Field Reserved (bits 12-15) = 0
371
//      Field SPLSS (bit 16) = 0
372
//      Field TEXPS (bit 17) = 1
373
//      Field Reserved (bit 18) = 0
374
//      Field TMIST (bit 19) = 0
375
//      Field Reserved (bit 20) = 0
376
//      Field CSRC (bit 21) = 0
377
//      Field LPM (bits 22-23) = 0
378
//      Field CSR (bit 24) = 0
379
//      Field LOLRE (bit 25) = 0
380
//      Field FIOPD (bit 26) = 0
381
//      Field Reserved (bits 27-31) = 0
382
         */
383
        lwi     r3,0x04000|(PLPRCR_PTX<<20)
384
        stw     r3,PLPRCR(r4)
385
 
386
        LED(0xE0)
387
        lwi     r3,0x40000
388
        mtctr   r3
389
10:     nop
390
        bdnz    10b
391
        LED(0xE1)
392
 
393
        /* SDRAM Initialization Sequence, UPMA, CS1 */
394
        li      r3,0
395
        stw     r3,MAR(r4)
396
 
397
        lwi     r3,0x80002115;  /* run precharge from loc 21 (0x15) */
398
        stw     r3,MCR(r4)
399
 
400
        lwi     r3,0x80002830;  /* run refresh 8 times */
401
        stw     r3,MCR(r4)
402
 
403
        lwi     r3,0x88;        /* MR 88 for high range */
404
        stw     r3,MAR(r4)
405
 
406
        lwi     r3,0x80002116;  /* run MRS pattern from loc 22 (0x16) */
407
        stw     r3,MCR(r4)
408
 
409
        # mask interrupt sources in the SIU
410
        lis     r2,0
411
        lwi     r3,CYGARC_REG_IMM_SIMASK
412
        stw     r2,0(r3)
413
 
414
        # set the decrementer to maxint
415
        lwi     r2,0
416
        not     r2,r2
417
        mtdec   r2
418
 
419
        # and enable the timebase and decrementer to make sure
420
        li      r2,1                            # TBEnable and not TBFreeze
421
        lwi     r3,CYGARC_REG_IMM_TBSCR
422
        sth     r2,0(r3)
423
 
424
        LED( 8 )
425
 
426
#ifdef CYG_HAL_STARTUP_ROM
427
        # move return address to where the ROM is
428
        mflr    r3
429
        lwi     r4,0x00FFFFFF        // CAUTION!! Assumes only low 16M for ROM
430
        and     r3,r3,r4
431
        oris    r3,r3,CYGMEM_REGION_rom>>16
432
        mtlr    r3
433
#endif
434
 
435
#ifdef CYG_HAL_STARTUP_ROMRAM
436
        // Copy image from ROM to RAM
437
        LED(0x10)
438
        mflr    r3
439
        lwi     r4,0xFE000000
440
        lwi     r5,0x01FFFFFF   // ROM/FLASH base
441
        and     r3,r3,r5        // segment relative
442
        lwi     r6,_hal_hardware_init_done
443
        mtlr    r6
444
        sub     r6,r3,r6        // Absolute address
445
        add     r6,r6,r4        // FLASH address
446
        lwi     r7,0            // where to copy to
447
        lwi     r8,__ram_data_end
448
10:     lwz     r5,0(r6)
449
        stw     r5,0(r7)
450
        addi    r6,r6,4
451
        addi    r7,r7,4
452
        cmplw   r7,r8
453
        bne     10b
454
        LED(0x20)
455
#endif
456
 
457
        blr
458
FUNC_END( hal_hardware_init )
459
 
460
 
461
#ifdef CYGPRI_DO_PROGRAM_UPMS
462
# -------------------------------------------------------------------------
463
# this table initializes the User Programmable Machine (UPM) nastiness
464
# in the QUICC to control DRAM timing.
465
 
466
__upmtbl_start:
467
// single read   (offset 0x00 in upm ram)
468
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00
469
       .long   0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04
470
// burst read    (offset 0x08 in upm ram)
471
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00
472
       .long   0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44
473
       .long   0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35
474
       .long   0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35
475
// single write  (offset 0x18 in upm ram)
476
       .long   0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47
477
       .long   0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
478
// burst write   (offset 0x20 in upm ram)
479
       .long   0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
480
       .long   0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04
481
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
482
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
483
// refresh       (offset 0x30 in upm ram)
484
       .long   0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04
485
       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
486
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
487
// exception     (offset 0x3C in upm ram)
488
       .long   0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
489
__upmtbl_end:
490
#endif // CYGPRI_DO_PROGRAM_UPMS
491
 
492
FUNC_START(hal_viper_set_led)
493
        lwi     r4,0xFA100018
494
        stb     r3,0(r4)
495
        lwi     r5,_hold_led
496
        stw     r3,0(r5)
497
        blr
498
FUNC_END(hal_viper_set_led)
499
        .data
500
_hold_led:
501
        .long   0
502
        .text
503
 
504
FUNC_START(hal_viper_get_led)
505
        lwi     r5,_hold_led
506
        lwz     r3,0(r5)
507
        blr
508
FUNC_END(hal_viper_get_led)
509
 
510
FUNC_START(hal_viper_flash_led)
511
        lwi     r4,0xFA100018
512
    1:
513
        li      r5,10
514
        stb     r5,0(r4)
515
 
516
        lis     r5,10
517
        mtctr   r5
518
    2:
519
        bdnz    2b
520
 
521
        li      r5,12
522
        stb     r5,0(r4)
523
 
524
        lis     r5,10
525
        mtctr   r5
526
    3:
527
        bdnz    3b
528
 
529
        subi    r3,r3,1
530
        cmpwi   r3,0
531
        bge     1b
532
 
533
        li      r5,6
534
        stb     r5,0(r4)
535
 
536
        lis     r5,20
537
        mtctr   r5
538
    4:
539
        bdnz    4b
540
 
541
        blr
542
FUNC_END(hal_viper_flash_led)
543
 
544
 
545
#------------------------------------------------------------------------------
546
# end of viper.S

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