OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [sh/] [arch/] [v2_0/] [cdl/] [hal_sh.cdl] - Blame information for rev 454

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
# ====================================================================
2
#
3
#      hal_sh.cdl
4
#
5
#      SH architectural HAL package configuration data
6
#
7
# ====================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later version.
16
##
17
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
## for more details.
21
##
22
## You should have received a copy of the GNU General Public License along
23
## with eCos; if not, write to the Free Software Foundation, Inc.,
24
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
##
26
## As a special exception, if other files instantiate templates or use macros
27
## or inline functions from this file, or you compile this file and link it
28
## with other works to produce a work based on this file, this file does not
29
## by itself cause the resulting work to be covered by the GNU General Public
30
## License. However the source code for this file must still be made available
31
## in accordance with section (3) of the GNU General Public License.
32
##
33
## This exception does not invalidate any other reasons why a work based on
34
## this file might be covered by the GNU General Public License.
35
##
36
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
## at http://sources.redhat.com/ecos/ecos-license/
38
## -------------------------------------------
39
#####ECOSGPLCOPYRIGHTEND####
40
# ====================================================================
41
######DESCRIPTIONBEGIN####
42
#
43
# Author(s):      jskov
44
# Original data:  jskov
45
# Contributors:
46
# Date:           1999-10-29
47
#
48
#####DESCRIPTIONEND####
49
#
50
# ====================================================================
51
 
52
cdl_package CYGPKG_HAL_SH {
53
    display       "SH architecture"
54
    parent        CYGPKG_HAL
55
    hardware
56
    include_dir   cyg/hal
57
    define_header hal_sh.h
58
    description   "
59
        The SH (SuperH) architecture HAL package provides generic
60
        support for this processor architecture. It is also
61
        necessary to select a specific target platform HAL
62
        package."
63
 
64
    compile       hal_misc.c context.S sh_stub.c
65
 
66
    # The "-o file" is a workaround for CR100958 - without it the
67
    # output file would end up in the source directory under CygWin.
68
    # n.b. grep does not behave itself under win32
69
    make -priority 1 {
70
        /include/cyg/hal/sh_offsets.inc : /src/hal_mk_defs.c
71
        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh_offsets.tmp -o hal_mk_defs.tmp -S $<
72
        fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
73
        @echo $@ ": \\" > $(notdir $@).deps
74
        @tail +2 sh_offsets.tmp >> $(notdir $@).deps
75
        @echo >> $(notdir $@).deps
76
        @rm sh_offsets.tmp hal_mk_defs.tmp
77
    }
78
 
79
    make {
80
        /lib/vectors.o : /src/vectors.S
81
        $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
82
        @echo $@ ": \\" > $(notdir $@).deps
83
        @tail +2 vectors.tmp >> $(notdir $@).deps
84
        @echo >> $(notdir $@).deps
85
        @rm vectors.tmp
86
    }
87
 
88
    make {
89
        /lib/target.ld: /src/sh.ld
90
        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
91
        @echo $@ ": \\" > $(notdir $@).deps
92
        @tail +2 target.tmp >> $(notdir $@).deps
93
        @echo >> $(notdir $@).deps
94
        @rm target.tmp
95
    }
96
 
97
    cdl_interface CYGINT_HAL_SH_DMA_CHANNELS {
98
        display       "Number of DMA channels"
99
    }
100
 
101
    cdl_interface CYGINT_HAL_SH_DMA_CHANNELS_USED {
102
        display       "Number of requested DMA channels"
103
        requires      CYGINT_HAL_SH_DMA_CHANNELS_USED <= CYGINT_HAL_SH_DMA_CHANNELS
104
        description   "
105
            Various drivers may request use of a DMA channel, but only
106
            so many are available. These interfaces make sure the
107
            DMA resources are not overcommitted."
108
    }
109
 
110
    cdl_component CYGPKG_HAL_SH_CPU {
111
        display          "CPU type and endian mode controls"
112
        flavor     none
113
        no_define
114
        description      "
115
            CPU type and endian mode can be selected using these option."
116
 
117
        cdl_interface CYGINT_HAL_SH_VARIANT {
118
            display  "Number of variant implementations in this configuration"
119
            no_define
120
            requires 1 == CYGINT_HAL_SH_VARIANT
121
        }
122
 
123
        cdl_option CYGHWR_HAL_SH_FPU {
124
            display       "Variant FPU support"
125
            default_value 0
126
        }
127
 
128
        cdl_option CYGHWR_HAL_SH_NO_FPU {
129
            display       "Variant has no FPU support"
130
            calculated    !CYGHWR_HAL_SH_FPU
131
        }
132
 
133
        cdl_option CYGHWR_HAL_SH_BIGENDIAN {
134
            display          "Use big-endian mode"
135
            default_value    { (CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT != 0) \
136
                                ? 1 : 0 }
137
            description      "
138
                Use the CPU in big-endian mode."
139
        }
140
 
141
        cdl_interface CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT {
142
            display          "Platform wants default BE"
143
            no_define
144
            description      "
145
                This interface is set by the platform, not by the user,
146
                to indicate what the default endianness should be."
147
        }
148
    }
149
 
150
    cdl_component CYGPKG_HAL_SH_CACHE {
151
        display          "Cache controls"
152
        flavor     none
153
        no_define
154
        description      "
155
            Initial cache settings can be specified using these options."
156
 
157
        cdl_option CYGHWR_HAL_SH_CACHE_ENABLE {
158
            display       "Enable cache on startup"
159
            default_value 1
160
            description "
161
                Controls whether caches should be enabled on startup."
162
        }
163
    }
164
 
165
    # Real-time clock/counter specifics
166
    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
167
        display       "Real-time clock constants."
168
        description   "
169
            The NUMERATOR divided by the DENOMINATOR gives the number of
170
            nanoseconds per tick. The PERIOD is the divider to be programmed
171
            into a hardware timer that is driven from an appropriate hardware
172
            clock, such that the timer overflows once per tick (normally
173
            generating a CPU interrupt to mark the end of a tick). The tick
174
            rate is typically 100Hz.
175
            The SH HAL uses TMU counter 0 for driving the real-time
176
            clock."
177
        flavor        none
178
 
179
        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
180
            display       "Real-time clock numerator"
181
            flavor        data
182
            calculated    1000000000
183
        }
184
        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
185
            display       "Real-time clock denominator"
186
            flavor        data
187
            calculated    100
188
        }
189
        cdl_option CYGNUM_HAL_RTC_PERIOD {
190
            display       "Real-time clock period"
191
            flavor        data
192
            calculated    { CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/CYGNUM_HAL_RTC_DENOMINATOR / CYGHWR_HAL_SH_RTC_PRESCALE }
193
        }
194
    }
195
 
196
    cdl_option CYGBLD_LINKER_SCRIPT {
197
        display "Linker script"
198
        flavor data
199
        no_define
200
        calculated  { "src/sh.ld" }
201
    }
202
 
203
    cdl_option CYGPKG_HAL_SH_TESTS {
204
        display "SH tests"
205
        flavor  data
206
        no_define
207
        calculated { "tests/intr0" }
208
        description   "
209
            This option specifies the set of tests for the SH HAL."
210
    }
211
 
212
    cdl_component CYGBLD_HAL_SH_BSP_SYSCALL {
213
        display       "Build BSP syscall support file"
214
        default_value 1
215
        active_if     CYGSEM_REDBOOT_BSP_SYSCALLS
216
        description   "
217
            When the RedBoot option for supporting syscalls is enabled,
218
            build the SH architecture support file."
219
 
220
        compile       hal_syscall.c
221
    }
222
 
223
    cdl_component CYGPKG_REDBOOT_SH_OPTIONS {
224
        display       "Redboot for SuperH options"
225
        flavor        none
226
        no_define
227
        parent        CYGPKG_REDBOOT
228
        active_if     CYGPKG_REDBOOT
229
        description   "
230
            This option lists the target's requirements for a valid Redboot
231
            configuration."
232
 
233
        cdl_component CYGSEM_REDBOOT_SH_LINUX_BOOT {
234
            active_if      CYGBLD_BUILD_REDBOOT_WITH_EXEC
235
            display        "Support booting Linux via RedBoot"
236
            flavor         bool
237
            default_value  1
238
            description    "
239
               This option enables RedBoot to support booting of a Linux kernel."
240
            compile -library=libextras.a redboot_linux_exec.c
241
 
242
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_ENTRY {
243
                display        "Default kernel entry address"
244
                flavor         data
245
                default_value  0x8c102000
246
            }
247
 
248
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_BASE_ADDR {
249
                display        "Default parameter block address"
250
                flavor         data
251
                default_value  0x8c101000
252
            }
253
 
254
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_MOUNT_RDONLY {
255
                display        "Default MOUNT_RDONLY"
256
                flavor         data
257
                default_value  0
258
            }
259
 
260
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_RAMDISK_FLAGS {
261
                display        "Default RAMDISK_FLAGS"
262
                flavor         data
263
                default_value  0
264
            }
265
 
266
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_ORIG_ROOT_DEV {
267
                display        "Default ORIG_ROOT_DEV"
268
                flavor         data
269
                default_value  0
270
            }
271
 
272
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_LOADER_TYPE {
273
                display        "Default LOADER_TYPE"
274
                flavor         data
275
                default_value  0
276
            }
277
 
278
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_INITRD_START {
279
                display        "Default INITRD_START"
280
                flavor         data
281
                default_value  0
282
            }
283
 
284
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_INITRD_SIZE {
285
                display        "Default INITRD_SIZE"
286
                flavor         data
287
                default_value  0
288
            }
289
 
290
            cdl_option CYGDAT_REDBOOT_SH_LINUX_BOOT_COMMAND_LINE {
291
                display        "Default COMMAND_LINE"
292
                flavor         data
293
                default_value  { "console=ttySC1,38400" }
294
            }
295
        }
296
    }
297
}
298
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.