| 1 |
27 |
unneback |
#ifndef CYGONCE_HAL_INTR_H
|
| 2 |
|
|
#define CYGONCE_HAL_INTR_H
|
| 3 |
|
|
|
| 4 |
|
|
//==========================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// hal_intr.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// HAL Interrupt and clock support
|
| 9 |
|
|
//
|
| 10 |
|
|
//==========================================================================
|
| 11 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 21 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 26 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 30 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 31 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 32 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 33 |
|
|
// License. However the source code for this file must still be made available
|
| 34 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 37 |
|
|
// this file might be covered by the GNU General Public License.
|
| 38 |
|
|
//
|
| 39 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 40 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 41 |
|
|
// -------------------------------------------
|
| 42 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 43 |
|
|
//==========================================================================
|
| 44 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 45 |
|
|
//
|
| 46 |
|
|
// Author(s): jskov
|
| 47 |
|
|
// Contributors: jskov,
|
| 48 |
|
|
// Date: 1999-04-24
|
| 49 |
|
|
// Purpose: Define Interrupt support
|
| 50 |
|
|
// Description: The macros defined here provide the HAL APIs for handling
|
| 51 |
|
|
// interrupts and the clock.
|
| 52 |
|
|
//
|
| 53 |
|
|
// Usage:
|
| 54 |
|
|
// #include <cyg/hal/hal_intr.h>
|
| 55 |
|
|
// ...
|
| 56 |
|
|
//
|
| 57 |
|
|
//
|
| 58 |
|
|
//####DESCRIPTIONEND####
|
| 59 |
|
|
//
|
| 60 |
|
|
//==========================================================================
|
| 61 |
|
|
|
| 62 |
|
|
#include <pkgconf/hal.h>
|
| 63 |
|
|
|
| 64 |
|
|
#include <cyg/hal/var_intr.h>
|
| 65 |
|
|
|
| 66 |
|
|
// More include statements below. First part of this file must be
|
| 67 |
|
|
// usable for both assembly and C files, so only use defines here.
|
| 68 |
|
|
|
| 69 |
|
|
#include CYGBLD_HAL_VAR_INTR_MODEL_H
|
| 70 |
|
|
|
| 71 |
|
|
#ifndef __ASSEMBLER__
|
| 72 |
|
|
|
| 73 |
|
|
#include <cyg/infra/cyg_type.h>
|
| 74 |
|
|
|
| 75 |
|
|
#include <cyg/hal/sh_regs.h> // register definitions
|
| 76 |
|
|
#include <cyg/hal/hal_io.h> // io macros
|
| 77 |
|
|
#include <cyg/infra/cyg_ass.h> // CYG_FAIL
|
| 78 |
|
|
|
| 79 |
|
|
//--------------------------------------------------------------------------
|
| 80 |
|
|
// Static data used by HAL
|
| 81 |
|
|
|
| 82 |
|
|
// ISR tables
|
| 83 |
|
|
externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
|
| 84 |
|
|
externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
|
| 85 |
|
|
externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
|
| 86 |
|
|
// VSR table
|
| 87 |
|
|
externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
|
| 88 |
|
|
|
| 89 |
|
|
//--------------------------------------------------------------------------
|
| 90 |
|
|
// Default ISR
|
| 91 |
|
|
// The #define is used to test whether this routine exists, and to allow
|
| 92 |
|
|
// us to call it.
|
| 93 |
|
|
|
| 94 |
|
|
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
|
| 95 |
|
|
|
| 96 |
|
|
#define HAL_DEFAULT_ISR hal_default_isr
|
| 97 |
|
|
|
| 98 |
|
|
//--------------------------------------------------------------------------
|
| 99 |
|
|
// Interrupt state storage
|
| 100 |
|
|
|
| 101 |
|
|
typedef cyg_uint32 CYG_INTERRUPT_STATE;
|
| 102 |
|
|
|
| 103 |
|
|
//--------------------------------------------------------------------------
|
| 104 |
|
|
// Interrupt control macros
|
| 105 |
|
|
//
|
| 106 |
|
|
// Note that these macros control interrupt state by setting the Imask
|
| 107 |
|
|
// of the SR rather than the (more obvious) BL. This is because a CPU
|
| 108 |
|
|
// reset is forced if execptions (such as breakpoints) are generated
|
| 109 |
|
|
// while the BL flag is set.
|
| 110 |
|
|
|
| 111 |
|
|
#define HAL_DISABLE_INTERRUPTS(_old_) \
|
| 112 |
|
|
CYG_MACRO_START \
|
| 113 |
|
|
cyg_uint32 _tmp_; \
|
| 114 |
|
|
asm volatile ( \
|
| 115 |
|
|
"stc sr,%1 \n\t" \
|
| 116 |
|
|
"mov %2,%0 \n\t" \
|
| 117 |
|
|
"and %1,%0 \n\t" \
|
| 118 |
|
|
"or %2,%1 \n\t" \
|
| 119 |
|
|
"ldc %1,sr \n\t" \
|
| 120 |
|
|
: "=&r"(_old_), "=&r" (_tmp_) \
|
| 121 |
|
|
: "r" (CYGARC_REG_SR_IMASK) \
|
| 122 |
|
|
); \
|
| 123 |
|
|
CYG_MACRO_END
|
| 124 |
|
|
|
| 125 |
|
|
#define HAL_ENABLE_INTERRUPTS() \
|
| 126 |
|
|
CYG_MACRO_START \
|
| 127 |
|
|
cyg_uint32 _tmp_; \
|
| 128 |
|
|
asm volatile ( \
|
| 129 |
|
|
"stc sr,%0 \n\t" \
|
| 130 |
|
|
"and %1,%0 \n\t" \
|
| 131 |
|
|
"ldc %0,sr \n\t" \
|
| 132 |
|
|
: "=&r" (_tmp_) \
|
| 133 |
|
|
: "r" (~CYGARC_REG_SR_IMASK) \
|
| 134 |
|
|
); \
|
| 135 |
|
|
CYG_MACRO_END
|
| 136 |
|
|
|
| 137 |
|
|
#define HAL_RESTORE_INTERRUPTS(_old_) \
|
| 138 |
|
|
CYG_MACRO_START \
|
| 139 |
|
|
cyg_uint32 _tmp1_, _tmp2_; \
|
| 140 |
|
|
asm volatile ( \
|
| 141 |
|
|
"stc sr,%0 \n\t" \
|
| 142 |
|
|
"and %3,%0 \n\t" \
|
| 143 |
|
|
"not %3,%1 \n\t" \
|
| 144 |
|
|
"and %2,%1 \n\t" \
|
| 145 |
|
|
"or %1,%0 \n\t" \
|
| 146 |
|
|
"ldc %0,sr \n\t" \
|
| 147 |
|
|
: "=&r" (_tmp1_), "=&r" (_tmp2_) \
|
| 148 |
|
|
: "r" (_old_), "r" (~CYGARC_REG_SR_IMASK) \
|
| 149 |
|
|
); \
|
| 150 |
|
|
CYG_MACRO_END
|
| 151 |
|
|
|
| 152 |
|
|
#define HAL_QUERY_INTERRUPTS(_old_) \
|
| 153 |
|
|
CYG_MACRO_START \
|
| 154 |
|
|
asm volatile ( \
|
| 155 |
|
|
"stc sr,%0 \n\t" \
|
| 156 |
|
|
"and %1,%0 \n\t" \
|
| 157 |
|
|
: "=&r"(_old_) \
|
| 158 |
|
|
: "r" (CYGARC_REG_SR_IMASK) \
|
| 159 |
|
|
); \
|
| 160 |
|
|
CYG_MACRO_END
|
| 161 |
|
|
|
| 162 |
|
|
//--------------------------------------------------------------------------
|
| 163 |
|
|
// Vector translation.
|
| 164 |
|
|
|
| 165 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
| 166 |
|
|
|
| 167 |
|
|
# define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
|
| 168 |
|
|
|
| 169 |
|
|
#else
|
| 170 |
|
|
|
| 171 |
|
|
# define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
|
| 172 |
|
|
|
| 173 |
|
|
#endif
|
| 174 |
|
|
|
| 175 |
|
|
//--------------------------------------------------------------------------
|
| 176 |
|
|
// Routine to execute DSRs using separate interrupt stack
|
| 177 |
|
|
|
| 178 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 179 |
|
|
|
| 180 |
|
|
externC void hal_interrupt_stack_call_pending_DSRs(void);
|
| 181 |
|
|
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
|
| 182 |
|
|
hal_interrupt_stack_call_pending_DSRs()
|
| 183 |
|
|
|
| 184 |
|
|
// these are offered solely for stack usage testing
|
| 185 |
|
|
// if they are not defined, then there is no interrupt stack.
|
| 186 |
|
|
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
|
| 187 |
|
|
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
|
| 188 |
|
|
// use them to declare these extern however you want:
|
| 189 |
|
|
// extern char HAL_INTERRUPT_STACK_BASE[];
|
| 190 |
|
|
// extern char HAL_INTERRUPT_STACK_TOP[];
|
| 191 |
|
|
// is recommended
|
| 192 |
|
|
#endif
|
| 193 |
|
|
|
| 194 |
|
|
//--------------------------------------------------------------------------
|
| 195 |
|
|
// Interrupt and VSR attachment macros
|
| 196 |
|
|
|
| 197 |
|
|
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
|
| 198 |
|
|
CYG_MACRO_START \
|
| 199 |
|
|
cyg_uint32 _index_; \
|
| 200 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 201 |
|
|
\
|
| 202 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
|
| 203 |
|
|
(_state_) = 0; \
|
| 204 |
|
|
else \
|
| 205 |
|
|
(_state_) = 1; \
|
| 206 |
|
|
CYG_MACRO_END
|
| 207 |
|
|
|
| 208 |
|
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
|
| 209 |
|
|
CYG_MACRO_START \
|
| 210 |
|
|
cyg_uint32 _index_; \
|
| 211 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 212 |
|
|
\
|
| 213 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
|
| 214 |
|
|
{ \
|
| 215 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
|
| 216 |
|
|
hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
|
| 217 |
|
|
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
|
| 218 |
|
|
} \
|
| 219 |
|
|
CYG_MACRO_END
|
| 220 |
|
|
|
| 221 |
|
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
|
| 222 |
|
|
CYG_MACRO_START \
|
| 223 |
|
|
cyg_uint32 _index_; \
|
| 224 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 225 |
|
|
\
|
| 226 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
|
| 227 |
|
|
{ \
|
| 228 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
|
| 229 |
|
|
hal_interrupt_data[_index_] = 0; \
|
| 230 |
|
|
hal_interrupt_objects[_index_] = 0; \
|
| 231 |
|
|
} \
|
| 232 |
|
|
CYG_MACRO_END
|
| 233 |
|
|
|
| 234 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 235 |
|
|
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
|
| 236 |
|
|
|
| 237 |
|
|
|
| 238 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
|
| 239 |
|
|
CYG_MACRO_START \
|
| 240 |
|
|
if( _poldvsr_ != NULL ) \
|
| 241 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 242 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 243 |
|
|
CYG_MACRO_END
|
| 244 |
|
|
|
| 245 |
|
|
// This is an ugly name, but what it means is: grab the VSR back to eCos
|
| 246 |
|
|
// internal handling, or if you like, the default handler. But if
|
| 247 |
|
|
// cooperating with GDB and CygMon, the default behaviour is to pass most
|
| 248 |
|
|
// exceptions to CygMon. This macro undoes that so that eCos handles the
|
| 249 |
|
|
// exception. So use it with care.
|
| 250 |
|
|
|
| 251 |
|
|
externC void cyg_hal_default_interrupt_vsr( void );
|
| 252 |
|
|
externC void cyg_hal_default_exception_vsr( void );
|
| 253 |
|
|
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
|
| 254 |
|
|
CYG_MACRO_START \
|
| 255 |
|
|
if( (void*)_poldvsr_ != (void*)NULL ) \
|
| 256 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 257 |
|
|
hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
|
| 258 |
|
|
? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
|
| 259 |
|
|
: (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
|
| 260 |
|
|
CYG_MACRO_END
|
| 261 |
|
|
|
| 262 |
|
|
|
| 263 |
|
|
//--------------------------------------------------------------------------
|
| 264 |
|
|
// Interrupt controller(s) access
|
| 265 |
|
|
//
|
| 266 |
|
|
|
| 267 |
|
|
externC void hal_interrupt_set_level(int, int);
|
| 268 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
|
| 269 |
|
|
hal_interrupt_set_level(_vector_, _level_);
|
| 270 |
|
|
|
| 271 |
|
|
externC void hal_interrupt_mask(int);
|
| 272 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 273 |
|
|
hal_interrupt_mask(_vector_);
|
| 274 |
|
|
|
| 275 |
|
|
externC void hal_interrupt_unmask(int);
|
| 276 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 277 |
|
|
hal_interrupt_unmask(_vector_);
|
| 278 |
|
|
|
| 279 |
|
|
externC void hal_interrupt_acknowledge(int);
|
| 280 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 281 |
|
|
hal_interrupt_acknowledge(_vector_);
|
| 282 |
|
|
|
| 283 |
|
|
externC void hal_interrupt_configure(int, int, int);
|
| 284 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
|
| 285 |
|
|
hal_interrupt_configure(_vector_, _level_, _up_);
|
| 286 |
|
|
|
| 287 |
|
|
#endif // __ASSEMBLER__
|
| 288 |
|
|
|
| 289 |
|
|
//--------------------------------------------------------------------------
|
| 290 |
|
|
#endif // ifndef CYGONCE_HAL_INTR_H
|
| 291 |
|
|
// End of hal_intr.h
|
