1 |
27 |
unneback |
#ifndef CYGONCE_HAL_VAR_BANK_H
|
2 |
|
|
#define CYGONCE_HAL_VAR_BANK_H
|
3 |
|
|
//=============================================================================
|
4 |
|
|
//
|
5 |
|
|
// hal_var_bank.h
|
6 |
|
|
//
|
7 |
|
|
// Architecture abstractions for variants with banked registers
|
8 |
|
|
//
|
9 |
|
|
//=============================================================================
|
10 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
11 |
|
|
// -------------------------------------------
|
12 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
13 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
14 |
|
|
//
|
15 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
16 |
|
|
// the terms of the GNU General Public License as published by the Free
|
17 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
18 |
|
|
//
|
19 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
20 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
21 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
22 |
|
|
// for more details.
|
23 |
|
|
//
|
24 |
|
|
// You should have received a copy of the GNU General Public License along
|
25 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
26 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
27 |
|
|
//
|
28 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
29 |
|
|
// or inline functions from this file, or you compile this file and link it
|
30 |
|
|
// with other works to produce a work based on this file, this file does not
|
31 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
32 |
|
|
// License. However the source code for this file must still be made available
|
33 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
34 |
|
|
//
|
35 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
36 |
|
|
// this file might be covered by the GNU General Public License.
|
37 |
|
|
//
|
38 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
39 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
40 |
|
|
// -------------------------------------------
|
41 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
42 |
|
|
//=============================================================================
|
43 |
|
|
//#####DESCRIPTIONBEGIN####
|
44 |
|
|
//
|
45 |
|
|
// Author(s): jskov
|
46 |
|
|
// Contributors:jskov
|
47 |
|
|
// Date: 2002-01-11
|
48 |
|
|
// Purpose: Architecture abstractions for variants with banked registers
|
49 |
|
|
//
|
50 |
|
|
//####DESCRIPTIONEND####
|
51 |
|
|
//
|
52 |
|
|
//=============================================================================
|
53 |
|
|
|
54 |
|
|
//-----------------------------------------------------------------------------
|
55 |
|
|
// Processor saved states:
|
56 |
|
|
|
57 |
|
|
typedef struct
|
58 |
|
|
{
|
59 |
|
|
// These are common to all saved states
|
60 |
|
|
cyg_uint32 r[16]; // Data regs
|
61 |
|
|
cyg_uint32 macl; // Multiply and accumulate - low
|
62 |
|
|
cyg_uint32 mach; // Multiply and accumulate - high
|
63 |
|
|
cyg_uint32 pr; // Procedure Reg
|
64 |
|
|
cyg_uint32 sr; // Status Reg
|
65 |
|
|
cyg_uint32 pc; // Program Counter
|
66 |
|
|
|
67 |
|
|
// This marks the limit of state saved during a context switch and
|
68 |
|
|
// is used to calculate necessary stack allocation for context switches.
|
69 |
|
|
// It would probably be better to have a union instead...
|
70 |
|
|
cyg_uint32 context_size[0];
|
71 |
|
|
|
72 |
|
|
// These are only saved on interrupts
|
73 |
|
|
cyg_uint32 vbr; // Vector Base Register
|
74 |
|
|
cyg_uint32 gbr; // Global Base Register
|
75 |
|
|
|
76 |
|
|
// These are only saved on interrupts
|
77 |
|
|
cyg_uint32 event; // EXCEVT or INTEVT
|
78 |
|
|
} HAL_SavedRegisters;
|
79 |
|
|
|
80 |
|
|
//-----------------------------------------------------------------------------
|
81 |
|
|
// Context Initialization
|
82 |
|
|
// Initialize the context of a thread.
|
83 |
|
|
// Arguments:
|
84 |
|
|
// _sparg_ name of variable containing current sp, will be written with new sp
|
85 |
|
|
// _thread_ thread object address, passed as argument to entry point
|
86 |
|
|
// _entry_ entry point address.
|
87 |
|
|
// _id_ bit pattern used in initializing registers, for debugging.
|
88 |
|
|
|
89 |
|
|
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
|
90 |
|
|
CYG_MACRO_START \
|
91 |
|
|
register HAL_SavedRegisters *_regs_; \
|
92 |
|
|
int _i_; \
|
93 |
|
|
_regs_ = (HAL_SavedRegisters *)((_sparg_) - sizeof(HAL_SavedRegisters)); \
|
94 |
|
|
for( _i_ = 0; _i_ < 16; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \
|
95 |
|
|
(_regs_)->r[15] = (CYG_WORD)(_regs_); /* SP = top of stack */ \
|
96 |
|
|
(_regs_)->r[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \
|
97 |
|
|
(_regs_)->mach = 0; /* MACH = 0 */ \
|
98 |
|
|
(_regs_)->macl = 0; /* MACL = 0 */ \
|
99 |
|
|
(_regs_)->pr = (CYG_WORD)(_entry_); /* PR = entry point */ \
|
100 |
|
|
(_regs_)->sr = 0; /* SR = enable interrupts */ \
|
101 |
|
|
(_regs_)->pc = (CYG_WORD)(_entry_); /* set PC for thread dbg */ \
|
102 |
|
|
_sparg_ = (CYG_ADDRESS)_regs_; \
|
103 |
|
|
CYG_MACRO_END
|
104 |
|
|
|
105 |
|
|
//-----------------------------------------------------------------------------
|
106 |
|
|
// Thread register state manipulation for GDB support.
|
107 |
|
|
|
108 |
|
|
// Translate a stack pointer as saved by the thread context macros above into
|
109 |
|
|
// a pointer to a HAL_SavedRegisters structure.
|
110 |
|
|
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
|
111 |
|
|
(_regs_) = (HAL_SavedRegisters *)(_sp_)
|
112 |
|
|
|
113 |
|
|
// Copy a set of registers from a HAL_SavedRegisters structure into a
|
114 |
|
|
// GDB ordered array.
|
115 |
|
|
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
|
116 |
|
|
CYG_MACRO_START \
|
117 |
|
|
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
|
118 |
|
|
int _i_; \
|
119 |
|
|
\
|
120 |
|
|
for( _i_ = 0; _i_ < 16; _i_++ ) \
|
121 |
|
|
_regval_[_i_] = (_regs_)->r[_i_]; \
|
122 |
|
|
\
|
123 |
|
|
_regval_[16] = (_regs_)->pc; \
|
124 |
|
|
_regval_[17] = (_regs_)->pr; \
|
125 |
|
|
_regval_[18] = (_regs_)->gbr; \
|
126 |
|
|
_regval_[19] = (_regs_)->vbr; \
|
127 |
|
|
_regval_[20] = (_regs_)->mach; \
|
128 |
|
|
_regval_[21] = (_regs_)->macl; \
|
129 |
|
|
_regval_[22] = (_regs_)->sr; \
|
130 |
|
|
\
|
131 |
|
|
/* 23-51 not used atm. */ \
|
132 |
|
|
CYG_MACRO_END
|
133 |
|
|
|
134 |
|
|
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
|
135 |
|
|
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
|
136 |
|
|
CYG_MACRO_START \
|
137 |
|
|
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
|
138 |
|
|
int _i_; \
|
139 |
|
|
\
|
140 |
|
|
for( _i_ = 0; _i_ < 16; _i_++ ) \
|
141 |
|
|
(_regs_)->r[_i_] = _regval_[_i_]; \
|
142 |
|
|
\
|
143 |
|
|
(_regs_)->pc = _regval_[16]; \
|
144 |
|
|
(_regs_)->pr = _regval_[17]; \
|
145 |
|
|
(_regs_)->gbr = _regval_[18]; \
|
146 |
|
|
(_regs_)->vbr = _regval_[19]; \
|
147 |
|
|
(_regs_)->mach = _regval_[20]; \
|
148 |
|
|
(_regs_)->macl = _regval_[21]; \
|
149 |
|
|
(_regs_)->sr = _regval_[22]; \
|
150 |
|
|
CYG_MACRO_END
|
151 |
|
|
|
152 |
|
|
//--------------------------------------------------------------------------
|
153 |
|
|
// CPU address space translation macros
|
154 |
|
|
#define CYGARC_BUS_ADDRESS(x) ((CYG_ADDRWORD)(x) & 0x1fffffff)
|
155 |
|
|
#define CYGARC_CACHED_ADDRESS(x) (CYGARC_BUS_ADDRESS(x)|0x80000000)
|
156 |
|
|
#define CYGARC_UNCACHED_ADDRESS(x) (CYGARC_BUS_ADDRESS(x)|0xa0000000)
|
157 |
|
|
|
158 |
|
|
//-----------------------------------------------------------------------------
|
159 |
|
|
#endif // CYGONCE_HAL_VAR_BANK_H
|
160 |
|
|
// End of hal_var_bank.h
|